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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:10.7930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20c04e73-dadd-4aea-f9b2-08dc90409991 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7885 There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan Acked-by: Rafael J. Wysocki Acked-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e022e6eb766c..384739d592af 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -781,6 +781,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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This simplifies the code and improves readability by using a standard kernel function for boolean string conversion. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/cpufreq.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index a45aac17c20f..1fdabb660231 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -614,10 +614,9 @@ static ssize_t show_boost(struct kobject *kobj, static ssize_t store_boost(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { - int ret, enable; + bool enable; - ret = sscanf(buf, "%d", &enable); - if (ret != 1 || enable < 0 || enable > 1) + if (kstrtobool(buf, &enable)) return -EINVAL; if (cpufreq_boost_trigger_state(enable)) { @@ -641,10 +640,10 @@ static ssize_t show_local_boost(struct cpufreq_policy *policy, char *buf) static ssize_t store_local_boost(struct cpufreq_policy *policy, const char *buf, size_t count) { - int ret, enable; + int ret; + bool enable; - ret = kstrtoint(buf, 10, &enable); - if (ret || enable < 0 || enable > 1) + if (kstrtobool(buf, &enable)) return -EINVAL; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:12.5132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8de26509-2c17-4ef3-d79d-08dc90409a9a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6321 Introduce a new init_boost callback in cpufreq to initialize the boost state for specific pstate drivers. This initialization is required before calling the set_boost interface for each CPU. The init_boost callback will set up and synchronize each CPU's current boost state before invoking the set_boost function. Without this step, the boost state may be inconsistent across CPUs. Signed-off-by: Perry Yuan --- drivers/cpufreq/cpufreq.c | 13 +++++++++++-- include/linux/cpufreq.h | 2 ++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 1fdabb660231..64c6770e24c8 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -1429,8 +1429,17 @@ static int cpufreq_online(unsigned int cpu) goto out_free_policy; } - /* Let the per-policy boost flag mirror the cpufreq_driver boost during init */ - policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); + /* init boost state to prepare set_boost callback for each CPU */ + if (cpufreq_driver->init_boost) { + ret = cpufreq_driver->init_boost(policy); + if (ret) + pr_debug("%s: %d: boost initialization failed\n", __func__, + __LINE__); + goto out_offline_policy; + } else { + /* Let the per-policy boost flag mirror the cpufreq_driver boost during init */ + policy->boost_enabled = cpufreq_boost_enabled() && policy_has_boost_freq(policy); + } /* * The initialization has succeeded and the policy is online. diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 20f7e98ee8af..0698c0292d8f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -409,6 +409,8 @@ struct cpufreq_driver { bool boost_enabled; int (*set_boost)(struct cpufreq_policy *policy, int state); + /* initialize boost state to be consistent before calling set_boost */ + int (*init_boost)(struct cpufreq_policy *policy); /* * Set by drivers that want to register with the energy model after the * policy is properly initialized, but before the governor is started. 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Wed, 19 Jun 2024 09:17:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB59.mail.protection.outlook.com (10.167.241.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Wed, 19 Jun 2024 09:17:12 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 19 Jun 2024 04:17:09 -0500 From: Perry Yuan To: , , , CC: , , , , Subject: [PATCH v12 4/9] cpufreq: amd-pstate: initialize new core precision boost state Date: Wed, 19 Jun 2024 17:16:37 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB59:EE_|MN0PR12MB6320:EE_ X-MS-Office365-Filtering-Correlation-Id: e891e51f-1d8a-4d1d-b166-08dc90409acc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|82310400023|1800799021; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:12.8399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e891e51f-1d8a-4d1d-b166-08dc90409acc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6320 From: Perry Yuan Add one global `global_params` to represent CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. The active, guided and passive modes of the amd-pstate driver can support frequency boost control when the "Core Performance Boost" (CPB) feature is enabled in the BIOS. When enabled in BIOS, the user has an option at runtime to allow/disallow the cores from operating in the boost frequency range. Add an amd_pstate_global_params object to record whether CPB is enabled in BIOS, and if it has been activated by the user Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 59 +++++++++++++++++++++++++++++------- drivers/cpufreq/amd-pstate.h | 13 ++++++++ 2 files changed, 61 insertions(+), 11 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5bdcdd3ea163..0c50b8ba16b6 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -102,6 +102,8 @@ static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); /* * AMD Energy Preference Performance (EPP) @@ -694,7 +696,7 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) if (!cpudata->boost_supported) { pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; + return -ENOTSUPP; } if (state) @@ -712,18 +714,38 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) return 0; } -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_boost_set(struct amd_cpudata *cpudata) { - u32 highest_perf, nominal_perf; + u64 boost_val; + int ret = -1; - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); + if (!cpu_feature_enabled(X86_FEATURE_CPB)) { + pr_debug_once("Boost CPB capabilities not present in the processor\n"); + ret = -EOPNOTSUPP; + goto exit_err; + } - if (highest_perf <= nominal_perf) - return; + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + ret = -EIO; + goto exit_err; + } + + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); + if (amd_pstate_global_params.cpb_supported) { + current_pstate_driver->boost_enabled = true; + WRITE_ONCE(cpudata->boost_supported, true); + } - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; + return 0; + +exit_err: + WRITE_ONCE(cpudata->boost_supported, false); + current_pstate_driver->boost_enabled = false; + amd_pstate_global_params.cpb_boost = false; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -1005,7 +1027,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1387,6 +1408,21 @@ static bool amd_pstate_acpi_pm_profile_undefined(void) return false; } +static int amd_pstate_init_boost(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int ret; + + /* initialize cpu cores boot state */ + ret = amd_pstate_boost_set(cpudata); + if (ret) + return ret; + + policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + + return 0; +} + static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, ret; @@ -1465,7 +1501,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; @@ -1704,6 +1739,7 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, + .init_boost = amd_pstate_init_boost, .set_boost = amd_pstate_set_boost, .update_limits = amd_pstate_update_limits, .name = "amd-pstate", @@ -1721,6 +1757,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, .update_limits = amd_pstate_update_limits, + .init_boost = amd_pstate_init_boost, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index f80b33fa5d43..133042370a8f 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -102,4 +102,17 @@ struct amd_cpudata { s16 epp_default; }; +/** + * struct amd_pstate_global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct amd_pstate_global_params { + bool cpb_boost; + bool cpb_supported; +}; + +extern struct amd_pstate_global_params amd_pstate_global_params; + #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Wed Jun 19 09:16:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13703562 X-Patchwork-Delegate: mario.limonciello@amd.com Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2066.outbound.protection.outlook.com [40.107.100.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF7D5824A7; Wed, 19 Jun 2024 09:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 19 Jun 2024 04:17:12 -0500 From: Perry Yuan To: , , , CC: , , , , Subject: [PATCH v12 5/9] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Wed, 19 Jun 2024 17:16:38 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB57:EE_|DM6PR12MB4172:EE_ X-MS-Office365-Filtering-Correlation-Id: b372f2a3-f396-4080-a80c-08dc90409ce4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|82310400023|376011|36860700010; X-Microsoft-Antispam-Message-Info: ApKCExkxrZVrsHw7xc3ckSQLAMlcjyUCs2YGOBKZb+9Hv3lVv6Ljjjlu4iM0x4XmQwTxe9BnNxo1hFBrzVR1P3bzFb0fWhOm9ZHnra4aJahlSYPPCykG04Am7fifVL1Klq7fvdEsh1Kbl4Aldz00+51i4G4o1FUk/wyABRulvVqfYWSI9v4rPruA84Q9jsy+hyQ9UamkZ25109CVnOINDhIX5XLuWCsACfAMC54oIQL3WlQ8ujeKYMSldx5qou1qJopny7cq7uSUZdzeObQXV02I9olAE028ZCHbMwLSMDA9waqNo6spg/TVUK59xfbRDbgaBgM7FXpuYaqN8esS3fUPyzgmwEIJxhFZHndEQQrFFfxeXJu/uwEXO+Rx9w/xcBm0HKVHYKhmH/94KhVXPuqXia8Jm4ESTU7OHDKrr765ZOdYRcTMbQR6Tzpb7/0XWYA/h84ngHbA2MBiu4o+mdZPtA3to/zTD7kE1OrhitHcIwCg0nU4JjvUjEulCKKLms/lF3DSIqk10EZTVAxn2mRLJ9iJPsDEJ/bofomfmB/5X0yZA5avTq1jwh5q9+h5O5ovj7F3/gLu4xQPK6X0Fkik+pC7mG8CsDbTITaaB7OzxGQBc9vcJgjgU9Q0gLLK8CtNbQ4U3K/0PUC6MXiwpwxoamO7sKZ8uSl8BxlIOAZi/WwUaFXjnFzbkKVMBGXkt8dF5ZEflL9opo0fg4g0Knx5VRmruZfqHFF8Oc63O1Gg454hGFdFxNp0QoZPkJJyr8dJPi7fChfsE23kVrSSKSJqCdEHnfEcRy0f0U4L7Jwnbupn9TF445MXGKdiKgTRH1aaWO3+lE/D7oVYGcd5B8Wi2/3YXnl+nejQePJ1jcKgqKk3MMooCgS9xHnDdKgi5/qsFMMCjCbt//zV9BDxwQJGFMioVwkvthFNsiARxQfAFcQ1N0R8uammxxVS+ccUQfymcvw+iCHeR0invAH682s8x8o+ghw9+XhXkxWdWQ1ofnH2qkb+y93RlLofhnCVY/N/u5mvnL08TFglyUY6tTvlb0/Z7X+zsA0v9fXP6aRg+7FgG79xfSHRDCrl/xGnKzLp3jJzle2bxYOJWCm2vJBPt3kNb9so0byrv0rD21H7J93Xt9iSZopj8XYzj1zYxEIdBoFIjB+9DUcRxaNxgH5YJ15KLVeVoXAaUiWUwlvE/A50lhiWXsg1LkR/eBaS92OLZEqjyTckWuJRigv55JNU0E2tqN6LTn8NZXSXtON5GDIrQf9Ff0TJazsMJEFqLXdhgRlh5VL+QseoAMlXbWmHByEEai0D4WdTjnwQaBukcf9tFbSrzpHDtj8jF4wcN3hSkdtdX3NC7x+0SreX4VGpqQOktSCvEnQWhJHWWSw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(1800799021)(82310400023)(376011)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:16.3524 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b372f2a3-f396-4080-a80c-08dc90409ce4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4172 From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0): check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1): disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2): enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate-ut.c | 2 +- drivers/cpufreq/amd-pstate.c | 112 +++++++++++++++++++++++++++++++- drivers/cpufreq/amd-pstate.h | 1 + 3 files changed, 113 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index fc275d41d51e..b528f198f4c3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -227,7 +227,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max == cpudata->max_freq) || (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS; diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0c50b8ba16b6..1c2320808ae1 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -104,6 +104,7 @@ static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; struct amd_pstate_global_params amd_pstate_global_params; EXPORT_SYMBOL_GPL(amd_pstate_global_params); +static int amd_pstate_cpu_boost(int cpu, bool state); /* * AMD Energy Preference Performance (EPP) @@ -736,6 +737,7 @@ static int amd_pstate_boost_set(struct amd_cpudata *cpudata) if (amd_pstate_global_params.cpb_supported) { current_pstate_driver->boost_enabled = true; WRITE_ONCE(cpudata->boost_supported, true); + WRITE_ONCE(cpudata->boost_state, true); } amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; @@ -743,6 +745,7 @@ static int amd_pstate_boost_set(struct amd_cpudata *cpudata) exit_err: WRITE_ONCE(cpudata->boost_supported, false); + WRITE_ONCE(cpudata->boost_state, false); current_pstate_driver->boost_enabled = false; amd_pstate_global_params.cpb_boost = false; return ret; @@ -1346,6 +1349,111 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } +static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) +{ + struct amd_cpudata *cpudata = policy->driver_data; + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf, nominal_freq, max_freq; + int ret; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + nominal_freq = READ_ONCE(cpudata->nominal_freq); + max_freq = READ_ONCE(cpudata->max_freq); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + cpufreq_cpu_release(policy); + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = max_freq; + else + policy->cpuinfo.max_freq = nominal_freq * 1000; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq); + if (ret < 0) + pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu); + } + + return ret < 0 ? ret : 0; +} + +static int amd_pstate_cpu_boost(int cpu, bool state) +{ + int ret; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!policy) { + pr_err("policy is NULL\n"); + ret = -ENODATA; + goto err_exit; + } + + ret = amd_pstate_cpu_boost_update(policy, state); + refresh_frequency_limits(policy); + WRITE_ONCE(cpudata->boost_state, state); + policy->boost_enabled = state; + +err_exit: + cpufreq_cpu_put(policy); + return ret < 0 ? ret : 0; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", amd_pstate_global_params.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + if (!amd_pstate_global_params.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret = kstrtobool(buf, &new_state); + if (ret) + return ret; + + mutex_lock(&amd_pstate_driver_lock); + for_each_present_cpu(cpu) { + ret = amd_pstate_cpu_boost(cpu, new_state); + if (ret < 0) { + pr_warn("failed to update cpu boost for CPU%d (%zd)\n", cpu, ret); + goto err_exit; + } + } + amd_pstate_global_params.cpb_boost = !!new_state; + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1356,6 +1464,7 @@ cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1380,6 +1489,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, &dev_attr_prefcore.attr, + &dev_attr_cpb_boost.attr, NULL }; @@ -1418,7 +1528,7 @@ static int amd_pstate_init_boost(struct cpufreq_policy *policy) if (ret) return ret; - policy->boost_enabled = READ_ONCE(cpudata->boost_supported); + policy->boost_enabled = READ_ONCE(cpudata->boost_state); return 0; } diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index 133042370a8f..fb240a870289 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -100,6 +100,7 @@ struct amd_cpudata { u64 cppc_cap1_cached; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:18.6024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0babfb4-8a3a-43bd-84cf-08dc90409e45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5658 Add support for the set_boost callback in the active mode driver to enable boost control via the cpufreq core. This ensures a consistent boost control interface across all pstate modes, including passive mode, guided mode, and active mode. With this addition, all three pstate modes can support the same boost control interface with unique interface and global CPB control. Each CPU also supports individual boost control, allowing global CPB to change all cores' boost states simultaneously. Specific CPUs can update their boost states separately, ensuring all cores' boost states are synchronized. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Acked-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 1c2320808ae1..299e52d4b17e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -699,20 +699,11 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) pr_err("Boost mode is not supported by this processor or SBIOS\n"); return -ENOTSUPP; } + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_cpu_boost(policy->cpu, state); + mutex_unlock(&amd_pstate_driver_lock); - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq * 1000; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) - return ret; - - return 0; + return ret < 0 ? ret : 0; } static int amd_pstate_boost_set(struct amd_cpudata *cpudata) @@ -1868,6 +1859,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .resume = amd_pstate_epp_resume, .update_limits = amd_pstate_update_limits, .init_boost = amd_pstate_init_boost, + .set_boost = amd_pstate_set_boost, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:25.8368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17d75edc-2cc2-46c2-a34d-08dc9040a290 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6280 From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here it needs to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan Acked-by: Huang Rui Reviewed-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 299e52d4b17e..f2ccef089acc 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -524,6 +524,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -543,6 +544,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); + value &= ~AMD_CPPC_MAX_PERF(~0L); value |= AMD_CPPC_MAX_PERF(max_perf); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:27.2743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8217a16d-2603-4351-2311-08dc9040a373 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6244 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..bcc0d9404c18 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,16 @@ control its functionality at the system level. They are located in the This attribute is read-only to check the state of preferred core set by the kernel parameter. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this attribute file which allows + user to change all cores frequency boosting state. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2024 09:17:28.9618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 016c75a0-014f-411c-b5de-08dc9040a468 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB57.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9388 Updates the documentation in `amd-pstate.rst` to include information about the per CPU boost control feature. Users can now enable or disable the Core Performance Boost (CPB) feature on individual CPUs using the `boost` sysfs attribute. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- Documentation/admin-guide/pm/amd-pstate.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index bcc0d9404c18..98e43c53c387 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -281,6 +281,26 @@ integer values defined between 0 to 255 when EPP feature is enabled by platform firmware, if EPP feature is disabled, driver will ignore the written value This attribute is read-write. +``boost`` +The `boost` sysfs attribute provides control over the CPU core +performance boost, allowing users to manage the maximum frequency limitation +of the CPU. This attribute can be used to enable or disable the boost feature +on individual CPUs. + +When the boost feature is enabled, the CPU can dynamically increase its frequency +beyond the base frequency, providing enhanced performance for demanding workloads. +On the other hand, disabling the boost feature restricts the CPU to operate at the +base frequency, which may be desirable in certain scenarios to prioritize power +efficiency or manage temperature. + +To manipulate the `boost` attribute, users can write a value of `0` to disable the +boost or `1` to enable it, for the respective CPU using the sysfs path +`/sys/devices/system/cpu/cpuX/cpufreq/boost`, where `X` represents the CPU number. + +It is important to note that modifying the global variable +`amd_pstate_global_params.cpb_boost` will override the individual CPU settings. + + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.