From patchwork Wed Jun 19 10:11:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13703620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C90BCC27C53 for ; Wed, 19 Jun 2024 10:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=T3xON2h2xbVG30yQyF33zsls/t9gOK/543Opt+teOpk=; b=TQzMTYPaTvbgZjaQUDjbj+n9YG BB4S1Y6JfUQijCfHTTWcZA8CZ8pilzcltslqePFrlKZFUceyQtmGa0AItAs9QadwrA/wmQ6wCTeM6 x6LreQbaZmpRXntgwxthmMji7u67YyVX93WRoZHaNtAXjYx9ML9Rhu8I04TY6VymBWTgUhMOKELNB htOCdPmCR+w70HpcutBRmuA2u0vgSGqeLR/jLT1HvBgarn13ZK3bApAnXGPThJJ87HE4T2FhfN1rd bu4D0KoIhJskM9i5rLk0Atae2nTbvxKTUXHqJseyXftfrw/0kbqzX1dUO5iG5OCywTIxrEmHzbMy4 H2ykFduw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIn-00000000jVs-0N48; Wed, 19 Jun 2024 10:12:29 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIU-00000000jRs-3TER for linux-arm-kernel@lists.infradead.org; Wed, 19 Jun 2024 10:12:12 +0000 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-362b32fbb3bso899534f8f.2 for ; Wed, 19 Jun 2024 03:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718791929; x=1719396729; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T3xON2h2xbVG30yQyF33zsls/t9gOK/543Opt+teOpk=; b=KGje212gKoFv0FzTb8GIKKJ4nLviMoJAk2ya5XJaiKfJA3WKluu8BPQzpcBXghWFUK RpU6wbgM2x2ENCl6jmcNebEFw9bhHUsUX3RjNL+pj4WyBonoLgmrr2tVkMVWdX/t6j+M NVAYVk0fDUExNXeGZPkb6uQGJpmpXH9k/tUETX9zlqyjt+hvI3QctTLwHst4edgHRIsh GTtz3tLh1gORywLwGXAnWdkzp3v2XPGuureePUCQwTEjXwKDNhEM3JEOHlLjszCTr72K Wn5C3KKiwUK7ailnr2LU0xHwJ+zkFENdPwNUoUb6CgXnuoyP4u+8qyz3J7jdud5F9lFq 6XKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718791929; x=1719396729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T3xON2h2xbVG30yQyF33zsls/t9gOK/543Opt+teOpk=; b=vYw0UVCH2KB4L8/yyUBRiO2iDAX81YHIqoE0lzBzdel8bL9zfuA1ZK0HGIC6EBUmOL n73SOyqdQIVVuJTWaAm9/qtAQmnLA4Ww7LUpUV9sy3brRIdGZeUhSSMf04es2twFav6a uczafbmxVNTuiWWAapOkQbve1zKTpsLkehIakbJEsJzd49764EtZzSu6H4M6AomrTV+O p7XsSLtkji1MbwTs6yikjP9jO0eNK3MfyUlDIPDXyDFOwwobRgfMpRwQV9woP7i2dU7D +mho2p7wa8zUcwDveRHlLNDTo1TRAjfb5AGRTcbofmbt0V1efeEVJKvTJUMGk3RsLxno 35TA== X-Forwarded-Encrypted: i=1; AJvYcCWdlYr0mmrOZ7SpOiJF4Nv5H7Qb+ESInOc6cIYut2XfKT15XVnkEDLTapNolZkUkfQg94Z8YRwAilywjppTV3RX4J0zo5Bs0+YNIngsnd/nfodXsgE= X-Gm-Message-State: AOJu0Yz8NZacMTYO6u+pH33Fdoqz8LVyqUIBcMcdEbj+BRb1J9y63wm6 FU0+2WTcLPGg+5a8xwyarp8/fAPLkhujCh0Q8g768ugrJIwKAap4//SGQHf3to0= X-Google-Smtp-Source: AGHT+IG2kKR9AJ4Xve9v1M/xcezVMVRX51DSqCLtivR58CHrVK/OVUmA/K+zAtsEnUAD/1LOt9gYfg== X-Received: by 2002:a5d:550e:0:b0:35f:2c43:8861 with SMTP id ffacd0b85a97d-3631998f664mr1605544f8f.66.1718791929293; Wed, 19 Jun 2024 03:12:09 -0700 (PDT) Received: from localhost (p509153eb.dip0.t-ipconnect.de. [80.145.83.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-360750ad20bsm16622708f8f.54.2024.06.19.03.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 03:12:08 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , William Breathitt Gray , Lee Jones , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thorsten Scherer Subject: [PATCH v2 1/5] mfd: stm32-timers: Unify alignment of register definition Date: Wed, 19 Jun 2024 12:11:42 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11404; i=u.kleine-koenig@baylibre.com; h=from:subject:message-id; bh=URUfwaiOSrPZlfy433XXHQY/TFA8jECx1YrYlu6D9CI=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmcq7hDOp2oycl/aTg79uVReGpzfgzpVnaEjxop EKtatm46oaJATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZnKu4QAKCRCPgPtYfRL+ TtvpB/9WWbNmM+4Fh90FJ67FdiyBqJQvSzqX4/KEuhMnUeeGitAyIJDFoJLnxYk6Ne8Km2sifO0 /LddP279V3TSYUzsGFF6VYv8fFLG7RLv8VYX8Wt3VGbS+mUV26el6qeH7uAKx3qnBavujOSLKKP WmaBKGbsc8kp5NbeD5dFfvqK2uxjofFXvLbNanS9ZmP2z8xgVyqoNxkg5+AAjIuuOsN9pOAHNSM ph3Sbl9KyyWm2+dRW1Rxwr0c0uS6pIfW7k0Gy24z+5/9HIPuQG4+OJnC6Gwz+T7j9yGMh2Qfkk3 bLjt3ZqrB+Pg98Mj0eDMVHoI7JivcKzE9c2HKHfbhmPzN/cD X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_031210_893990_42BA4459 X-CRM114-Status: GOOD ( 12.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use tabs consistently for indention and properly align register names, values and comments. This improves readability (at least for my eyes). Signed-off-by: Uwe Kleine-König --- include/linux/mfd/stm32-timers.h | 170 +++++++++++++++---------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 9eb17481b07f..5794110b2b28 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -12,97 +12,97 @@ #include #include -#define TIM_CR1 0x00 /* Control Register 1 */ -#define TIM_CR2 0x04 /* Control Register 2 */ -#define TIM_SMCR 0x08 /* Slave mode control reg */ -#define TIM_DIER 0x0C /* DMA/interrupt register */ -#define TIM_SR 0x10 /* Status register */ -#define TIM_EGR 0x14 /* Event Generation Reg */ -#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ -#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ -#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ -#define TIM_CNT 0x24 /* Counter */ -#define TIM_PSC 0x28 /* Prescaler */ -#define TIM_ARR 0x2c /* Auto-Reload Register */ -#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ -#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ -#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ -#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ -#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ -#define TIM_DCR 0x48 /* DMA control register */ -#define TIM_DMAR 0x4C /* DMA register for transfer */ -#define TIM_TISEL 0x68 /* Input Selection */ +#define TIM_CR1 0x00 /* Control Register 1 */ +#define TIM_CR2 0x04 /* Control Register 2 */ +#define TIM_SMCR 0x08 /* Slave mode control reg */ +#define TIM_DIER 0x0C /* DMA/interrupt register */ +#define TIM_SR 0x10 /* Status register */ +#define TIM_EGR 0x14 /* Event Generation Reg */ +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_CNT 0x24 /* Counter */ +#define TIM_PSC 0x28 /* Prescaler */ +#define TIM_ARR 0x2c /* Auto-Reload Register */ +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ +#define TIM_DCR 0x48 /* DMA control register */ +#define TIM_DMAR 0x4C /* DMA register for transfer */ +#define TIM_TISEL 0x68 /* Input Selection */ -#define TIM_CR1_CEN BIT(0) /* Counter Enable */ -#define TIM_CR1_DIR BIT(4) /* Counter Direction */ -#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ -#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ -#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ -#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ -#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ -#define TIM_DIER_UIE BIT(0) /* Update interrupt */ -#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ -#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ -#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ -#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ -#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ -#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ -#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ -#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ -#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ -#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ -#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ -#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ -#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ -#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ -#define TIM_EGR_UG BIT(0) /* Update Generation */ -#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ -#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ -#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ -#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ -#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ -#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ -#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ -#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ -#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ -#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ -#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ -#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ -#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ -#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ -#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ -#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ -#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ -#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ -#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ -#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ -#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ -#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ -#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ -#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ -#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ -#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ -#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ -#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) -#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ -#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ -#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ -#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ -#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4)) -#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */ -#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ +#define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_DIR BIT(4) /* Counter Direction */ +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ +#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ +#define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ +#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ +#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ +#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ +#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ +#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ +#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ +#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ +#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ +#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ +#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ +#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */ +#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */ +#define TIM_EGR_UG BIT(0) /* Update Generation */ +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ +#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ +#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ +#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ +#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ +#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ +#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */ +#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ +#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ +#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ +#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ +#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ +#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ +#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ +#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ +#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ +#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ +#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ +#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) +#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ +#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ +#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4)) +#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */ +#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ -#define MAX_TIM_PSC 0xFFFF -#define MAX_TIM_ICPSC 0x3 -#define TIM_CR2_MMS_SHIFT 4 -#define TIM_CR2_MMS2_SHIFT 20 +#define MAX_TIM_PSC 0xFFFF +#define MAX_TIM_ICPSC 0x3 +#define TIM_CR2_MMS_SHIFT 4 +#define TIM_CR2_MMS2_SHIFT 20 #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ #define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ #define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ #define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ -#define TIM_SMCR_TS_SHIFT 4 -#define TIM_BDTR_BKF_MASK 0xF -#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) +#define TIM_SMCR_TS_SHIFT 4 +#define TIM_BDTR_BKF_MASK 0xF +#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) enum stm32_timers_dmas { STM32_TIMERS_DMA_CH1, From patchwork Wed Jun 19 10:11:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13703623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B7B5C2BA15 for ; Wed, 19 Jun 2024 10:12:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fWXZAlLTUOX+tTobWucYGS5J3I+aXFzRea0PJgB3aYU=; b=s6Ae3B49k7TEMi1s1WTZGJyeDc xPMEo+17f6WE0wKg3/lDU2pCwVzV9KqrkegYtza8xcrTnSB2j1/97F/MGwDYs8alXzfBQ/Dz4O2q1 AyJwrifZFKjD4DsPGd1BFIP8+6FgsGX62mjE8oyvJYt0AnN9njvmmPUk1Rwn2Qp2ioiIvIAIJ1Qdm PiDEigvLPnQG250ee+QFEvxo0QmApt8eFKcEkgoAP9icIVRxN69Xx9CcXq6wiFegwJPamWPMRRYOp GBCtPzjErEngdQO9gIom7yD9uvHpIr20ZT+jaHPyiiKIaGVpzi+5mENhaHEAPS0G6dOj0CdRMPW5v pEfTc+0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsJ2-00000000jcn-1JCX; Wed, 19 Jun 2024 10:12:44 +0000 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIW-00000000jSD-02Qn for linux-arm-kernel@lists.infradead.org; Wed, 19 Jun 2024 10:12:13 +0000 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-421cd1e5f93so46147645e9.0 for ; Wed, 19 Jun 2024 03:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718791930; x=1719396730; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fWXZAlLTUOX+tTobWucYGS5J3I+aXFzRea0PJgB3aYU=; b=oKOerVzVmxDrTc6hv+SeEOXAzFltKgCN5WJgtapHHrPhtLqu83TQX8CXO7K3tkOzLV SbLvQbtDEGWxlVp4wk5ESDBjCXilK1j4HjaZgIT9xUtOMEHBctM0XnRIvcL3cOaWSLBk UkqGOFcCecLR7Q3B3vTfJpBQfzphJWxbukBREP/BwTLuGlVIgvmTK2LgKf09wUGlwJES 7scKvotZf8yTSQlUN6PYtt7TyiG5ObfHOZSvFehHDljfp6GHd3JIWWINxmdIZH8GIMyK UHKkEMV28riDw52kFrCGRhVX6Ae1tqkJvCSNkTzKZD+yTkD6zKXn8vuXqyIsh4qP6HSv oqKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718791930; x=1719396730; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fWXZAlLTUOX+tTobWucYGS5J3I+aXFzRea0PJgB3aYU=; b=YqB6rKJAP3emBKZv20epMM41ymIKl48YJEMWMGinkyAkb4gSFklHeKh6AUvlWwV9s6 k1X6robDHTqp+c3FnYgwXstcgnuLApCDnsAWBO/m78KYk5yrbzOyYlxf9INEMKmqN7+M jtWMMop6ywUOlXesfGgfyO0iuEMvvYLe49PaFUV7E2HHk3LbT9YwS+HX5NQoPaPdbpNR UpYG5Uqhi8Ybm2aXJEM4MOjIelwHWpqrRtJNjiAm77YN8WPXAE9TJ0OrO95WmCGZz28a 2j7daJ/6lghEJtO2a1VqfoQ4lfUlkVqDswKUg2WgSmRIuGe8NW2zHUckISdoxrRwwn3u cuow== X-Forwarded-Encrypted: i=1; AJvYcCW9vmiOAyUY8YAALQXQn+nrYgyU8Dw1DdByqFNzpZOl05/sqmZfB/IMNb8YwA+drgoP0oszYH47Ag9pFEkoHrnH+SDOufpkd1lBk9HbKXIPgZeisFU= X-Gm-Message-State: AOJu0YyVxQVrq6iNEExvHmMyhXqBkZqW4qpNhfpoj7lNoHXIvASogR9Z cmHHfemxNAGswl7Uy5f1jD5WtMSA+VQfkj2XdD+AQ6Baodaafygguu9IKdRO41o= X-Google-Smtp-Source: AGHT+IHIxrQqbYiuGPGtgLfNvQ8yNK+7Isq3Mu1k2EywX94rSO7C16VmJUJD0LF/8DIYPtV/McCtnQ== X-Received: by 2002:a05:600c:4652:b0:422:615f:649e with SMTP id 5b1f17b1804b1-42475298ba0mr15577755e9.27.1718791930619; Wed, 19 Jun 2024 03:12:10 -0700 (PDT) Received: from localhost (p509153eb.dip0.t-ipconnect.de. [80.145.83.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3615d7a1a0csm4234227f8f.23.2024.06.19.03.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 03:12:10 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , William Breathitt Gray , Lee Jones , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thorsten Scherer Subject: [PATCH v2 2/5] mfd: stm32-timers: Add some register definitions with a parameter Date: Wed, 19 Jun 2024 12:11:43 +0200 Message-ID: <05df15f61dde81033407d3b4fcb67ee403ecc8db.1718791090.git.u.kleine-koenig@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6869; i=u.kleine-koenig@baylibre.com; h=from:subject:message-id; bh=stG4EosrRZoLl+rGkaCdgcYZ2i4JpRbIXzGPd14Nook=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmcq7k0muWLeHuQ6CBwgj3N6qOjE3WGeJGtti5m ryq8Pb9UQKJATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZnKu5AAKCRCPgPtYfRL+ TumdB/45ANiIOKmrxtVh0tAsSOvCQJW7uCAA6Y6U4alc+bMWmJzMzms7t1yeL8+ytmfgYESjlKY xeZs7/c/s8Qh75yAh63Qk/kRytlJj6ChbwmFSQqKIZHVzOKkdyMxDCjWgobMO6C0k8uKBGYbnfP yWCc1L/wLfg7UKYkwzbq8xQUXxnz/Me59MYkgc52zwQHs3jbLIgMU9QTBiIzqlMWytuc+udR5Su bDdMiKZS1Q+MVX2MqR5Ros+Oidq/DKoCGgqGX4Qv2xZxMtk0I/XRsDHrM9ZOeTCk76VvlTbkGYG eNlg+EWaBcbWpmtfERFdUlOmQUUNvXNzLo/wAOH4OFKXES74 X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_031212_083433_7A804B61 X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There are some registers that belong together and are numbered from 1 to 4. Introduce a macro definition for these that takes the channel number as parameter and define the previously available constants using the new ones. This allows to simplify some users that up to now use constructs like TIM_CCER_CC1NE << (ch * 4) which is an ugly mix of using a predefined value and still knowing internal details about it. Note that there are several decrements by 1 involved. These are necessary because software guys start counting at 0 while the hardware designer started at 1 (and having TIM_CCER_CCxE(1) be TIM_CCER_CC2E isn't a sane option). The compiler is expected to optimize these out nicely. Signed-off-by: Uwe Kleine-König --- include/linux/mfd/stm32-timers.h | 60 +++++++++++++++++++------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 5794110b2b28..92b45a559656 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -24,10 +24,11 @@ #define TIM_CNT 0x24 /* Counter */ #define TIM_PSC 0x28 /* Prescaler */ #define TIM_ARR 0x2c /* Auto-Reload Register */ -#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ -#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ -#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ -#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ +#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ +#define TIM_CCR1 TIM_CCRx(1) /* Capt/Comp Register 1 */ +#define TIM_CCR2 TIM_CCRx(2) /* Capt/Comp Register 2 */ +#define TIM_CCR3 TIM_CCRx(3) /* Capt/Comp Register 3 */ +#define TIM_CCR4 TIM_CCRx(4) /* Capt/Comp Register 4 */ #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ #define TIM_DCR 0x48 /* DMA control register */ #define TIM_DMAR 0x4C /* DMA register for transfer */ @@ -41,16 +42,18 @@ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ -#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */ -#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */ -#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */ -#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */ +#define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */ +#define TIM_DIER_CC1IE TIM_DIER_CCxIE(1) /* CC1 Interrupt Enable */ +#define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */ +#define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */ +#define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */ #define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ -#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ -#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ -#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ -#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ +#define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */ +#define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */ +#define TIM_DIER_CC2DE TIM_DIER_CCxDE(2) /* CC2 DMA request Enable */ +#define TIM_DIER_CC3DE TIM_DIER_CCxDE(3) /* CC3 DMA request Enable */ +#define TIM_DIER_CC4DE TIM_DIER_CCxDE(4) /* CC4 DMA request Enable */ #define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ #define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ @@ -70,19 +73,26 @@ #define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */ #define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */ #define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */ -#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ -#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ -#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ -#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ -#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ -#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ -#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */ -#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ -#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ -#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */ -#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ -#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ -#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */ +#define TIM_CCER_CCxE(x) BIT(0 + 4 * ((x) - 1)) /* Capt/Comp x out Ena (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxP(x) BIT(1 + 4 * ((x) - 1)) /* Capt/Comp x Polarity (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxNE(x) BIT(2 + 4 * ((x) - 1)) /* Capt/Comp xN out Ena (x ∈ {1, .. 4}) */ +#define TIM_CCER_CCxNP(x) BIT(3 + 4 * ((x) - 1)) /* Capt/Comp xN Polarity (x ∈ {1, .. 4}) */ +#define TIM_CCER_CC1E TIM_CCER_CCxE(1) /* Capt/Comp 1 out Ena */ +#define TIM_CCER_CC1P TIM_CCER_CCxP(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE TIM_CCER_CCxNE(1) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP TIM_CCER_CCxNP(1) /* Capt/Comp 1N Polarity */ +#define TIM_CCER_CC2E TIM_CCER_CCxE(2) /* Capt/Comp 2 out Ena */ +#define TIM_CCER_CC2P TIM_CCER_CCxP(2) /* Capt/Comp 2 Polarity */ +#define TIM_CCER_CC2NE TIM_CCER_CCxNE(2) /* Capt/Comp 2N out Ena */ +#define TIM_CCER_CC2NP TIM_CCER_CCxNP(2) /* Capt/Comp 2N Polarity */ +#define TIM_CCER_CC3E TIM_CCER_CCxE(3) /* Capt/Comp 3 out Ena */ +#define TIM_CCER_CC3P TIM_CCER_CCxP(3) /* Capt/Comp 3 Polarity */ +#define TIM_CCER_CC3NE TIM_CCER_CCxNE(3) /* Capt/Comp 3N out Ena */ +#define TIM_CCER_CC3NP TIM_CCER_CCxNP(3) /* Capt/Comp 3N Polarity */ +#define TIM_CCER_CC4E TIM_CCER_CCxE(4) /* Capt/Comp 4 out Ena */ +#define TIM_CCER_CC4P TIM_CCER_CCxP(4) /* Capt/Comp 4 Polarity */ +#define TIM_CCER_CC4NE TIM_CCER_CCxNE(4) /* Capt/Comp 4N out Ena */ +#define TIM_CCER_CC4NP TIM_CCER_CCxNP(4) /* Capt/Comp 4N Polarity */ #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */ #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */ From patchwork Wed Jun 19 10:11:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13703625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64A8BC27C53 for ; Wed, 19 Jun 2024 10:12:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eHeUArdSKpP0gigzpdr9jDKMc/RdHGYl+hgWmyzctFg=; b=A/4Fnk9L3vw1xDfjgml5o4nonB Q99s59wr7bKT3WlHFOPxwfENLnS2ta0lwyGAhOYGhdYB3/j7x0J99qhqzU+WlvzCUEmru1C+jwoX6 0LuP6XX8ojXhHTP1vfwp36sYFqEnrYa6wacNFOa/qqYkZ+TCdfvEjqa/2tTeoDi61plJfK311RD2c QLKF8Mf6m+y5UqvVWv+NyHMcQFaM9L8S+2NTZkrRrJAewxXuyZd0MwnwIpUArEGDZDXsB34RhYkkm Cmq3LQfRmPXMfmXTL/Kzx8o7QW5qT/7b2Om3ZF2Cfp8aC5nZUFVgHHFhLMeSEG8QaCkvGIvsnaNQz m3Z+VoeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsJ5-00000000jeG-0kmM; Wed, 19 Jun 2024 10:12:47 +0000 Received: from mail-lj1-x22e.google.com ([2a00:1450:4864:20::22e]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIX-00000000jSg-3B0J for linux-arm-kernel@lists.infradead.org; Wed, 19 Jun 2024 10:12:29 +0000 Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2ebe6495aedso60727821fa.0 for ; Wed, 19 Jun 2024 03:12:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718791932; x=1719396732; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eHeUArdSKpP0gigzpdr9jDKMc/RdHGYl+hgWmyzctFg=; b=dc0fdIFlnNlxCSJoV8MoK/904zS5Z1W05AUNmUm+Kc8IlGxfUcR+Ot+JWbfnH7A+cx x/MPasjy+fZXEfw5xhZeZ+Kg7/Zq9kwBs/gJ4hVXk5psPZHrgXng0gWKUO4WUfDeAijM CaJzb6EDURvSqwFu2gaGt2nuaeGG0D40mFeMZlOBPwGSP59LvG3pYjlSIXqC8J8OkxGd EA86KZS6GOluhChsFlvfKN/7cC7ROM3yZpXzLZmFL+SOHo6DsyiRz19m/BTJFrw8UDw7 j/M6NYFugPctTNInICAnI0YMV4nKhrRF5hPozurBH3Y2d4TorsC/N3TRQ6dYFnZ1jP9x wmvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718791932; x=1719396732; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eHeUArdSKpP0gigzpdr9jDKMc/RdHGYl+hgWmyzctFg=; b=u3GpiNR6MGKfz4Yw+JZfY7k4jRsTpz4agPPBoxcTlRUS1Ht4f+yH1BxFCqYyJODUA9 w3KBstgKxqkQAPmLP0ACIcu8w47KLi8YPKltCz6cCkuTRl1OnxEYxrrbMNG0zWNDy5sc FtREl7nx44/IMFBJt8d8WWA8NqiyICYlNiwakPAIxbE4qjXRogJKKrG9Ifs5JTPymFu1 pMYxoWRBF8XQCezh7kVBh7jX+BSX9pLCq3oj2LXewBF3LJww7wj1C6J2uAhcF5T1AIdC tBtR4++pxPW+xhF4T5KJpYdOXD/zYdA6rSkA1aXYYJ2n9odS8RY4R5RH+lC5UmVJBpNp iKWA== X-Forwarded-Encrypted: i=1; AJvYcCWhd74M2nGhURyvsoOgJB3ywSosIVwVUPghGBZ2Y8CTFoNQDumn2C8qZOOuLcqSnfrn7SPjnwJvb6nTvbauR08OYsDrtlxl+4rmtctQSxnvRe/UeXQ= X-Gm-Message-State: AOJu0Yz04Wi2is0HbFT9iAhBlsI87wn79sEnA481GP7pvt/0VWO1xI1A Cn3GMwMzGsoVvXL0yYM6IE+VbkofY4siSASaHmt8QNWBOk61pY+/8syhRB1McMo= X-Google-Smtp-Source: AGHT+IGyBLZDsIe+RLHY2gT0ffX4UdQ+4/orS3dRcY6M6qSnO9AgKtn+LaqX7vFTMoagllxCj9bhpg== X-Received: by 2002:a19:c205:0:b0:52c:aa0f:622d with SMTP id 2adb3069b0e04-52ccaa37500mr1184800e87.30.1718791931979; Wed, 19 Jun 2024 03:12:11 -0700 (PDT) Received: from localhost (p509153eb.dip0.t-ipconnect.de. [80.145.83.235]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-422f602e802sm224164165e9.11.2024.06.19.03.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 03:12:11 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , William Breathitt Gray , Lee Jones , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thorsten Scherer Subject: [PATCH v2 3/5] counter: stm32-timer-cnt: Use TIM_DIER_CCxIE(x) instead of TIM_DIER_CCxIE(x) Date: Wed, 19 Jun 2024 12:11:44 +0200 Message-ID: <126bd153a03f39e42645573eecf44ffab5354fc7.1718791090.git.u.kleine-koenig@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1691; i=u.kleine-koenig@baylibre.com; h=from:subject:message-id; bh=ls4kxFHqkBG+kx3WnRXHImWHnlbY3kjK18Z2TnMQLqo=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmcq7mxkltqOid2paUGt3syPB6S0GwVABYwtite mZw5LibI4+JATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZnKu5gAKCRCPgPtYfRL+ ThvbCACIw0IFO0iRtD++sN85YjotjckPff1mDVwNLBVaYqLdD/VtfYCUK2skkHC67BNifelJo3I G2/mOes1u137ttN4EbhqeW5MG9RqBa19yYwx31nH8RvOUywSbqyhYfdgeuDqtr/A1NDvL6eOnjU U9uwZf7FjLh4mnnTehhIJJoGBFAKprGxIbVI7QjjBJiP0/WEB0U/GF85mbSjXauaQBq5Iw2yynC DEczOF7dcKrtl1IzqBaF08lPGfHzGpX0WUbX064/snRbhcVXQ5ruP93BFjUM+67ecHXsEymcTHy dTqkyaIFtvIUw3HjwSHexHs0tMC4xNcCb6dgUX0okdcKZ6W3 X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_031227_807154_899791EB X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org These two defines have the same purpose and this change doesn't introduce any differences in drivers/counter/stm32-timer-cnt.o. The only difference between the two is that TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE while TIM_DIER_CCxIE(1) == TIM_DIER_CC1IE . That makes it necessary to have an explicit "+ 1" in the user code, but IMHO this is a good thing as this is the code locatation that "knows" that for software channel 1 you have to use TIM_DIER_CC2IE (because software guys start counting at 0, while the relevant hardware designer started at 1). Signed-off-by: Uwe Kleine-König Acked-by: William Breathitt Gray --- drivers/counter/stm32-timer-cnt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 0664ef969f79..186e73d6ccb4 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -465,7 +465,7 @@ static int stm32_count_events_configure(struct counter_device *counter) ret = stm32_count_capture_configure(counter, event_node->channel, true); if (ret) return ret; - dier |= TIM_DIER_CC_IE(event_node->channel); + dier |= TIM_DIER_CCxIE(event_node->channel + 1); break; default: /* should never reach this path */ @@ -478,7 +478,7 @@ static int stm32_count_events_configure(struct counter_device *counter) /* check for disabled capture events */ for (i = 0 ; i < priv->nchannels; i++) { - if (!(dier & TIM_DIER_CC_IE(i))) { + if (!(dier & TIM_DIER_CCxIE(i + 1))) { ret = stm32_count_capture_configure(counter, i, false); if (ret) return ret; From patchwork Wed Jun 19 10:11:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13703624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88CDBC2BA1A for ; Wed, 19 Jun 2024 10:12:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Qi4aJYEUuIQ/V13fBIYhBcSSVZbkz2WHC3xkADAjAwY=; b=ADiUAfceghgMmzTp5ACFJwb3Mh Lj+E07WhreC9pjsFzHErVxz2WZDZalFQ2Z3nA1sLzxaLGJ5wFBUN6SFmWrVMpEDnHITMDq3XeM3E/ LCIl8QQ4VrPfwToG5MsZbG1jym+Hfvn8I6fgpoJ9oi3VoN56JundSxa8D2xTTiNBLgO8U165RSY6n KV1IvmgWTtuA6tRbJrpBTwl3mah5oS0bSN/4rEU9vfZIIvVtIv1xweGYPLfHUCvDdpRQZM/iiTxHE 8h3Z4Ffy9PwcXQnc+5hiW231AJhzsTICBq6RSPOcbLmmgWeUsSEn1Ii9Admx6fGMvp15Q0ewveKkJ VVbhsmbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsJ6-00000000jfR-0wpm; Wed, 19 Jun 2024 10:12:48 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIZ-00000000jSo-0CVm for linux-arm-kernel@lists.infradead.org; Wed, 19 Jun 2024 10:12:30 +0000 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a63359aaacaso1012410366b.1 for ; Wed, 19 Jun 2024 03:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718791933; x=1719396733; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qi4aJYEUuIQ/V13fBIYhBcSSVZbkz2WHC3xkADAjAwY=; b=Y8Ge6iU0OHMZJhyb77ejtrweRQExItmMu39TYYmjrQm+7ifveDdMJ+fGy3+d/jqK8V de5aDpEzzvj0phn4cVZah07ORW1+IWrh5+B1dT4iOyt9j1UJAjPJJE5gMP5xqfp39pP4 PH/e0ybFstUEfef3ebywfOa6ztZ675PtXah86RQrxicdxq4qdGeB0A4Xy7hOblWkrno8 UeeA35EAj3DhciQxzy11HgbhoV0VvnFC8T0+QN3u5OuqCSh3GNxI+VDFUD9Sjd+LXH1l ZGqbMTW44V7P2QG4DfK+Eq8LStLOYwOexpQv7ZKDc88o0h8cuTT0pkxunzK24x+LNk2e YVHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718791933; x=1719396733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qi4aJYEUuIQ/V13fBIYhBcSSVZbkz2WHC3xkADAjAwY=; b=T7MhJiFDjGWWWHfIT7YUglZQGVvZ8uiXofHuLxzbM8y2ZN1R0PusTquo+4sIWw3Qjd hwYDV6lZ++99zgtoCBXx70JUno0z57bjo6LHJfBt9IBmtibpyA3S3AXjzslY+4aAkyZl UNP55aLSmu6iAXqvYLm0qQr/RSblmtvn4G0CkLtHRYo8I4SUPI16Ivld8KZHmCzu6FGK pivlXR2DtkgAzPZWoxhOgetK2FvFluwTTPqobaSUVmkhdZ2ITG1kCfC4tz/XDjNtbnUL SEPZfSboZ+qKn9q90kaaznWVKWo27LjLD+GHP5GV3Uni+8uGT7QKzOMR3zCE0DkPEKh4 BnmA== X-Forwarded-Encrypted: i=1; AJvYcCXcf1ZjHaiOspskvx0SvKMYNtteKDtfFqYRD4zgH18892ufJHinRRUWy1koG9Ff6UPrI0xMMTfGdjjxn+V4JYZqWtKg+2s+nqBIl8xT4XxIJQ3Ul3s= X-Gm-Message-State: AOJu0YzcmfyDo6UFGShl2LqUZ6M0nqNEN+ANZba3u9dni19J7KgzqmaE 5oXMp3etkoEBKSD1d2iCBB7HxahG7zd9Ni6dDdBuz+inmixgRiibFJDgSoHhOzo= X-Google-Smtp-Source: AGHT+IEvkBeb1adtQps5uR2c9XR/Xi41EP+Gxj4qPXO+OoA/UyIlWg8yqWZ8kfEL9FPggix9HVnzKw== X-Received: by 2002:a17:907:1682:b0:a6f:98b6:36e with SMTP id a640c23a62f3a-a6fab605048mr169655966b.11.1718791933291; Wed, 19 Jun 2024 03:12:13 -0700 (PDT) Received: from localhost (p509153eb.dip0.t-ipconnect.de. [80.145.83.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-363a23143dfsm1168204f8f.87.2024.06.19.03.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 03:12:13 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , William Breathitt Gray , Lee Jones , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thorsten Scherer Subject: [PATCH v2 4/5] mfd: stm32-timers: Drop unused TIM_DIER_CC_IE Date: Wed, 19 Jun 2024 12:11:45 +0200 Message-ID: <6c8fcc4ed159992a1dbb0796087e6ceb10c39c96.1718791090.git.u.kleine-koenig@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1147; i=u.kleine-koenig@baylibre.com; h=from:subject:message-id; bh=zia9ohJCDf6pPTMCj3l2MlOJgs40Pm2zXv4CKnsKZ4Y=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmcq7oy8mveEdP8uq3o2jBR0yAiv7fDFKSJltQ4 YkOueb1NN2JATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZnKu6AAKCRCPgPtYfRL+ TrX5B/0USVLFzo4MlcaT5z91XGN6knZpVjFtzoHUM0al+H/HJnjOPt2QItflEUYgFAJQzvuiGBb AZhX+KiO1s5etz6fLwixuy9K3rJ1JXcuBQ5FRDBf3PsZHXNKY3Htb4q3VYI34xmH8S8gLwCMk27 DoObyZ4OWbW++D14JjTSStR8wGDREHItW8erobR0HABTTDcP9K8n+HqNXDPyvgReo1fB+VlDwr/ IBtUTkomTjRAmLKMk0kQz6IzO6UmIpQC3VRx/R4fVBWGsq+gypGxPqP8kyoDhONcuf/bPJTt6C7 0rKidDi+2qnuyqmHz9QOjbqCFPs74jFe1MNyOrRuKdTNk/s8 X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_031227_856149_30B278EA X-CRM114-Status: GOOD ( 11.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This macro is misleading as TIM_DIER_CC_IE(1) == TIM_DIER_CC2IE . The only user was updated to use TIM_DIER_CCxIE() instead which doesn't suffer from this mismatch, so TIM_DIER_CC_IE can be dropped. Signed-off-by: Uwe Kleine-König --- include/linux/mfd/stm32-timers.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 92b45a559656..f09ba598c97a 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -47,7 +47,6 @@ #define TIM_DIER_CC2IE TIM_DIER_CCxIE(2) /* CC2 Interrupt Enable */ #define TIM_DIER_CC3IE TIM_DIER_CCxIE(3) /* CC3 Interrupt Enable */ #define TIM_DIER_CC4IE TIM_DIER_CCxIE(4) /* CC4 Interrupt Enable */ -#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */ #define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ #define TIM_DIER_CCxDE(x) BIT(9 + ((x) - 1)) /* CCx DMA request Enable (x ∈ {1, .. 4}) */ #define TIM_DIER_CC1DE TIM_DIER_CCxDE(1) /* CC1 DMA request Enable */ From patchwork Wed Jun 19 10:11:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= X-Patchwork-Id: 13703622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 089ABC41513 for ; Wed, 19 Jun 2024 10:12:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Oy65aQubSD4tbmjRxefZecoIq4GXZIdFH64RPRpuevk=; b=zO+n+FG2sIwyiX5Rh9DBArIMn5 9/gnWNSXfyYW6dMdjHiwdoKCulO2UFpGnMYqX/dgAke+cVTRxPg2kiYgOhCKBjjek6NYgKapfDwKT IHMbmS/fX36bq7aP/Av1D4N8XjPQZmNiyHSsIb1WjVnv5GMxlFFMCdHCCViTe4T1J9RzJYkF91aVa 5/eD5m2MMw0ZJ/dyxl6N78nXSrW6l37F22RrJj2QRbYUYuKI7SG/iK3N3mHfviB3H2XrKBW1AjWQ+ t/4BS5vJ7KkR8ewX/SdFocEivwkur7l+y80zarmBClM/6wWl1S8jipN+mPhS6XHv1XeX7AjjITHdC T0zrKrew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsJ3-00000000jdQ-3ZTT; Wed, 19 Jun 2024 10:12:45 +0000 Received: from mail-lj1-x231.google.com ([2a00:1450:4864:20::231]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJsIb-00000000jSt-1Kvd for linux-arm-kernel@lists.infradead.org; Wed, 19 Jun 2024 10:12:29 +0000 Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2eaae2a6dc1so113036171fa.0 for ; Wed, 19 Jun 2024 03:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718791935; x=1719396735; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oy65aQubSD4tbmjRxefZecoIq4GXZIdFH64RPRpuevk=; b=FtRDXvly9W4lU4Nnq9s+jhFIxRnODj+W79gC9gcDBwSxUsBI8cLPIVQ5y/vhhCxHFT XdXsuCvN8d7NshgHatr7teZW2kySDjS8xDZCIqjG63zry67XmXBWt8Dd2j85u+uaS2q+ o/xswEjlnPIgPCfaeXSulES0nP0Lm1GPQq+2X0RzioBid6wSyPWpnMvmybIWh/fLTjbd XADP5H0kfg/S9jjQdla7hSQj/urNpNsIS1Wb4oZ7cHYNHUhXVWjL9t5P4eUQ0oSMPR2X ZjxGcM4EUZZ36WstUGuL2R4rM5SJ73hHKGk5ewV3i2OqIMcAILu+IeSC3/0YTzlYqhoV RNag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718791935; x=1719396735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oy65aQubSD4tbmjRxefZecoIq4GXZIdFH64RPRpuevk=; b=e5hoo3plcPuXY5gCnmnfnkVjBREJYXvWy1jwRov31/W7w8/NinIbbp8Zk5f7AHWsWO Lzp9o5KhWa/FA8DWc3TduoN3MHM+SUyYqt1dH0lYq2cn2K3ZrkeDbe8EphHHgZzp1Anw lgLOUNGfIDxn+qFnTCwwl6YYeBBbek6y0y2vMZ2BnNYjkn3fGFd9WT4P4g+uM8RDbmAg r4QhQJbimpeTaEzsUW0P5hjtXPlVKa1aYykHwKsQIVTetceGhBTmoiYVXD+9BNhDH+Tp Bv6ps+p3lK1J+4DVMEuLpRBtWzqn8beUkMH6yqwY03d5Gpr+Wf8GRUIDuGRgmUJ1+fu4 SLjQ== X-Forwarded-Encrypted: i=1; AJvYcCVIROLE7Gi8bw7Iw+Ll2UIdKK2Tv88sQzbuZk8PK9ifULtZWhtQAY1ETY4upYqUNvTDRiEu+MUg7SebsJrUU0sqXQ66fhxQ04Fr+Qo4dY5fDGM1b1g= X-Gm-Message-State: AOJu0YzkdcZqFQKqcONlPz6xNE7Q8+7YqOFwcK+EunfK2v97RGW3eS0g jE0ZDNSb2oFgguYOSyimB1EBnN5kJTpyoKVSnC6gK6xG29e98TAVG7XuycpBRro= X-Google-Smtp-Source: AGHT+IElXV90COGxqoASkehEGVkVUJcHtIY55Qg2BOMAPU5KAnXGT3gOKzusHP31PljuwUXHfU62qQ== X-Received: by 2002:a05:6512:448:b0:52c:80fb:ee76 with SMTP id 2adb3069b0e04-52ccaa594ecmr1527652e87.58.1718791934559; Wed, 19 Jun 2024 03:12:14 -0700 (PDT) Received: from localhost (p509153eb.dip0.t-ipconnect.de. [80.145.83.235]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42286fe9184sm255060585e9.13.2024.06.19.03.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 03:12:14 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , William Breathitt Gray , Lee Jones , Maxime Coquelin , Alexandre Torgue Cc: linux-pwm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thorsten Scherer Subject: [PATCH v2 5/5] pwm-stm32: Make use of parametrised register definitions Date: Wed, 19 Jun 2024 12:11:46 +0200 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3795; i=u.kleine-koenig@baylibre.com; h=from:subject:message-id; bh=I3iLNPbAvcDPk6Nw1QUlh23HxzYQPmXbPfOcTvZTTEE=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBmcq7q8zY1OOIGZ/eP/4KeEUhCpX1HQd4lcfMiE qgoW7JMHLiJATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZnKu6gAKCRCPgPtYfRL+ Toq4B/43LSGZu83nHMjrJj4MVPM4vtZms21eY4jgIjU0Gvcs7NtU61MHYKGY3AQOsxCPCNc9EvE t9VLqpH3lK2V4Haw2olqbsodrKWM508IzC24LQtqaqS8f1FqyzXuKaocLu4LYI2GsxUSURmkZh9 wRXRlhUikcxngpax3XlBNCaZ5ciBR68PmvbY+C2R7MgF6K4LkKRFYLr9PvvT9Gizpxp3hfYTAvP k1TXOVJaY2Tjv7E5t+9Advu+4qK49FdWMUpbx+/GfU21s6WTNwPLWCw7Rd14FtsQ/G8ymng3Vux Ga/FXD/DKAYkCorgEQiWt4mZDuWDWL/lOX6/6dpm/p8Lg+zi X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_031227_768466_EEEED75D X-CRM114-Status: GOOD ( 16.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is no semantic change, but it is a nicer on the eyes of a reader, because TIM_CCR1 + 4 * ch encodes internal register knowledge, while TIM_CCRx(ch + 1) keeps that information completely in the header defining the registers. While I expected this to not result in any changes in the binary, gcc 13 (as provided by Debian in the gcc-13-arm-linux-gnueabihf 13.2.0-12cross1 package) compiles the new version with an allmodconfig to more compact code: $ source/scripts/bloat-o-meter drivers/pwm/pwm-stm32.o-pre drivers/pwm/pwm-stm32.o add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-488 (-488) Function old new delta stm32_pwm_get_state 968 936 -32 stm32_pwm_apply_locked 1920 1464 -456 Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-stm32.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index a2f231d13a9f..49a76514b83e 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -360,7 +360,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch, dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk), (u64)NSEC_PER_SEC * (prescaler + 1)); - regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty); + regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty); /* Configure output mode */ shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; @@ -382,9 +382,9 @@ static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch, { u32 mask; - mask = TIM_CCER_CC1P << (ch * 4); + mask = TIM_CCER_CCxP(ch + 1); if (priv->have_complementary_output) - mask |= TIM_CCER_CC1NP << (ch * 4); + mask |= TIM_CCER_CCxNP(ch + 1); regmap_update_bits(priv->regmap, TIM_CCER, mask, polarity == PWM_POLARITY_NORMAL ? 0 : mask); @@ -402,9 +402,9 @@ static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) return ret; /* Enable channel */ - mask = TIM_CCER_CC1E << (ch * 4); + mask = TIM_CCER_CCxE(ch + 1); if (priv->have_complementary_output) - mask |= TIM_CCER_CC1NE << (ch * 4); + mask |= TIM_CCER_CCxNE(ch); regmap_set_bits(priv->regmap, TIM_CCER, mask); @@ -422,9 +422,9 @@ static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch) u32 mask; /* Disable channel */ - mask = TIM_CCER_CC1E << (ch * 4); + mask = TIM_CCER_CCxE(ch + 1); if (priv->have_complementary_output) - mask |= TIM_CCER_CC1NE << (ch * 4); + mask |= TIM_CCER_CCxNE(ch + 1); regmap_clear_bits(priv->regmap, TIM_CCER, mask); @@ -493,8 +493,8 @@ static int stm32_pwm_get_state(struct pwm_chip *chip, if (ret) goto out; - state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4)); - state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ? + state->enabled = ccer & TIM_CCER_CCxE(ch + 1); + state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; ret = regmap_read(priv->regmap, TIM_PSC, &psc); if (ret) @@ -502,7 +502,7 @@ static int stm32_pwm_get_state(struct pwm_chip *chip, ret = regmap_read(priv->regmap, TIM_ARR, &arr); if (ret) goto out; - ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr); + ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr); if (ret) goto out; @@ -702,7 +702,7 @@ static int stm32_pwm_suspend(struct device *dev) ccer = active_channels(priv); for (i = 0; i < chip->npwm; i++) { - mask = TIM_CCER_CC1E << (i * 4); + mask = TIM_CCER_CCxE(i + 1); if (ccer & mask) { dev_err(dev, "PWM %u still in use by consumer %s\n", i, chip->pwms[i].label);