From patchwork Wed Jun 19 18:45:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13704416 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02E5C1586F2 for ; Wed, 19 Jun 2024 18:46:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718822766; cv=none; b=YwB9A3+fi0Gebj0mh5NiSAnQpHXnYoXaWBR/58nknwWMw+X9vJOBZoGgZq9wyi3/WaohC3pOqkZsUR3KB0ZEE39lyK9FrSACtdDXFkjePJ2DxRB8SUPRMhqSxcFGFXRsAJddx4HjixKSkLPfnoh4A4QETocx9SQjL59/oROK9C0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718822766; c=relaxed/simple; bh=xQZfBrjg8Y1IyEOd4VaZKMauy6Z5Ydh+j9RZPVg6KZk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nKLMFkZHuJVvQA0shj7/ku0tsPYZOXNIru2QWCuzfPZGMqpMNL8H7rUh/UAA8thwi3HmeF4r+vIw2tivANd6zoZmjAmmaYEJWKU9QygXmBq4maLDzj2wy/GvdgiBpPuO9af2JRRNh+Uzum8a+8I+5yh6Q0jpiNxyEeXk1a1zCgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl; spf=none smtp.mailfrom=bgdev.pl; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b=gAL+o4vV; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b="gAL+o4vV" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-42172ed3487so1050875e9.0 for ; Wed, 19 Jun 2024 11:46:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1718822763; x=1719427563; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Of1uWBxSEjvKTQJleea6ZxhN8mHuCcwxXxdGI9uF93A=; b=gAL+o4vVw3jcnhq4PUbRpC74aZANSxP2sHepAl477+dHyw3hIiYtKS9iQYOzNR/aZl 7jG7iLmV3Eq2lBLWWUnK6mwdZDiAlv/bi52N9kVh0HgIjWYLsLw9y/CplYlywGk3vr6y jbwWpbF3OYq7oBGO3aLvdLCbprYHWo+51G/sASidqzssMBKA+L8kkhB6GGuyGhS9xZVE JSaetH0dSnfHCJDTFQf5ZtPdDY0xzTK2pTGGYRjhj1zHxTUF4OPeFToRxOpMpNMHNNyK pOO33h0IRjazGywi2++BR6mrtBlZK+3jLdtOMH6cxOopJbiuilV4xGuNYqMzbTENJT2D 5ItQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718822763; x=1719427563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Of1uWBxSEjvKTQJleea6ZxhN8mHuCcwxXxdGI9uF93A=; b=AR2zP+BaKKcT4WfjSVxKLAZ3hnPuSj6fRfXjC62y/FJKZXbJ0CUzaGAZ1mD2pA4vKo gAgRrIh8cYteAcEYOPNgb3TkHEjXokZMn5ch5afJQ30mBLNYwoXc3oR3FImm5ym9+3AH dqTclRw+vCTnL1pJgBLNCxKVqbmhgbKHdDIswbrTJ6Qjj7py2iqH2ayoWtjvl0/xWcML vDFNrD67mTw6Jna7PRM9YQoAhzGDRylsgk+BzNNEz6cjjjOaFvYKuZo5Mf/13pgKMsiU R/7T8M34UFhIb6o8JMeZf6H5wYUYJ3+tUkEaPDfov4Lz52EXAWuHb8BqYd7ABLbRwElX WxnQ== X-Forwarded-Encrypted: i=1; AJvYcCUfnkIhHg4vC2h1/MtgBVD+cuVk5OC/M/yXGBTkenotNnmfIxn2VVq9vdnJVFZVt4hHViS6MVa1KUTknUQtMoDQQR4qIYXEDZJ8SvSYhA== X-Gm-Message-State: AOJu0Yxbmh6tx9gddUOfW9RQ5RrniPKc0AlMuTjXomlQKhFgGzd/IWtB CYzMxvLbyeuLBBhPoeMeoJdK1e+amW0xI1iPoXT9SLNbIiStj/Q3VgvhjPVMw8g= X-Google-Smtp-Source: AGHT+IG94KmlBI+1kAFW/XzI6UK2YpoCtdBNr/zZ39tySmt8Nx0B1Rz4PfJT6D+Bu6Uwl7ILTiqtkg== X-Received: by 2002:a7b:cc13:0:b0:424:784c:b13b with SMTP id 5b1f17b1804b1-424784cb209mr15137645e9.13.1718822763293; Wed, 19 Jun 2024 11:46:03 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:dc:7e00:991f:deb8:4c5d:d73d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36098c8c596sm7594156f8f.14.2024.06.19.11.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 11:46:02 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 1/8] net: phy: add support for overclocked SGMII Date: Wed, 19 Jun 2024 20:45:42 +0200 Message-ID: <20240619184550.34524-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski The Aquantia AQR115C PHY supports the Overlocked SGMII mode. In order to support it in the driver, extend the PHY core with the new mode bits and pieces. Signed-off-by: Bartosz Golaszewski --- drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 13 ++++++++++++- include/linux/phy.h | 4 ++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 15f349e5995a..7cf87cae11f0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -138,6 +138,7 @@ int phy_interface_num_ports(phy_interface_t interface) case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_1000BASEKX: + case PHY_INTERFACE_MODE_OCSGMII: return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 02427378acfd..ce07d41a233f 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -128,6 +128,7 @@ static const phy_interface_t phylink_sfp_interface_preference[] = { PHY_INTERFACE_MODE_5GBASER, PHY_INTERFACE_MODE_2500BASEX, PHY_INTERFACE_MODE_SGMII, + PHY_INTERFACE_MODE_OCSGMII, PHY_INTERFACE_MODE_1000BASEX, PHY_INTERFACE_MODE_100BASEX, }; @@ -180,6 +181,7 @@ static unsigned int phylink_interface_signal_rate(phy_interface_t interface) switch (interface) { case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: /* 1.25Mbd */ + case PHY_INTERFACE_MODE_OCSGMII: return 1250; case PHY_INTERFACE_MODE_2500BASEX: /* 3.125Mbd */ return 3125; @@ -231,6 +233,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_OCSGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -515,6 +518,10 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, caps |= MAC_1000HD | MAC_1000FD; fallthrough; + case PHY_INTERFACE_MODE_OCSGMII: + caps |= MAC_2500FD; + fallthrough; + case PHY_INTERFACE_MODE_REVRMII: case PHY_INTERFACE_MODE_RMII: case PHY_INTERFACE_MODE_SMII: @@ -929,6 +936,7 @@ static int phylink_parse_mode(struct phylink *pl, case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_XLGMII: + case PHY_INTERFACE_MODE_OCSGMII: caps = ~(MAC_SYM_PAUSE | MAC_ASYM_PAUSE); caps = phylink_get_capabilities(pl->link_config.interface, caps, RATE_MATCH_NONE); @@ -1357,7 +1365,8 @@ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart) case MLO_AN_INBAND: link_state = pl->link_config; - if (link_state.interface == PHY_INTERFACE_MODE_SGMII) + if (link_state.interface == PHY_INTERFACE_MODE_SGMII || + link_state.interface == PHY_INTERFACE_MODE_OCSGMII) link_state.pause = MLO_PAUSE_NONE; break; @@ -3640,6 +3649,7 @@ void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state, break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_OCSGMII: case PHY_INTERFACE_MODE_QSGMII: phylink_decode_sgmii_word(state, lpa); break; @@ -3715,6 +3725,7 @@ int phylink_mii_c22_pcs_encode_advertisement(phy_interface_t interface, adv |= ADVERTISE_1000XPSE_ASYM; return adv; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_OCSGMII: case PHY_INTERFACE_MODE_QSGMII: return 0x0001; default: diff --git a/include/linux/phy.h b/include/linux/phy.h index e6e83304558e..73da0983d631 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -128,6 +128,7 @@ extern const int phy_10gbit_features_array[1]; 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Wed, 19 Jun 2024 11:46:04 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:dc:7e00:991f:deb8:4c5d:d73d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36098c8c596sm7594156f8f.14.2024.06.19.11.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 11:46:03 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 2/8] net: stmmac: qcom-ethqos: add support for 2.5G overlocked SGMII mode Date: Wed, 19 Jun 2024 20:45:43 +0200 Message-ID: <20240619184550.34524-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Add support for 2.5G speed in Overclocked SGMII mode to the QCom ethqos driver. Signed-off-by: Bartosz Golaszewski --- .../net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 80eb72bc6311..dac91bc72070 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -665,6 +665,14 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos) return val; } +static void qcom_ethqos_speed_mode_2500(struct net_device *ndev, void *data) +{ + struct stmmac_priv *priv = netdev_priv(ndev); + + priv->plat->max_speed = 2500; + priv->plat->phy_interface = PHY_INTERFACE_MODE_OCSGMII; +} + static int ethqos_configure(struct qcom_ethqos *ethqos) { return ethqos->configure_func(ethqos); @@ -787,6 +795,9 @@ static int qcom_ethqos_probe(struct platform_device *pdev) case PHY_INTERFACE_MODE_RGMII_TXID: ethqos->configure_func = ethqos_configure_rgmii; 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Wed, 19 Jun 2024 11:46:04 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 3/8] net: phy: aquantia: add missing include guards Date: Wed, 19 Jun 2024 20:45:44 +0200 Message-ID: <20240619184550.34524-4-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski The header is missing the include guards so add them. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Lunn --- drivers/net/phy/aquantia/aquantia.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/phy/aquantia/aquantia.h b/drivers/net/phy/aquantia/aquantia.h index c0e1fd9d7152..b8502793962e 100644 --- a/drivers/net/phy/aquantia/aquantia.h +++ b/drivers/net/phy/aquantia/aquantia.h @@ -6,6 +6,9 @@ * Author: Heiner Kallweit */ +#ifndef AQUANTIA_H +#define AQUANTIA_H + #include #include @@ -198,3 +201,5 @@ int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index, int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable); int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes); + +#endif /* AQUANTIA_H */ From patchwork Wed Jun 19 18:45:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13704419 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9AFD158DB2 for ; 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Wed, 19 Jun 2024 11:46:06 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:dc:7e00:991f:deb8:4c5d:d73d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36098c8c596sm7594156f8f.14.2024.06.19.11.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 11:46:06 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 4/8] net: phy: aquantia: add support for aqr115c Date: Wed, 19 Jun 2024 20:45:45 +0200 Message-ID: <20240619184550.34524-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Add support for a new model to the Aquantia driver. This PHY supports Overlocked SGMII mode with 2.5G speeds. Signed-off-by: Bartosz Golaszewski --- drivers/net/phy/aquantia/aquantia_main.c | 41 ++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c index 6c14355744b7..11da460698b0 100644 --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c @@ -29,6 +29,7 @@ #define PHY_ID_AQR113 0x31c31c40 #define PHY_ID_AQR113C 0x31c31c12 #define PHY_ID_AQR114C 0x31c31c22 +#define PHY_ID_AQR115C 0x31c31c33 #define PHY_ID_AQR813 0x31c31cb2 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 @@ -111,7 +112,6 @@ static u64 aqr107_get_stat(struct phy_device *phydev, int index) int len_h = stat->size - len_l; u64 ret; int val; - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); if (val < 0) return U64_MAX; @@ -368,7 +368,7 @@ static int aqr107_read_status(struct phy_device *phydev) phydev->interface = PHY_INTERFACE_MODE_RXAUI; break; case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + phydev->interface = PHY_INTERFACE_MODE_OCSGMII; break; default: phydev->interface = PHY_INTERFACE_MODE_NA; @@ -721,6 +721,18 @@ static int aqr113c_config_init(struct phy_device *phydev) return aqr107_fill_interface_modes(phydev); } +static int aqr115c_config_init(struct phy_device *phydev) +{ + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_OCSGMII) + return -ENODEV; + + phy_set_max_speed(phydev, SPEED_2500); + + return 0; +} + static int aqr107_probe(struct phy_device *phydev) { int ret; @@ -999,6 +1011,30 @@ static struct phy_driver aqr_driver[] = { .led_hw_control_get = aqr_phy_led_hw_control_get, .led_polarity_set = aqr_phy_led_polarity_set, }, +{ + PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), + .name = "Aquantia AQR115C", + .probe = aqr107_probe, + .get_rate_matching = aqr107_get_rate_matching, + .config_init = aqr115c_config_init, + .config_aneg = aqr_config_aneg, + .config_intr = aqr_config_intr, + .handle_interrupt = aqr_handle_interrupt, + .read_status = aqr107_read_status, + .get_tunable = aqr107_get_tunable, + .set_tunable = aqr107_set_tunable, + .suspend = aqr107_suspend, + .resume = aqr107_resume, + .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, + .link_change_notify = aqr107_link_change_notify, + .led_brightness_set = aqr_phy_led_brightness_set, + .led_hw_is_supported = aqr_phy_led_hw_is_supported, + .led_hw_control_set = aqr_phy_led_hw_control_set, + .led_hw_control_get = aqr_phy_led_hw_control_get, + .led_polarity_set = aqr_phy_led_polarity_set, +}, { PHY_ID_MATCH_MODEL(PHY_ID_AQR813), .name = "Aquantia AQR813", @@ -1042,6 +1078,7 @@ static struct mdio_device_id __maybe_unused aqr_tbl[] = { { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, { } }; 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Wed, 19 Jun 2024 11:46:07 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 5/8] net: phy: aquantia: wait for FW reset before checking the vendor ID Date: Wed, 19 Jun 2024 20:45:46 +0200 Message-ID: <20240619184550.34524-6-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Checking the firmware register before it boots makes no sense, it will report 0 even if FW is loaded. Always wait for FW to boot before continuing. Signed-off-by: Bartosz Golaszewski --- drivers/net/phy/aquantia/aquantia.h | 1 + drivers/net/phy/aquantia/aquantia_firmware.c | 4 ++++ drivers/net/phy/aquantia/aquantia_main.c | 6 +++--- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/aquantia/aquantia.h b/drivers/net/phy/aquantia/aquantia.h index b8502793962e..2465345081f8 100644 --- a/drivers/net/phy/aquantia/aquantia.h +++ b/drivers/net/phy/aquantia/aquantia.h @@ -201,5 +201,6 @@ int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index, int aqr_phy_led_active_low_set(struct phy_device *phydev, int index, bool enable); int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes); +int aqr_wait_reset_complete(struct phy_device *phydev); #endif /* AQUANTIA_H */ diff --git a/drivers/net/phy/aquantia/aquantia_firmware.c b/drivers/net/phy/aquantia/aquantia_firmware.c index 0c9640ef153b..524627a36c6f 100644 --- a/drivers/net/phy/aquantia/aquantia_firmware.c +++ b/drivers/net/phy/aquantia/aquantia_firmware.c @@ -353,6 +353,10 @@ int aqr_firmware_load(struct phy_device *phydev) { int ret; + ret = aqr_wait_reset_complete(phydev); + if (ret) + return ret; + /* Check if the firmware is not already loaded by pooling * the current version returned by the PHY. If 0 is returned, * no firmware is loaded. diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c index 11da460698b0..eab779db225c 100644 --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c @@ -441,7 +441,7 @@ static int aqr107_set_tunable(struct phy_device *phydev, * The chip also provides a "reset completed" bit, but it's cleared after * read. Therefore function would time out if called again. */ -static int aqr107_wait_reset_complete(struct phy_device *phydev) +int aqr_wait_reset_complete(struct phy_device *phydev) { int val; @@ -494,7 +494,7 @@ static int aqr107_config_init(struct phy_device *phydev) WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, "Your devicetree is out of date, please update it. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 6/8] net: stmmac: provide the link_up() callback Date: Wed, 19 Jun 2024 20:45:47 +0200 Message-ID: <20240619184550.34524-7-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Provide drivers with means to react to link-up events in the form of another platform callback. Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++ include/linux/stmmac.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 5ddbb0d44373..644bc8a24661 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1006,6 +1006,9 @@ static void stmmac_mac_link_up(struct phylink_config *config, struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); u32 old_ctrl, ctrl; + if (priv->plat->link_up) + priv->plat->link_up(priv->dev, priv->plat->bsp_priv); + if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && priv->plat->serdes_powerup) priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 9c54f82901a1..9dc54d6d65ae 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -271,6 +271,7 @@ struct plat_stmmacenet_data { void (*dump_debug_regs)(void *priv); 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Wed, 19 Jun 2024 11:46:09 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 7/8] net: stmmac: provide the open() callback Date: Wed, 19 Jun 2024 20:45:48 +0200 Message-ID: <20240619184550.34524-8-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Provide drivers with means of injecting additional code into the stmmac_open() function. Signed-off-by: Bartosz Golaszewski --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +++ include/linux/stmmac.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 644bc8a24661..5f628176d994 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3953,6 +3953,9 @@ static int __stmmac_open(struct net_device *dev, if (ret < 0) return ret; + if (priv->plat->open) + priv->plat->open(dev, priv->plat->bsp_priv); + if ((!priv->hw->xpcs || xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { ret = stmmac_init_phy(dev); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 9dc54d6d65ae..59991b38cadb 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -262,6 +262,7 @@ struct plat_stmmacenet_data { void (*serdes_powerdown)(struct net_device *ndev, void *priv); void (*speed_mode_2500)(struct net_device *ndev, void *priv); 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Wed, 19 Jun 2024 11:46:10 -0700 (PDT) From: Bartosz Golaszewski To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH net-next 8/8] net: stmmac: qcom-ethqos: add a DMA-reset quirk for sa8775p-ride-r3 Date: Wed, 19 Jun 2024 20:45:49 +0200 Message-ID: <20240619184550.34524-9-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240619184550.34524-1-brgl@bgdev.pl> References: <20240619184550.34524-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski On sa8775p-ride the RX clocks from the AQR115C PHY are not available at the time of the DMA reset so we need to loop TX clocks to RX and then disable loopback after link-up. Use the provided callbacks to do it for this board. Signed-off-by: Bartosz Golaszewski --- .../stmicro/stmmac/dwmac-qcom-ethqos.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index dac91bc72070..ec43449d0252 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -21,6 +21,7 @@ #define RGMII_IO_MACRO_CONFIG2 0x1C #define RGMII_IO_MACRO_DEBUG1 0x20 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28 +#define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4 /* RGMII_IO_MACRO_CONFIG fields */ #define RGMII_CONFIG_FUNC_CLK_EN BIT(30) @@ -79,6 +80,9 @@ #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14) #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15) +/* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */ +#define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3) + #define SGMII_10M_RX_CLK_DVDR 0x31 struct ethqos_emac_por { @@ -678,6 +682,29 @@ static int ethqos_configure(struct qcom_ethqos *ethqos) return ethqos->configure_func(ethqos); } +static void qcom_ethqos_set_serdes_loopback(struct qcom_ethqos *ethqos, + bool enable) +{ + rgmii_updatel(ethqos, + SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN, + enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0, + EMAC_WRAPPER_SGMII_PHY_CNTRL1); +} + +static void qcom_ethqos_open(struct net_device *pdev, void *priv) +{ + struct qcom_ethqos *ethqos = priv; + + qcom_ethqos_set_serdes_loopback(ethqos, true); +} + +static void qcom_ethqos_link_up(struct net_device *ndev, void *priv) +{ + struct qcom_ethqos *ethqos = priv; + + qcom_ethqos_set_serdes_loopback(ethqos, false); +} + static void ethqos_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) { struct qcom_ethqos *ethqos = priv; @@ -861,6 +888,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev) if (data->dma_addr_width) plat_dat->host_dma_width = data->dma_addr_width; + if (of_device_is_compatible(np, "qcom,sa8775p-ethqos") && + ethqos->phy_mode == PHY_INTERFACE_MODE_OCSGMII) { + plat_dat->open = qcom_ethqos_open; + plat_dat->link_up = qcom_ethqos_link_up; + } + if (ethqos->serdes_phy) { plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup; plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;