From patchwork Thu Jun 20 07:37:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13704915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31E40C27C79 for ; Thu, 20 Jun 2024 07:37:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7OSv1FiS0iLF2SIYsC9Vy089XEQIvQEpbNtADRhQU5k=; b=4+wm4178t4fSM5AmKPmJuQ4uG6 S2OuMGnbp3j+sfU2sApHdCwLvYEurQbD/a/WEJmhqpbG52b7lODLIM0NEZmGId4Ygds9Mp/8zvAkk jFu8uLiqaLkVnBHS8MaLGZKY5T48GH7JPHopCvOJw4AsqVA6goKLzTr7jvoCcy0jfafs2ltzOw1Q2 MolAJMUrpVcT1nikJiU/lrnoWpijTwsXRXTX/VZ2sbQGnFJ8FJWc1L2vFdjGKm3AtPcBU3qZzE274 NnSi54SSOa50UuWM8+s/HZ3s9hp+/iJNuhncXbhaPVCgJntICp5GzRQJCBgayMlZgvnWcOUhcUvsg q3K3or/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMM-000000040ZQ-1P1i; Thu, 20 Jun 2024 07:37:30 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMH-000000040YC-2Jl3 for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2024 07:37:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 2F80ACE2392; Thu, 20 Jun 2024 07:37:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57498C2BD10; Thu, 20 Jun 2024 07:37:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718869042; bh=wWsG+klFvcpiixryAZ+uWO3LiazmvaYTn5a544yY6+k=; h=From:To:Subject:Date:In-Reply-To:References:From; b=p5hTjTiVNXdzJwlt9FYk9CEHnIYRR6KS8S2/GkcRQrqfeIl25g6tUGQi9CMZUDgb1 p9pISHlLFn9l4HL3MqltbJzKImANd+XM6f18nxxgKcjt00VmchvT+LyBk1urclkFPg KVMV9MydFPM69KDZZNN3mgpWDrfyzKVuYbrAiIf4nnFI338l3KDmc/SU36OyLGrao+ /7W8pMO9MAHFVq5iCcQzH0V8M1NFqICvGi8LDg+QrcaxBj4fhu0nnGnJT8yW2CSq3E WK9QKhTM3WwhHm186ox6zvxGmDrnPF3E2IN73uUA0ASpY8l43SNXyUZ0HC0lVDalL3 gA/1FjoIC2BJA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 1/4] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1 Date: Thu, 20 Jun 2024 09:37:12 +0200 Message-ID: <20240620073715.13560-2-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240620073715.13560-1-kabel@kernel.org> References: <20240620073715.13560-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_003725_811119_E253C700 X-CRM114-Status: GOOD ( 11.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár IRQs 0 (IPI) and 1 (MSI) are handled internally by this driver, generic_handle_domain_irq() is never called for these IRQs. Disallow mapping these IRQs. Signed-off-by: Pali Rohár [ changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 4b021a67bdfe..f488c35d9130 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -566,6 +566,10 @@ static struct irq_chip armada_370_xp_irq_chip = { static int armada_370_xp_mpic_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { + /* IRQs 0 and 1 cannot be mapped, they are handled internally */ + if (hw <= 1) + return -EINVAL; + armada_370_xp_irq_mask(irq_get_irq_data(virq)); if (!is_percpu_irq(hw)) writel(hw, per_cpu_int_base + From patchwork Thu Jun 20 07:37:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13704916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 062C2C2BB85 for ; Thu, 20 Jun 2024 07:37:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=20CA5prDqUxWAM1Z+Eol6q+Z786udVSKpzg64UmQk+s=; b=tCV9z8y95IIX7d/reXEu9ijqgh bH98UhGHg3k++Zq9bzSjnWyESAY8LGfL9Tygyrl8vdvEejoHDerbaoYPI7LjtUmqs4vNhBctOKgt6 vE+bynwUg3LGXQbz/NtqE/rsluFRqdlpT0TOS1o5VZiLK+iNuKxIKjBf1ZohYSUfj3JR1gfObJifb myja0RNrV7JGG+3P15W1ym/KFxrfu/xarp17I8aADW8kVpdE7t50vlENFa/XcWXTVNdtjR2Q2JSD0 W2IuTTAbP+FgxcInIMncDsJHf22M3+Pg3e3YSPVa8JlyOpEMyGSmFIbr7c8mrZ5dYaUKhr+E2sIz9 kkkBB1sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMN-000000040Zz-1LAp; Thu, 20 Jun 2024 07:37:31 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMJ-000000040Yd-1nDG for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2024 07:37:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id AA112CE23BA; Thu, 20 Jun 2024 07:37:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEB78C32781; Thu, 20 Jun 2024 07:37:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718869044; bh=WPti5GNnym1yh8L19XY39E6BdWNRYNdoXbDLMmL10TM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=NyBMFnFsj3Z2b2D2EIng2YfvMiwQf+AcjLhRdCceNC/YE6AuGmO3OJCCmygZK7wJI Yij/NKj7kMEaOlsE9JzjqVs2PPG/TbVK3gOyfpPOh4RthIdsk67A57XMSOXhBt8l/6 GCpzasGyvXMPgjjY3h0VZWr8Vdpk759AcS5+YdWSdgi+FlMTMunKDW28YW94HIfSC4 I1gtLMNKwcjOmL85i4p9JhE7ta/x0ejBjqaq1jymjqFnqG1XBKbHcm/U/5wF0Vb/EQ 3Vc/on9i8oMzwqdMQslkYc2MnAFItIt4ZmITr8HinU7pbGMGmxWOBWfk6BjubtLVMM ZfZJaT7bhzdYg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 2/4] irqchip/armada-370-xp: Only call ipi_resume() if IPI is available Date: Thu, 20 Jun 2024 09:37:13 +0200 Message-ID: <20240620073715.13560-3-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240620073715.13560-1-kabel@kernel.org> References: <20240620073715.13560-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_003727_676310_43F9E40C X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár IPI is available only on systems where the mpic controller does not have a parent IRQ defined (e.g. on Armada XP). If a parent IRQ is defined, inter-processor interrupts are handled by an interrupt controller higher in the hierarchy (most probably a parent GIC). Only call ipi_resume() on systems where IPI is available in the mpic controller. Signed-off-by: Pali Rohár [ refactored a little and changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index f488c35d9130..ea95e327f672 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -156,6 +157,17 @@ static DEFINE_MUTEX(msi_used_lock); static phys_addr_t msi_doorbell_addr; #endif +static inline bool is_ipi_available(void) +{ + /* + * We distinguish IPI availability in the IC by the IC not having a + * parent irq defined. If a parent irq is defined, there is a parent + * interrupt controller (e.g. GIC) that takes care of inter-processor + * interrupts. + */ + return parent_irq <= 0; +} + static inline bool is_percpu_irq(irq_hw_number_t irq) { if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) @@ -527,7 +539,8 @@ static void armada_xp_mpic_reenable_percpu(void) armada_370_xp_irq_unmask(data); } - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); armada_370_xp_msi_reenable_percpu(); } @@ -750,7 +763,8 @@ static void armada_370_xp_mpic_resume(void) if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); } static struct syscore_ops armada_370_xp_mpic_syscore_ops = { From patchwork Thu Jun 20 07:37:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13704917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26A78C2BA18 for ; Thu, 20 Jun 2024 07:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6dlKFdQ6efrdTQL7n/pqXsusfdVJGIpgAR2nleO4k00=; b=oRmwwJDFWDfT+NY8AsnRckMxY0 wJhy4g1CFpp+wN6pmjsptraTy0olq3RsnQE9vpMS2ya3rw9nSe4GZnnB11G8q0RATlHVTcZn2ZFCr xdlWRJClwmSV7gyCHnwLNR1k3G3XI5Dcm+dOMqNpWL/tyycQOeNlwkCXrJYLwi3nged5DrhfhXPbF zeM2NYbfl28IqBkIGUttgy9BOuAsLN1c4umuKb20dAaVqNwx0fpmTIJGPMXYQ1Wv5MGVwXkKBrWvX ZiUPI8qcOWvg0FLdzSc8ykwIBHVG9IC2Hz+O8QlUamnQLOBeOw7c+E5wFQpGtns3D/FiVFLLe5KrK PkjX5EmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMZ-000000040eH-2Mln; Thu, 20 Jun 2024 07:37:43 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMM-000000040ZD-0SMc for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2024 07:37:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 2780FCE2392; Thu, 20 Jun 2024 07:37:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4FA3FC4AF07; Thu, 20 Jun 2024 07:37:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718869047; bh=dZrLVKTdPiccjRN/nS6wrH8xra7iqcEJWj9cQdWfU3Y=; h=From:To:Subject:Date:In-Reply-To:References:From; b=TwUlI6LUTvgP/4jvAZ6dmmi8D1DxbAhxLigXnM+CPkwMd+6pyOWvtufQlpVEJb0Vg icJiChJ36CT+NTOPXPFYzxZXM8HpfSJh/waGxRuAMJWCAwcUJ8c96+wwb9Ggx3a0Gw hX/ojD8tfcqOaA5uwrl80Oy/3JD7KNSryLOl6Osbx69B39vcjCilOC59z6Z4KJRaHz tZpUlhwfUjtLgy7s+wI16BLTyDbzPA5lBlW2qb7I3xIySInDkP1woIc4d1tu1gvUP+ sUM3B92Zfg4Mqcl5cVc+kxEJOhmb+MUcbXC6jhpzD1vCEgrj/ZTvgkr0qtaBw3YS8k 5smwr+E4EesZA== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 3/4] irqchip/armada-370-xp: Do not touch IPI registers on platforms without IPI Date: Thu, 20 Jun 2024 09:37:14 +0200 Message-ID: <20240620073715.13560-4-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240620073715.13560-1-kabel@kernel.org> References: <20240620073715.13560-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_003730_842982_86742F53 X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár On platforms where IPI is not available in the MPIC, the IPI registers instead represent an additional set of MSI interrupt registers (currently unused by the driver). Do not touch these registers on platforms where IPI is not available in the MPIC. Signed-off-by: Pali Rohár [ refactored, changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index ea95e327f672..aca64de4e3f8 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -508,6 +508,9 @@ static void armada_xp_mpic_smp_cpu_init(void) for (i = 0; i < nr_irqs; i++) writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); + if (!is_ipi_available()) + return; + /* Disable all IPIs */ writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); @@ -758,7 +761,7 @@ static void armada_370_xp_mpic_resume(void) /* Reconfigure doorbells for IPIs and MSIs */ writel(doorbell_mask_reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); - if (doorbell_mask_reg & IPI_DOORBELL_MASK) + if (is_ipi_available() && (doorbell_mask_reg & IPI_DOORBELL_MASK)) writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); @@ -809,13 +812,18 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, BUG_ON(!armada_370_xp_mpic_domain); irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED); + /* + * Initialize parent_irq before calling any other functions, since it is + * used to distinguish between IPI and non-IPI platforms. + */ + parent_irq = irq_of_parse_and_map(node, 0); + /* Setup for the boot CPU */ armada_xp_mpic_perf_init(); armada_xp_mpic_smp_cpu_init(); armada_370_xp_msi_init(node, main_int_res.start); - parent_irq = irq_of_parse_and_map(node, 0); if (parent_irq <= 0) { irq_set_default_host(armada_370_xp_mpic_domain); set_handle_irq(armada_370_xp_handle_irq); From patchwork Thu Jun 20 07:37:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13704918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DA77C27C79 for ; Thu, 20 Jun 2024 07:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sih01dttlMs+jI0nvrlUQfl/B5O4IdyBr0RxqlwQQV0=; b=cStffi+8jXzH7lbB2d0RZTFeRW VE8U0pU/vqhaGCBuITWnpt495Di/YKKw7QvC3cG82Bb5SOczQ63vHrUUkvdrAfbIcX8VX6qZQyN8D WJliWKG5t75QPwBiemHO9/fb7FszeCrJQdnuMy7M6qWcJG2QIwal5kJ9YHqVsOXXfzCVFQBh8EaQJ gcIELBAJONjv3Hght7lX2NCB5Bf9sojauxAhHWQtG1JqfyPmDNhQGf/Egb6hcImISIfPBclcialHE X4PGCc3hSiLc1jXPnKXFFdbTWTkWwyE9aaYHdJQg27JaAQqf5v2Nt0heedW8071qCuQC8+ect9HAY NoX+tgIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMa-000000040er-3kEo; Thu, 20 Jun 2024 07:37:44 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMN-000000040ZR-1H4a for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2024 07:37:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1DEE9620DF; Thu, 20 Jun 2024 07:37:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C1CA3C2BD10; Thu, 20 Jun 2024 07:37:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718869049; bh=+yDj1WsfxKfcGcJJbAgNqkl2I7QzhkT48z7zcQ/GEVw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=uFU/1gI+HEZ1g6csW+g1Tg5XsvZ5O8iycD0m9pXLUKs90c/8FfkK5y+DR2ZS3KxjM yupR/Pb5t3pe/I/MTeET1EYCefukAgguvn3WK666Jg0VgAzOJ0LKU2jcywWKU8FHvw kOysK0BGYjh6R0+hBYc+HL0TXVllHkS8qCT4ID5wd8kgLWMGoKE29t2glEnTW+A+A3 1z37ppFW4TuIW3ys4Glhn++uzuleIWDd8Q4k4O9OY+4P9AZ4emzIB2i+YnyTwmUYgC jCzHNyUb8rLJUng14CwarfedvJr8BKkLmBV73jPB9z8FIs17VT23HG2oj2dVVUNwrJ 5vTXZPqwfictg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 4/4] irqchip/armada-370-xp: Add support for 32 MSI interrupts on non-IPI platforms Date: Thu, 20 Jun 2024 09:37:15 +0200 Message-ID: <20240620073715.13560-5-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240620073715.13560-1-kabel@kernel.org> References: <20240620073715.13560-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_003731_533202_ADA6332C X-CRM114-Status: GOOD ( 19.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár The doorbell interrupts have the following layout on IPI vs no-IPI platforms: | 0...7 | 8...15 | 16...31 | ------------------+---------+----------+---------------------+ IPI platform | IPI | n/a | MSI | ------------------+---------+----------+---------------------+ non-IPI platform | MSI | ------------------+------------------------------------------+ Currently the driver only allows for the upper 16...31 interrupts for MSI domain (i.e. the MSI domain has only 16 interrupts). On platforms where IPI is not available, we can use whole 32 MSI interrupts. Implement support also for the lower 16 MSI interrupts on non-IPI platforms. Signed-off-by: Pali Rohár [ refactored, changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 77 +++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index aca64de4e3f8..924a574f28ea 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include @@ -136,6 +137,7 @@ #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +/* IPI and MSI interrupt definitions for IPI platforms */ #define IPI_DOORBELL_START (0) #define IPI_DOORBELL_END (8) #define IPI_DOORBELL_MASK 0xFF @@ -144,6 +146,14 @@ #define PCI_MSI_DOORBELL_END (32) #define PCI_MSI_DOORBELL_MASK 0xFFFF0000 +/* MSI interrupt definitions for non-IPI platforms */ +#define PCI_MSI_FULL_DOORBELL_START 0 +#define PCI_MSI_FULL_DOORBELL_NR 32 +#define PCI_MSI_FULL_DOORBELL_END 32 +#define PCI_MSI_FULL_DOORBELL_MASK GENMASK(31, 0) +#define PCI_MSI_FULL_DOORBELL_SRC0_MASK GENMASK(15, 0) +#define PCI_MSI_FULL_DOORBELL_SRC1_MASK GENMASK(31, 16) + static void __iomem *per_cpu_int_base; static void __iomem *main_int_base; static struct irq_domain *armada_370_xp_mpic_domain; @@ -152,7 +162,7 @@ static int parent_irq; #ifdef CONFIG_PCI_MSI static struct irq_domain *armada_370_xp_msi_domain; static struct irq_domain *armada_370_xp_msi_inner_domain; -static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR); +static DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR); static DEFINE_MUTEX(msi_used_lock); static phys_addr_t msi_doorbell_addr; #endif @@ -168,6 +178,30 @@ static inline bool is_ipi_available(void) return parent_irq <= 0; } +static inline u32 msi_doorbell_mask(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_MASK : + PCI_MSI_FULL_DOORBELL_MASK; +} + +static inline unsigned int msi_doorbell_start(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_START : + PCI_MSI_FULL_DOORBELL_START; +} + +static inline unsigned int msi_doorbell_size(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_NR : + PCI_MSI_FULL_DOORBELL_NR; +} + +static inline unsigned int msi_doorbell_end(void) +{ + return is_ipi_available() ? PCI_MSI_DOORBELL_END : + PCI_MSI_FULL_DOORBELL_END; +} + static inline bool is_percpu_irq(irq_hw_number_t irq) { if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) @@ -225,7 +259,7 @@ static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg msg->address_lo = lower_32_bits(msi_doorbell_addr); msg->address_hi = upper_32_bits(msi_doorbell_addr); - msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START); + msg->data = BIT(cpu + 8) | (data->hwirq + msi_doorbell_start()); } static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, @@ -258,7 +292,7 @@ static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq, int hwirq, i; mutex_lock(&msi_used_lock); - hwirq = bitmap_find_free_region(msi_used, PCI_MSI_DOORBELL_NR, + hwirq = bitmap_find_free_region(msi_used, msi_doorbell_size(), order_base_2(nr_irqs)); mutex_unlock(&msi_used_lock); @@ -295,9 +329,10 @@ static void armada_370_xp_msi_reenable_percpu(void) u32 reg; /* Enable MSI doorbell mask and combined cpu local interrupt */ - reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) - | PCI_MSI_DOORBELL_MASK; + reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + reg |= msi_doorbell_mask(); writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + /* Unmask local doorbell interrupt */ writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); } @@ -309,7 +344,7 @@ static int armada_370_xp_msi_init(struct device_node *node, ARMADA_370_XP_SW_TRIG_INT_OFFS; armada_370_xp_msi_inner_domain = - irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR, + irq_domain_add_linear(NULL, msi_doorbell_size(), &armada_370_xp_msi_domain_ops, NULL); if (!armada_370_xp_msi_inner_domain) return -ENOMEM; @@ -325,6 +360,10 @@ static int armada_370_xp_msi_init(struct device_node *node, armada_370_xp_msi_reenable_percpu(); + /* Unmask low 16 MSI irqs on non-IPI platforms */ + if (!is_ipi_available()) + writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + return 0; } #else @@ -619,20 +658,20 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) u32 msimask, msinr; msimask = readl_relaxed(per_cpu_int_base + - ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) - & PCI_MSI_DOORBELL_MASK; + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); + msimask &= msi_doorbell_mask(); writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); - for (msinr = PCI_MSI_DOORBELL_START; - msinr < PCI_MSI_DOORBELL_END; msinr++) { + for (msinr = msi_doorbell_start(); + msinr < msi_doorbell_end(); msinr++) { unsigned int irq; if (!(msimask & BIT(msinr))) continue; - irq = msinr - PCI_MSI_DOORBELL_START; + irq = msinr - msi_doorbell_start(); generic_handle_domain_irq(armada_370_xp_msi_inner_domain, irq); } @@ -661,7 +700,7 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) continue; - if (irqn == 1) { + if (irqn == 0 || irqn == 1) { armada_370_xp_handle_msi_irq(NULL, true); continue; } @@ -722,6 +761,7 @@ static int armada_370_xp_mpic_suspend(void) static void armada_370_xp_mpic_resume(void) { + bool src0 = false, src1 = false; int nirqs; irq_hw_number_t irq; @@ -761,9 +801,18 @@ static void armada_370_xp_mpic_resume(void) /* Reconfigure doorbells for IPIs and MSIs */ writel(doorbell_mask_reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); - if (is_ipi_available() && (doorbell_mask_reg & IPI_DOORBELL_MASK)) + + if (is_ipi_available()) { + src0 = doorbell_mask_reg & IPI_DOORBELL_MASK; + src1 = doorbell_mask_reg & PCI_MSI_DOORBELL_MASK; + } else { + src0 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC0_MASK; + src1 = doorbell_mask_reg & PCI_MSI_FULL_DOORBELL_SRC1_MASK; + } + + if (src0) writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) + if (src1) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); if (is_ipi_available())