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[2003:eb:5f2e:9b00:caea:2d1d:6a49:249f]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6f56fa415dsm780915466b.220.2024.06.20.07.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 07:42:31 -0700 (PDT) From: iansdannapel@gmail.com To: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Cc: Ian Dannapel Subject: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver Date: Thu, 20 Jun 2024 16:42:17 +0200 Message-Id: <20240620144217.124733-1-iansdannapel@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add a new driver for loading binary firmware using "SPI passive programming" on Efinix FPGAs. Signed-off-by: Ian Dannapel --- drivers/fpga/Kconfig | 8 ++ drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 219 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 228 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..cb3a6628fa71 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI FPGA manager driver support for Xilinx FPGA configuration over slave serial interface. +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI passive" + depends on SPI + help + This option enables support for the FPGA manager driver to configure + Efinix Trion and Titanium Series FPGAs over SPI using passive serial + mode. + config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..adbd51d2cd1e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c new file mode 100644 index 000000000000..7f7d7e6714ae --- /dev/null +++ b/drivers/fpga/efinix-spi.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Trion and Titanium Series FPGA SPI Passive Programming Driver + * + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel + * + * Manage Efinix FPGA firmware that is loaded over SPI using + * the serial configuration interface. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *done; + struct gpio_desc *reset; + struct gpio_desc *cs; + enum fpga_mgr_states state; +}; + +static int get_done_gpio(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret = 0; + + if (conf->done) { + ret = gpiod_get_value(conf->done); + if (ret < 0) + dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); + } + + return ret; +} + +static void reset(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + gpiod_set_value(conf->reset, 1); + /* wait tCRESET_N */ + usleep_range(5, 15); + gpiod_set_value(conf->reset, 0); + conf->state = FPGA_MGR_STATE_RESET; +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + return conf->state; +} + +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + char data[13] = {0}; + + return spi_write(conf->spi, data, sizeof(data)); +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EINVAL; + } + + /* reset with chip select active */ + gpiod_set_value(conf->cs, 1); + usleep_range(5, 15); + reset(mgr); + + /* wait tDMIN */ + usleep_range(100, 150); + + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret; + + ret = spi_write(conf->spi, buf, count); + if (ret) { + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", + ret); + return ret; + } + + /* append at least 100 clock cycles */ + efinix_spi_apply_clk_cycles(mgr); + + /* release chip select */ + gpiod_set_value(conf->cs, 0); + + return 0; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct efinix_spi_conf *conf = mgr->priv; + unsigned long timeout = + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + bool expired = false; + int done; + + if (conf->done) { + while (!expired) { + expired = time_after(jiffies, timeout); + + done = get_done_gpio(mgr); + if (done < 0) + return done; + + if (done) + break; + } + } + + if (expired) + return -ETIMEDOUT; + + /* wait tUSER */ + usleep_range(75, 125); + + return 0; +} + +static const struct fpga_manager_ops efinix_spi_ops = { + .state = efinix_spi_state, + .write_init = efinix_spi_write_init, + .write = efinix_spi_write, + .write_complete = efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi = spi; + conf->state = FPGA_MGR_STATE_UNKNOWN; + + conf->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->reset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->reset), + "Failed to get RESET gpio\n"); + + conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH); + if (IS_ERR(conf->cs)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), + "Failed to get CHIP_SELECT gpio\n"); + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf->done = devm_gpiod_get_optional(&spi->dev, "done", GPIOD_IN); + if (IS_ERR(conf->done)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->done), + "Failed to get DONE gpio\n"); + + mgr = devm_fpga_mgr_register(&spi->dev, + "Efinix SPI Passive Programming FPGA Manager", + &efinix_spi_ops, conf); + + return PTR_ERR_OR_ZERO(mgr); +} + +#ifdef CONFIG_OF +static const struct of_device_id efnx_spi_of_match[] = { + { .compatible = "efnx,fpga-spi-passive", }, + {} +}; +MODULE_DEVICE_TABLE(of, efnx_spi_of_match); +#endif + +static const struct spi_device_id efinix_ids[] = { + { "fpga-spi-passive", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + + +static struct spi_driver efinix_spi_passive_driver = { + .driver = { + .name = "efnx-fpga-spi-passive", + .of_match_table = of_match_ptr(efnx_spi_of_match), + }, + .probe = efinix_spi_probe, + .id_table = efinix_ids, +}; + +module_spi_driver(efinix_spi_passive_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel "); +MODULE_DESCRIPTION("Load Efinix FPGA firmware over SPI passive"); From patchwork Thu Jun 20 14:44:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Dannapel X-Patchwork-Id: 13705635 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0757C1AE85D; Thu, 20 Jun 2024 14:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718894693; cv=none; b=hTa7B0lyq2mk9jo+LVwlx94zVmWLWXfZuTo9sinpaxmCu3e0nev87MS/Syz2do3guq2gRgBGqZOPvIiCNVz22i7V7M8YDqJSRsolxbyxrvz6mO/2iPEbYp2xewyOH0RyZxWsbD/d+GqnMPoP2Rq5KcjgBAcyJIxCTvm4Gx6cqRw= ARC-Message-Signature: i=1; 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[2003:eb:5f2e:9b00:caea:2d1d:6a49:249f]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cb741e782sm9706982a12.64.2024.06.20.07.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jun 2024 07:44:49 -0700 (PDT) From: iansdannapel@gmail.com To: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Dannapel Subject: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming binding description Date: Thu, 20 Jun 2024 16:44:40 +0200 Message-Id: <20240620144440.125374-1-iansdannapel@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add device tree binding documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel --- .../bindings/fpga/efnx,fpga-passive-spi.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.yaml diff --git a/Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.yaml b/Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.yaml new file mode 100644 index 000000000000..855ceb3b89e8 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efnx,fpga-passive-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +description: | + Efinix Trion and Titanium Series FPGAs support a method of loading the + bitstream over what is referred to as "SPI Passive Programming". + Only serial (1x bus width) is supported, setting the programming mode + is not in the scope the this manager and must be done elsewhere. + + References: + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efnx,fpga-spi-passive + + spi-cpha: true + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset pin (low active) + maxItems: 1 + + cs-gpios: + description: + chip-select pin (low active) + maxItems: 1 + + done-gpios: + description: + optional programming done pin, referred as CDONE (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - cs-gpios + +additionalProperties: false + +examples: + - | + &spi2 { + #address-cells = <1>; + #size-cells = <0>; + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "efnx,fpga-spi-passive"; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reg = <0>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +...