From patchwork Thu Jun 20 21:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13706394 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95A5642AA0 for ; Thu, 20 Jun 2024 21:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918473; cv=none; b=NqEFnDhoVs36zgyITTYSKMQL2PEenZCpyDc7Wzi9CihgCf0lkDIENW1f5Uw1HNSXIu4UHY1AJsSyRx5C4RoPVtIwZaUmxz7+MXAPsAQAwp6TtqeWYosPjp8+QvDBL11db0P11JW31WtK4qVqbWDDiTGXCrakDQDFrMiCj/whjOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918473; c=relaxed/simple; bh=5bN6GDW+jIUWREsZGg3CxhpxdC0DWE0q3FMsuWgUuHk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bTp5/ZHL1yv8uE+Ae8MxhnD62/Nn9DnQ0znTJ3x+JpSEodFkkyTODY0L7HJIs7hRmEloi9DsHJXgDB2hGObqMCSK/wRidtH43GEavNwXLVnrxGnQ8vrb0PymvoLPpXfG9/20IKYwY4rpCmafBlH3bm7mGeDyhhgQcs2T6zSjkbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LcFabWxI; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LcFabWxI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718918472; x=1750454472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5bN6GDW+jIUWREsZGg3CxhpxdC0DWE0q3FMsuWgUuHk=; b=LcFabWxIKWlWUNKcWyZ/pnI3U5B+IQlTfZXoPRA2RJn4Ku4fYbesxdYC aFpSUxMJ9Jk34cJ5ANZytSKXwCUDxgSD5dggenTVBe/vDl/w/KuPPkR9Y c+iPSJdXlK46QUQ6ZeavBY07E/lK9hEwk0Hfcesl7PwDz65s2R/ZQ0mOY es4BdAGrVr+mLpg9r3TQKI1L3t27UbXnLpXRHRhnX26OlGvMgVKmGcWjV vESfHt5T0RpZUg/E/KL9r55Wo6NNXFeZ4WJTBqn3grmV/qz9RNYrID5+P FqpC0zhYpeL/FOZonw1MnnKe01rZxf/eG0OyjIerx8EWSX1eDUHwizhEQ Q==; X-CSE-ConnectionGUID: GEhRBH6TSlODN+U55UiL0Q== X-CSE-MsgGUID: Wkre7xtYRUKCUgK5p7xDyw== X-IronPort-AV: E=McAfee;i="6700,10204,11109"; a="19811214" X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="19811214" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:11 -0700 X-CSE-ConnectionGUID: yl3bNE3NQ6mnKMukQw7fAw== X-CSE-MsgGUID: YinZY4reRmKC25Wi9uxW3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="79883662" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:10 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 1/6] platform/x86/intel/vsec.h: Move to include/linux Date: Thu, 20 Jun 2024 17:20:45 -0400 Message-ID: <20240620212055.3314064-2-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" Some drivers outside of PDX86 need access to the vsec header. Move it to include/linux to make it easier to include. Signed-off-by: David E. Box --- MAINTAINERS | 1 + drivers/platform/x86/intel/pmc/core_ssram.c | 2 +- drivers/platform/x86/intel/pmt/class.c | 2 +- drivers/platform/x86/intel/pmt/class.h | 2 +- drivers/platform/x86/intel/pmt/crashlog.c | 2 +- drivers/platform/x86/intel/pmt/telemetry.c | 2 +- drivers/platform/x86/intel/sdsi.c | 3 +-- drivers/platform/x86/intel/tpmi.c | 3 +-- drivers/platform/x86/intel/vsec.c | 7 +++---- .../x86/intel/vsec.h => include/linux/intel_vsec.h | 11 +++++++++-- 10 files changed, 20 insertions(+), 15 deletions(-) rename drivers/platform/x86/intel/vsec.h => include/linux/intel_vsec.h (92%) diff --git a/MAINTAINERS b/MAINTAINERS index d0738dd0a625..693bb4ac14a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11413,6 +11413,7 @@ INTEL VENDOR SPECIFIC EXTENDED CAPABILITIES DRIVER M: David E. Box S: Supported F: drivers/platform/x86/intel/vsec.* +F: include/linux/intel_vsec.h INTEL VIRTUAL BUTTON DRIVER M: AceLan Kao diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 1bde86c54eb9..baddaaec25ee 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -9,11 +9,11 @@ */ #include +#include #include #include #include "core.h" -#include "../vsec.h" #include "../pmt/telemetry.h" #define SSRAM_HDR_SIZE 0x100 diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 4b53940a64e2..d7939b28e937 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -9,12 +9,12 @@ */ #include +#include #include #include #include #include -#include "../vsec.h" #include "class.h" #define PMT_XA_START 1 diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index d23c63b73ab7..d6f9ccaf28c8 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -2,13 +2,13 @@ #ifndef _INTEL_PMT_CLASS_H #define _INTEL_PMT_CLASS_H +#include #include #include #include #include #include -#include "../vsec.h" #include "telemetry.h" /* PMT access types */ diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x86/intel/pmt/crashlog.c index 4014c02cafdb..9079d5dffc03 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include -#include "../vsec.h" #include "class.h" /* Crashlog discovery header types */ diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 09258564dfc4..3478f891ea0b 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -16,7 +17,6 @@ #include #include -#include "../vsec.h" #include "class.h" #define TELEM_SIZE_OFFSET 0x0 diff --git a/drivers/platform/x86/intel/sdsi.c b/drivers/platform/x86/intel/sdsi.c index 277e4f4b20ac..9d137621f0e6 100644 --- a/drivers/platform/x86/intel/sdsi.c +++ b/drivers/platform/x86/intel/sdsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,8 +23,6 @@ #include #include -#include "vsec.h" - #define ACCESS_TYPE_BARID 2 #define ACCESS_TYPE_LOCAL 3 diff --git a/drivers/platform/x86/intel/tpmi.c b/drivers/platform/x86/intel/tpmi.c index 6c0cbccd80bb..b9fa1cbfdcf7 100644 --- a/drivers/platform/x86/intel/tpmi.c +++ b/drivers/platform/x86/intel/tpmi.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -59,8 +60,6 @@ #include #include -#include "vsec.h" - /** * struct intel_tpmi_pfs_entry - TPMI PM Feature Structure (PFS) entry * @tpmi_id: TPMI feature identifier (what the feature is and its data format). diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 0fdfaf3a4f5c..2b46807f868b 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -17,14 +17,13 @@ #include #include #include -#include #include +#include +#include #include #include #include -#include "vsec.h" - #define PMT_XA_START 0 #define PMT_XA_MAX INT_MAX #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) @@ -341,7 +340,7 @@ static bool intel_vsec_walk_vsec(struct pci_dev *pdev, void intel_vsec_register(struct pci_dev *pdev, struct intel_vsec_platform_info *info) { - if (!pdev || !info) + if (!pdev || !info || !info->headers) return; intel_vsec_walk_header(pdev, info); diff --git a/drivers/platform/x86/intel/vsec.h b/include/linux/intel_vsec.h similarity index 92% rename from drivers/platform/x86/intel/vsec.h rename to include/linux/intel_vsec.h index e23e76129691..ff7998cadab4 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/include/linux/intel_vsec.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _VSEC_H -#define _VSEC_H +#ifndef _INTEL_VSEC_H +#define _INTEL_VSEC_H #include #include @@ -103,6 +103,13 @@ static inline struct intel_vsec_device *auxdev_to_ivdev(struct auxiliary_device return container_of(auxdev, struct intel_vsec_device, auxdev); } +#if IS_ENABLED(CONFIG_INTEL_VSEC) void intel_vsec_register(struct pci_dev *pdev, struct intel_vsec_platform_info *info); +#else +static inline void intel_vsec_register(struct pci_dev *pdev, + struct intel_vsec_platform_info *info) +{ +} +#endif #endif From patchwork Thu Jun 20 21:20:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13706395 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 626D77C09E for ; Thu, 20 Jun 2024 21:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918474; cv=none; b=mgZ5TBNldGtBasMmSWquLnhNMtCj2vn3rHbL9coB45y4NkFFJEhPY0bTwmPXx3F8NRjjFnya2JhwhjsWzjRFeqXdi5dt73kCpghiiLXrw55bOJ97ibx0LAHdpV+lUHGK34dz0ZOUIBnG9ieVPRC68Jzx9CmzX//LYRzqjoLY5Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918474; c=relaxed/simple; bh=R8dbb3VgmZF9CuqsKQAVTfcfpL/OtdrfBMNafCLJTlQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nfIApVUtYuQYLlkjjkeq/FcuqceA5X+Hpbg56MmRVSGW5Mm+92TqQpdstcqbdfIMpW0tPIoLpu28PIfDQ2LAbjzoOi4d+cdd+66xWFlrYse8NYtX5U7Hoge3Gp6lhM1irXy3bsjPStm0sKcR+CnGgesYhWkYL2Jz7gofBCFRZXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jCVzWju1; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jCVzWju1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718918473; x=1750454473; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R8dbb3VgmZF9CuqsKQAVTfcfpL/OtdrfBMNafCLJTlQ=; b=jCVzWju105aB1jut8vKla03YbjoKLq8c9BU2VVn2UHQsQZqHE27m97uH RxUuqx6Ge2URtikepueh0nNCBC/eo7xAPCpaDITXfXxFx/QeotwGE1hez g9WC7Li3bdi5ifPXP9hbok618dgwZPSrHh4aJKx02vo4tMU7goGvzSKsL 6gGdi+kTobI3O6gXwMn+6zPdr40nQt7MOfEi1/nxbisExSW1JyvYW/CfZ 0+zklT4DGU0E21s+trPpx9dBSoBUyhj76max+xD/L1S0gtlRMHzsK94Aw 9q8TOMBpXv4gL6sH/rbocuGQJcsrnfIZ/bS3HMOuKfxH0PDSjjiXqmGWK g==; X-CSE-ConnectionGUID: vS/vKO/aRgWEIMIlcD8JoQ== X-CSE-MsgGUID: 4bcNTi90TP2XiwuOAAFu2A== X-IronPort-AV: E=McAfee;i="6700,10204,11109"; a="19811219" X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="19811219" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:13 -0700 X-CSE-ConnectionGUID: O+/3UEV/SGGXe8PSeYfgZQ== X-CSE-MsgGUID: omxrtjujROGy8RpYc062Tw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="79883669" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:12 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 2/6] platform/x86/intel/vsec: Add PMT read callbacks Date: Thu, 20 Jun 2024 17:20:46 -0400 Message-ID: <20240620212055.3314064-3-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" Some PMT providers require device specific actions before their telemetry can be read. Provide assignable PMT read callbacks to allow providers to perform those actions. Signed-off-by: David E. Box --- drivers/platform/x86/intel/vsec.c | 1 + include/linux/intel_vsec.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 2b46807f868b..7b5cc9993974 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -212,6 +212,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; intel_vsec_dev->base_addr = info->base_addr; + intel_vsec_dev->priv_data = info->priv_data; if (header->id == VSEC_ID_SDSI) intel_vsec_dev->ida = &intel_vsec_sdsi_ida; diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index ff7998cadab4..003301783331 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -67,10 +67,15 @@ enum intel_vsec_quirks { VSEC_QUIRK_EARLY_HW = BIT(4), }; +struct pmt_callbacks { + int (*read_telem)(void *args, u32 guid, u64 *data, u32 count); +}; + /* Platform specific data */ struct intel_vsec_platform_info { struct device *parent; struct intel_vsec_header **headers; + void *priv_data; unsigned long caps; unsigned long quirks; u64 base_addr; From patchwork Thu Jun 20 21:20:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. 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Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 3/6] platform/x86/intel/pmt: Use PMT callbacks Date: Thu, 20 Jun 2024 17:20:47 -0400 Message-ID: <20240620212055.3314064-4-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "David E. Box" PMT providers may require device specific actions before their telemetry may be read. If the read_telem() is assigned, call it instead of memcpy_fromio() and return. Since this needs to be done in multiple locations, add pmt_telem_read_mmio() as a wrapper function to perform this and any other needed checks. Signed-off-by: David E. Box --- drivers/platform/x86/intel/pmt/class.c | 26 +++++++++++++++++----- drivers/platform/x86/intel/pmt/class.h | 8 +++++-- drivers/platform/x86/intel/pmt/telemetry.c | 10 +++++---- 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index d7939b28e937..c04bb7f97a4d 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -58,6 +58,22 @@ pmt_memcpy64_fromio(void *to, const u64 __iomem *from, size_t count) return count; } +int pmt_telem_read_mmio(struct pci_dev *pdev, struct pmt_callbacks *cb, u32 guid, void *buf, + void __iomem *addr, u32 count) +{ + if (cb && cb->read_telem) + return cb->read_telem(pdev, guid, buf, count); + + if (guid == GUID_SPR_PUNIT) + /* PUNIT on SPR only supports aligned 64-bit read */ + return pmt_memcpy64_fromio(buf, addr, count); + + memcpy_fromio(buf, addr, count); + + return count; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_read_mmio, INTEL_PMT); + /* * sysfs */ @@ -79,11 +95,8 @@ intel_pmt_read(struct file *filp, struct kobject *kobj, if (count > entry->size - off) count = entry->size - off; - if (entry->guid == GUID_SPR_PUNIT) - /* PUNIT on SPR only supports aligned 64-bit read */ - count = pmt_memcpy64_fromio(buf, entry->base + off, count); - else - memcpy_fromio(buf, entry->base + off, count); + count = pmt_telem_read_mmio(entry->ep->pcidev, entry->cb, entry->header.guid, buf, + entry->base + off, count); return count; } @@ -239,6 +252,7 @@ static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, entry->guid = header->guid; entry->size = header->size; + entry->cb = ivdev->priv_data; return 0; } @@ -300,7 +314,7 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry, goto fail_ioremap; if (ns->pmt_add_endpoint) { - ret = ns->pmt_add_endpoint(entry, ivdev->pcidev); + ret = ns->pmt_add_endpoint(ivdev, entry); if (ret) goto fail_add_endpoint; } diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index d6f9ccaf28c8..a267ac964423 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -24,6 +24,7 @@ struct pci_dev; struct telem_endpoint { struct pci_dev *pcidev; struct telem_header header; + struct pmt_callbacks *cb; void __iomem *base; bool present; struct kref kref; @@ -43,6 +44,7 @@ struct intel_pmt_entry { struct kobject *kobj; void __iomem *disc_table; void __iomem *base; + struct pmt_callbacks *cb; unsigned long base_addr; size_t size; u32 guid; @@ -55,10 +57,12 @@ struct intel_pmt_namespace { const struct attribute_group *attr_grp; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); - int (*pmt_add_endpoint)(struct intel_pmt_entry *entry, - struct pci_dev *pdev); + int (*pmt_add_endpoint)(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry); }; +int pmt_telem_read_mmio(struct pci_dev *pdev, struct pmt_callbacks *cb, u32 guid, void *buf, + void __iomem *addr, u32 count); bool intel_pmt_is_early_client_hw(struct device *dev); int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespace *ns, diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 3478f891ea0b..c9feac859e57 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -93,8 +93,8 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, return 0; } -static int pmt_telem_add_endpoint(struct intel_pmt_entry *entry, - struct pci_dev *pdev) +static int pmt_telem_add_endpoint(struct intel_vsec_device *ivdev, + struct intel_pmt_entry *entry) { struct telem_endpoint *ep; @@ -104,13 +104,14 @@ static int pmt_telem_add_endpoint(struct intel_pmt_entry *entry, return -ENOMEM; ep = entry->ep; - ep->pcidev = pdev; + ep->pcidev = ivdev->pcidev; ep->header.access_type = entry->header.access_type; ep->header.guid = entry->header.guid; ep->header.base_offset = entry->header.base_offset; ep->header.size = entry->header.size; ep->base = entry->base; ep->present = true; + ep->cb = ivdev->priv_data; kref_init(&ep->kref); @@ -218,7 +219,8 @@ int pmt_telem_read(struct telem_endpoint *ep, u32 id, u64 *data, u32 count) if (offset + NUM_BYTES_QWORD(count) > size) return -EINVAL; - memcpy_fromio(data, ep->base + offset, NUM_BYTES_QWORD(count)); + pmt_telem_read_mmio(ep->pcidev, ep->cb, ep->header.guid, data, ep->base + offset, + NUM_BYTES_QWORD(count)); return ep->present ? 0 : -EPIPE; } From patchwork Thu Jun 20 21:20:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Michael J. 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Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 4/6] drm/xe/vsec: Support BMG devices Date: Thu, 20 Jun 2024 17:20:48 -0400 Message-ID: <20240620212055.3314064-5-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Utilize the PMT callback API to add support for the BMG devices. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 5 + drivers/gpu/drm/xe/xe_device_types.h | 5 + drivers/gpu/drm/xe/xe_vsec.c | 214 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_vsec.h | 13 ++ 5 files changed, 238 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_vsec.c create mode 100644 drivers/gpu/drm/xe/xe_vsec.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 20dc9759bb3c..ee99a0a3f42f 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -126,6 +126,7 @@ xe-y += xe_bb.o \ xe_vm.o \ xe_vram.o \ xe_vram_freq.o \ + xe_vsec.o \ xe_wait_user_fence.o \ xe_wa.o \ xe_wopcm.o diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 0d57eea8f083..3660058a80f3 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -53,6 +53,7 @@ #include "xe_ttm_sys_mgr.h" #include "xe_vm.h" #include "xe_vram.h" +#include "xe_vsec.h" #include "xe_wait_user_fence.h" static int xe_file_open(struct drm_device *dev, struct drm_file *file) @@ -317,6 +318,8 @@ struct xe_device *xe_device_create(struct pci_dev *pdev, goto err; } + drmm_mutex_init(&xe->drm, &xe->pmt.lock); + err = xe_display_create(xe); if (WARN_ON(err)) goto err; @@ -689,6 +692,8 @@ int xe_device_probe(struct xe_device *xe) xe_hwmon_register(xe); + xe_vsec_init(xe); + return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); err_fini_display: diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index c37be471d11c..469e11fc0633 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -451,6 +451,11 @@ struct xe_device { struct mutex lock; } d3cold; + struct { + /** @pmt.lock: protect access for telemetry data */ + struct mutex lock; + } pmt; + /** * @pm_callback_task: Track the active task that is running in either * the runtime_suspend or runtime_resume callbacks. diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c new file mode 100644 index 000000000000..a8afef731379 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2022 - 2024 Intel Corporation + */ +#include +#include + +#include "xe_device.h" +#include "xe_device_types.h" +#include "xe_drv.h" +#include "xe_mmio.h" +#include "xe_platform_types.h" +#include "xe_pm.h" +#include "xe_vsec.h" + +#define SOC_BASE 0x280000 + +#define BMG_PMT_BASE 0xDB000 +#define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE) + +#define BMG_TELEMETRY_BASE 0xE0000 +#define BMG_TELEMETRY_OFFSET (SOC_BASE + BMG_TELEMETRY_BASE) + +#define GFX_BAR 0 + +#define SG_REMAP_INDEX1 XE_REG(SOC_BASE + 0x08) +#define SG_REMAP_ACCESS(_mem) ((_mem) << 24) +#define SG_REMAP_BITS GENMASK(31, 24) + +static struct intel_vsec_header bmg_telemetry = { + .length = 0x10, + .id = VSEC_ID_TELEMETRY, + .num_entries = 2, + .entry_size = 4, + .tbir = GFX_BAR, + .offset = BMG_DISCOVERY_OFFSET, +}; + +static struct intel_vsec_header *bmg_capabilities[] = { + &bmg_telemetry, + NULL +}; + +enum xe_vsec { + XE_VSEC_UNKNOWN = 0, + XE_VSEC_BMG, +}; + +static struct intel_vsec_platform_info xe_vsec_info[] = { + [XE_VSEC_BMG] = { + .caps = VSEC_CAP_TELEMETRY, + .headers = bmg_capabilities, + }, + { } +}; + +/* GUID Decode information */ +#define GUID_TELEM_ITERATION GENMASK(3, 0) +#define GUID_SEGMENT GENMASK(7, 4) +#define GUID_SOC_SKU GENMASK(11, 8) +#define GUID_DEVICE_ID GENMASK(27, 12) +#define GUID_CAP_TYPE GENMASK(29, 28) +#define GUID_RECORD_ID GENMASK(31, 30) + +enum record_id { + PUNIT, + OOBMSM_0, + OOBMSM_1 +}; + +enum capability { + CRASHLOG, + TELEMETRY, + WATCHER +}; + +/* + * The GUID will have the following bits to decode (high bits first): + * + * X(2bits) - Record-ID (0-PUNIT, 1-OOBMSM_0, 2-OOBMSM_1) + * X(2bits) - Capability Type (Crashlog-0, Telemetry Aggregator-1, Watcher-2) + * XXXX(16bits)– Device ID – changes for each down bin SKU’s (0xE2F8 for BMG) + * X(4bits) - SOC_SKU (SKU_INDEPENDENT-0, X3-1, X2-2, G31-3), + * X(4bits) - Segment (SEGMENT_INDEPENDENT-0, Client-1, Server-2) + * X(4bits) - {Telemetry space iteration number (0,1,..)} + * + */ +static int guid_decode(u32 guid, int *index, u32 *offset) +{ + u32 record_id = (guid & GUID_RECORD_ID) >> 30; + u32 cap_type = (guid & GUID_CAP_TYPE) >> 28; + u32 device_id = (guid & GUID_DEVICE_ID) >> 12; + + if (device_id != 0xE2F8) + return -ENODEV; + + if (record_id > OOBMSM_1 || cap_type > WATCHER) + return -EINVAL; + + *offset = 0; + + if (cap_type == CRASHLOG) { + *index = record_id == PUNIT ? 2 : 4; + return 0; + } + + switch (record_id) { + case PUNIT: + *index = 0; + if (cap_type == TELEMETRY) + *offset = 0x0200; + else /* if (cap_type == WATCHER) */ + *offset = 0x14A0; + break; + + case OOBMSM_0: + *index = 1; + if (cap_type == WATCHER) + *offset = 0x18D8; + break; + + case OOBMSM_1: + *index = 1; + if (cap_type == TELEMETRY) + *offset = 0x1000; + break; + } + + return 0; +} + +static int xe_pmt_telem_read(void *args, u32 guid, u64 *data, u32 count) +{ + struct xe_device *xe = pdev_to_xe_device((struct pci_dev *)args); + void __iomem *telem_addr = xe->tiles[0].mmio.regs + BMG_TELEMETRY_OFFSET; + u32 mem_region; + u32 offset; + int ret; + + ret = guid_decode(guid, &mem_region, &offset); + if (ret) + return ret; + + telem_addr += offset; + + mutex_lock(&xe->pmt.lock); + + /* indicate that we are not at an appropriate power level */ + ret = -ENODATA; + if (xe_pm_runtime_get_if_active(xe) > 0) { + /* set SoC re-mapper index register based on guid memory region */ + xe_mmio_rmw32(xe->tiles[0].primary_gt, SG_REMAP_INDEX1, SG_REMAP_BITS, + SG_REMAP_ACCESS(mem_region)); + + memcpy_fromio(data, telem_addr, count); + ret = count; + xe_pm_runtime_put(xe); + } + mutex_unlock(&xe->pmt.lock); + + return ret; +} + +struct pmt_callbacks xe_pmt_cb = { + .read_telem = xe_pmt_telem_read, +}; + +static const int vsec_platforms[] = { + [XE_BATTLEMAGE] = XE_VSEC_BMG, +}; + +static enum xe_vsec get_platform_info(struct xe_device *xe) +{ + if (xe->info.platform > XE_BATTLEMAGE) + return XE_VSEC_UNKNOWN; + + return vsec_platforms[xe->info.platform]; +} + +/** + * intel_vsec_init - Initialize resources and add intel_vsec auxiliary + * interface + * @xe: valid xe instance + */ +void xe_vsec_init(struct xe_device *xe) +{ + struct intel_vsec_platform_info *info; + struct device *dev = xe->drm.dev; + struct pci_dev *pdev = to_pci_dev(dev); + enum xe_vsec platform; + + platform = get_platform_info(xe); + if (platform == XE_VSEC_UNKNOWN) + return; + + info = &xe_vsec_info[platform]; + if (!info->headers) + return; + + switch (platform) { + case XE_VSEC_BMG: + info->priv_data = &xe_pmt_cb; + break; + default: + break; + } + + /* + * Register a VSEC. Cleanup is handled using device managed + * resources. + */ + intel_vsec_register(pdev, info); +} +MODULE_IMPORT_NS(INTEL_VSEC); diff --git a/drivers/gpu/drm/xe/xe_vsec.h b/drivers/gpu/drm/xe/xe_vsec.h new file mode 100644 index 000000000000..3fd29a21cad6 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_vsec.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright © 2022 - 2024 Intel Corporation + */ + +#ifndef _XE_VSEC_H_ +#define _XE_VSEC_H_ + +struct xe_device; + +void xe_vsec_init(struct xe_device *xe); + +#endif From patchwork Thu Jun 20 21:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13706398 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 516017640D for ; Thu, 20 Jun 2024 21:21:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918479; cv=none; b=tzkV6OMAgQaQRaTT/nMLIiCgncyX4sbBivrFbDJ1GLLL5UsrUmsDL2pgrgsBGhkXGLTAdB6Rlr6zHCh1BPDHFzWXzuIS5NfJgaVUs4CeAakXf4xWdacarHLfJSPePCoDy3DC5PlXyoysEGNvQN4mvQxxz6aPyPzT15qVPdvHtLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718918479; c=relaxed/simple; bh=o7pgEsl1M4jkRAL2OMPP8br1xBPkYV2QP+YAJ1OanhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OUGaOI+iFQSLJ/pocymRehsH/Ebb1VFoMTKyOynoMu5zDTsNg1msgEK5F07YjZUV/b7O5aKLQCF0gXA3Y+ckwZn1+XQUiz1QtD34mARxxTsamGW4slqKBIZwffPb2JAAjEDs5C2TgRYUrvGPfoxSFs7LydL+07C19oFkzcuQd5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GnYHGJYb; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GnYHGJYb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718918478; x=1750454478; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o7pgEsl1M4jkRAL2OMPP8br1xBPkYV2QP+YAJ1OanhY=; b=GnYHGJYbHMkxKr2bRbbmu+pSctrcXVEpaBa8s9B7obGcVmg7m7S7OfZX HYbLFiPt7JLqXBrN/y5pEsvZnRvQA1qWLh3Vw2hCndavtfR1LGFQ49dhF SQdy+B+x3ZniZBJP1FhoEW4rFeikRndwzP9ClJM2IUDEs9akT72nHFLOg Z3vLhmtECgM581p/VWC57Ddfk8/RkiL+UkzB9hhCB8wUh4HeOfswr+Pqx tt853hOPewfvqRNzwtyZTkOv58r+7FfgLAo/cYUaYiZv473pRngMdpZu/ ZP64FpTKRGmRcu3jgRogVQwiifHGcWJNkjdHDrtvEyDsxhEgBqwC1gRZJ w==; X-CSE-ConnectionGUID: 25NnxNFKTs6q85rzxBrZag== X-CSE-MsgGUID: kdTH6dmDQfmFMG+DMeKSRQ== X-IronPort-AV: E=McAfee;i="6700,10204,11109"; a="19811229" X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="19811229" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:18 -0700 X-CSE-ConnectionGUID: rp1PzKjTSxu/zUzNxhyItQ== X-CSE-MsgGUID: k9EnhowQSGG2v/xTrGfXKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,252,1712646000"; d="scan'208";a="79883691" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2024 14:21:17 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 5/6] platform/x86/intel/pmt: Add support for PMT base adjust Date: Thu, 20 Jun 2024 17:20:49 -0400 Message-ID: <20240620212055.3314064-6-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 DVSEC offsets are based on the endpoint BAR. If an endpoint is not avialable allow the offset information to be adjusted by the parent driver. Signed-off-by: Michael J. Ruhl --- drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 9 +++++++++ drivers/platform/x86/intel/vsec.c | 1 + include/linux/intel_vsec.h | 2 ++ 4 files changed, 13 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index a267ac964423..984cd40ee814 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -46,6 +46,7 @@ struct intel_pmt_entry { void __iomem *base; struct pmt_callbacks *cb; unsigned long base_addr; + s32 base_adjust; size_t size; u32 guid; int devid; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index c9feac859e57..5c44e500e8f6 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -78,6 +78,13 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, header->access_type = TELEM_ACCESS(readl(disc_table)); header->guid = readl(disc_table + TELEM_GUID_OFFSET); header->base_offset = readl(disc_table + TELEM_BASE_OFFSET); + if (entry->base_adjust) { + u32 new_base = header->base_offset + entry->base_adjust; + + dev_dbg(dev, "Adjusting baseoffset from 0x%x to 0x%x\n", + header->base_offset, new_base); + header->base_offset = new_base; + } /* Size is measured in DWORDS, but accessor returns bytes */ header->size = TELEM_SIZE(readl(disc_table)); @@ -302,6 +309,8 @@ static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxilia for (i = 0; i < intel_vsec_dev->num_resources; i++) { struct intel_pmt_entry *entry = &priv->entry[priv->num_entries]; + entry->base_adjust = intel_vsec_dev->base_adjust; + mutex_lock(&ep_lock); ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i); mutex_unlock(&ep_lock); diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 7b5cc9993974..be079d62a7bc 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -212,6 +212,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; intel_vsec_dev->base_addr = info->base_addr; + intel_vsec_dev->base_adjust = info->base_adjust; intel_vsec_dev->priv_data = info->priv_data; if (header->id == VSEC_ID_SDSI) diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 003301783331..930eab246fa1 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -79,6 +79,7 @@ struct intel_vsec_platform_info { unsigned long caps; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; struct intel_vsec_device { @@ -92,6 +93,7 @@ struct intel_vsec_device { size_t priv_data_size; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, From patchwork Thu Jun 20 21:20:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. 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Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, pavel.e.popov@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v2 6/6] drm/xe/vsec: Add support for DG2 Date: Thu, 20 Jun 2024 17:20:50 -0400 Message-ID: <20240620212055.3314064-7-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240620212055.3314064-1-michael.j.ruhl@intel.com> References: <20240620212055.3314064-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 DG2 needs to adjust the discovery offset WRT the GT BAR not the P2SB bar so add the base_adjust value to allow for the difference to be used. Update xe_vsec.c to include DG2 header information. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/xe_vsec.c | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index a8afef731379..a0a154657816 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -15,6 +15,16 @@ #define SOC_BASE 0x280000 +/* from drivers/platform/x86/intel/pmt/telemetry.c */ +#define TELEM_BASE_OFFSET 0x8 + +#define DG2_PMT_BASE 0xE8000 +#define DG2_DISCOVERY_START 0x6000 +#define DG2_TELEM_START 0x4000 + +#define DG2_DISCOVERY_OFFSET (SOC_BASE + DG2_PMT_BASE + DG2_DISCOVERY_START) +#define DG2_TELEM_OFFSET (SOC_BASE + DG2_PMT_BASE + DG2_TELEM_START) + #define BMG_PMT_BASE 0xDB000 #define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE) @@ -27,6 +37,20 @@ #define SG_REMAP_ACCESS(_mem) ((_mem) << 24) #define SG_REMAP_BITS GENMASK(31, 24) +static struct intel_vsec_header dg2_telemetry = { + .length = 0x10, + .id = VSEC_ID_TELEMETRY, + .num_entries = 1, + .entry_size = 3, + .tbir = GFX_BAR, + .offset = DG2_DISCOVERY_OFFSET, +}; + +static struct intel_vsec_header *dg2_capabilities[] = { + &dg2_telemetry, + NULL +}; + static struct intel_vsec_header bmg_telemetry = { .length = 0x10, .id = VSEC_ID_TELEMETRY, @@ -43,10 +67,16 @@ static struct intel_vsec_header *bmg_capabilities[] = { enum xe_vsec { XE_VSEC_UNKNOWN = 0, + XE_VSEC_DG2, XE_VSEC_BMG, }; static struct intel_vsec_platform_info xe_vsec_info[] = { + [XE_VSEC_DG2] = { + .caps = VSEC_CAP_TELEMETRY, + .headers = dg2_capabilities, + .quirks = VSEC_QUIRK_EARLY_HW, + }, [XE_VSEC_BMG] = { .caps = VSEC_CAP_TELEMETRY, .headers = bmg_capabilities, @@ -166,6 +196,7 @@ struct pmt_callbacks xe_pmt_cb = { }; static const int vsec_platforms[] = { + [XE_DG2] = XE_VSEC_DG2, [XE_BATTLEMAGE] = XE_VSEC_BMG, }; @@ -177,6 +208,49 @@ static enum xe_vsec get_platform_info(struct xe_device *xe) return vsec_platforms[xe->info.platform]; } +/* + * Access the DG2 PMT MMIO discovery table + * + * The intel_vsec driver does not typically access the discovery table. + * Instead, it creates a memory resource for the table and passes it + * to the PMT telemetry driver. Each discovery table contains 3 items, + * - GUID + * - Telemetry size + * - Telemetry offset (offset from P2SB BAR, not GT) + * + * For DG2 we know what the telemetry offset is, but we still need to + * use the discovery table to pass the GUID and the size. So figure + * out the difference between the P2SB offset and the GT offset and + * save this so that the telemetry driver can use it to adjust the + * value. + */ +static int dg2_adjust_offset(struct pci_dev *pdev, struct device *dev, + struct intel_vsec_platform_info *info) +{ + void __iomem *base; + u32 telem_offset; + u64 addr; + + /* compile check to verify that quirk has P2SB quirk added */ + + addr = pci_resource_start(pdev, GFX_BAR) + info->headers[0]->offset; + base = ioremap_wc(addr, 16); + if (!base) + return -ENOMEM; + + telem_offset = readl(base + TELEM_BASE_OFFSET); + + /* Use the base_addr + P2SB quirk to pass this info */ + if (telem_offset < DG2_TELEM_OFFSET) + info->base_adjust = -(DG2_TELEM_OFFSET - telem_offset); + else + info->base_adjust = -(telem_offset - DG2_TELEM_OFFSET); + + iounmap(base); + + return 0; +} + /** * intel_vsec_init - Initialize resources and add intel_vsec auxiliary * interface @@ -188,6 +262,7 @@ void xe_vsec_init(struct xe_device *xe) struct device *dev = xe->drm.dev; struct pci_dev *pdev = to_pci_dev(dev); enum xe_vsec platform; + u32 ret; platform = get_platform_info(xe); if (platform == XE_VSEC_UNKNOWN) @@ -198,6 +273,12 @@ void xe_vsec_init(struct xe_device *xe) return; switch (platform) { + case XE_VSEC_DG2: + ret = dg2_adjust_offset(pdev, dev, info); + if (ret) + return; + break; + case XE_VSEC_BMG: info->priv_data = &xe_pmt_cb; break;