From patchwork Fri Jun 21 09:40:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 13707163 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B033216E899; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; cv=none; b=RMZ/BMu6E2M4/INuDImUkpQxMTlE2Z0kLjnbwG0FqkbqnrFURwP6ef926XNUJ5hK7LolIjZkM1ki0e/FSROJtZ7kRLk6xTJiuCjQBKaGaNDUD2RR8Q8MMAItHBkhZiRPnN0xJr8yHtFi8AaWRuiKg57VlH7woifgbRmeStRZwqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; c=relaxed/simple; bh=OCxZlsLe/HD5Hbojf8KNOo9PgGbwSKUapEE/5kfRbKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ING1aPqFsdi+nyi4Ih/hvtyMYzt0oW9makY+0UW/IFl79rc1HUPJX+97B7TXBnXGw1F/I4UbNcr6wDcbDuavBTfwUcgthQvnDJpAW0y8JQYJ0h5v/5vCF5Hj+OCJQyx0PHcwSRNgjXbnS5o4haHTSNG5ZoPH54r6DyATcU9lE7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ad5a1sdd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ad5a1sdd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4BA35C4AF08; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962857; bh=OCxZlsLe/HD5Hbojf8KNOo9PgGbwSKUapEE/5kfRbKg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ad5a1sddhFIOWyyE7+U63ggbQWGI3IJY5+PHKG86LVark40Vr0IzxxgFWHvd9Qi/L dhFgqswYCBmH+yRfWhS9NPhhgK1/1SCiUd4wIjsxx4nP7bQTEMjG98eTyutAx1XPIc DgdU+k0DyMGEPyQB18wrq6erMGSqz+PQxuwqUJHBgqKeph2Mwb/pLu77QV0EDRcYCs 5gjvSI+N44Kild8sk/fcyGk60FAeXdlDTfxOFiESd8ygy1eHQGm0SfL68uRfrtSv41 E4iibOtnDVjL3jr/+eU05fHlN8iHJ0SuwmbZBZGKUBcsvsmlx6v5Vz/rUQ21lAoMuF jw3y/Uu5oQjAA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A04BC27C4F; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:53 +0800 Subject: [PATCH 1/6] media: dt-bindings: media: camss: Add qcom,sc7180-camss binding Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-1-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=9270; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=6Xx6yEhiC/IT72bgVtKLKKWZZ411ZEpiryAUl4p+XfU=; b=RBGcUP3sqE4hr+e4Z4Op3aR+LIO28zfEmCCJI/9mdcKah2a1bD7M1Oau+KNRRB/bsw3tyud+J nuS6gdUgoPKDRfXJ8WdoW6wRf7p4/mK3CGverBwYz3oz07207MumEEa X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Add bindings for qcom,sc7180-camss in order to support the camera subsystem for sm7125 as found in the Xiaomi Redmi 9 Pro cellphone. Signed-off-by: George Chan --- .../bindings/media/qcom,sc7180-camss.yaml | 324 +++++++++++++++++++++ 1 file changed, 324 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml new file mode 100644 index 000000000000..4dc10c32ee9c --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-camss.yaml @@ -0,0 +1,324 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc7180-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CAMSS ISP + +maintainers: + - Robert Foss + +description: | + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms + +properties: + compatible: + const: qcom,sc7180-camss + + clocks: + minItems: 25 + maxItems: 25 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cphy_rx_src + - const: csi0 + - const: csi1 + - const: csi2 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe_lite + - const: vfe_lite_cphy_rx + + interrupts: + minItems: 10 + maxItems: 10 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + iommus: + maxItems: 4 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + reg: + minItems: 10 + maxItems: 10 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interrupt-names + - interrupts + - iommus + - power-domains + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@acb3000 { + compatible = "qcom,sc7180-camss"; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + iommus = <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0x0>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + reg = <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; From patchwork Fri Jun 21 09:40:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 13707162 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B02E516E895; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; cv=none; b=B5wCR5q299LVUI8f9eJ/WQKC6LDilZSqDWwMaYlnZcSP03SJ9VtdoSEEfVLYy7tqW8xPEIxEhjg6pYsdeAQ9MLNdARW70kT8DbahT0L4gyicZ/lI1ut4/iLBeiRQ2DosbuMHnRAzL8Vr5OQodRWchPL82i/dl/bsE6+HNjmesls= ARC-Message-Signature: i=1; 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b=OURpnU+BY7jGENRYk9G9VAtNa3DCBojmpdnHndLL8VTFFDcDnayAxGjWsJXjQdBUG kEGhosAn1YDVrYpOdIFaWyUoCmTghwz0nXdy6Pu+tdvF1xRLhfnwDHyLNAojGa6rGj +CUWRPohLW9ObpzsBxuuQFVvaOpZ3KfJBAZwhnFuZW36wM1fek9msvN5EUReTS4q8B di7GBlVmvAKkWxYoXgCjjx8O54SHOHVXzSdkNWUIj2cAyArEVPLPOh1tGyOSroeD+n ZpYuQXhi8erluWaSG29AABQGzgQeyicp4no8aUk+Bfwqv6td1IDjmj3OPw3Ll69JJq ongJC3+s0bGgg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47724C2BD09; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:54 +0800 Subject: [PATCH 2/6] media: qcom: camss: Add CAMSS_SC7180 enum Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-2-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=576; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=4HwDgWtpMPEf780qBHcmuZUqzxXmWxCc6Ssp+LbI1Eo=; b=2Az5/ygCx4Ah/VzvEkKKKynF9jSOszic0691gERNKF8pSdCSYet1UgQ3PnkPqCniahi0mSfQv tTiW1FnMmlTA9A+BZGxZxNaHEDo/slKq5k4YNzcqOdUUCjz7a+UeOdH X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Adds a CAMSS SoC identifier for the SC7180. Signed-off-by: George Chan --- drivers/media/platform/qcom/camss/camss.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index ac15fe23a702..5e750c481b74 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -76,6 +76,7 @@ enum camss_version { CAMSS_8x96, CAMSS_660, CAMSS_845, + CAMSS_7180, CAMSS_8250, CAMSS_8280XP, }; From patchwork Fri Jun 21 09:40:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 13707161 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8624916E887; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; cv=none; b=tN3KdwJTxRgkn+S+uwJrbTUQrvyeNAgPdGIlBZah4rBOlAtys3MJEgR4ZTFDh5/iAgxOLKyl5LwV3RlnpDQDVFa002Lhm2dxN3c58GEmcCalJ4/aBMFk0rPiRKfntvl5VB0rlxk8hrYuWWjhav4YSz5EICTi02bp8qXiCzquciE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; c=relaxed/simple; bh=e+Bb+4Od2zDc+ezSDWksqaLGWJoSEqxlyUKc7wxHSXY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fJNlsVROyAEIkE5AGnkYSszOY07jrLi33WAZKpes3V2QZULSu5a/o2U9W32/6UNCf/vOevNW9Rg1HHtul76l9TqGOZOmnnn3rEp0HkryFkMDOeyyrF88hUuzxRYdxEj+UhvVWaqUSbomXeA3PoMu5V9k3VV14tpg98RUWveuCo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u2SRziR7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u2SRziR7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 631BEC4AF10; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962857; bh=e+Bb+4Od2zDc+ezSDWksqaLGWJoSEqxlyUKc7wxHSXY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=u2SRziR7FkqGq32WYdmkllbYutZrJWW17oARGGt1pQ25WcfeUColD49HOucTiGgU4 1f8ttkb1W4v0RcN4Yh29SwphSE4+RqM8rrawPNgQl7XXyqMDeXaHDNG7rItXdZ/nPN 9HKtEyJvZUvjqo7w5XrmCbZjKAQnFcdV2yFMcW4MyjodSw8GNXv05Xe58SPh6imDw3 +egIYHi8nxIZag+2qC39t7p0zGL94j8YpGtJ+cgdK0w9peLLLfR2WWnapNCY3xI93d CIjzTL2YRetZFo4L5cGnuT7PXTzV6r3Xd2qWboOVCnPBDxql9++5hlIl6XhNraDy4C uBny6YthMin6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D2DC2BBCA; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:55 +0800 Subject: [PATCH 3/6] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.2 two-phase MIPI CSI-2 DPHY init Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-3-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=6507; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=tNAk5rB+15UkLcsHaLJ+IrCh49KG/BffLl2z2QL1gu8=; b=NSJXmONVjOU/W3/fRkGxpWo81kLinuerJ5BKGo5DmDUD59Q0l1pgx5SSre4KqMJbLR5bCielJ /SVUvTNqhKiBMADqRB1h28J22FMny8V8Jk8DlXoT/DWbURHDy/Il8NO X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Add a PHY configuration sequence for the sc7180 which uses a Qualcomm Gen 2 version 1.2.2 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports two-phase D-PHY mode. Signed-off-by: George Chan --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 120 +++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index df7e93a5a4f6..181bb7f7c300 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -348,6 +348,121 @@ csiphy_reg_t lane_regs_sm8250[5][20] = { }, }; +/* GEN2 1.2.2 2PH */ +struct +csiphy_reg_t lane_regs_sc7180[5][20] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + static void csiphy_hw_version_read(struct csiphy_device *csiphy, struct device *dev) { @@ -509,6 +624,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, r = &lane_regs_sdm845[0][0]; array_size = ARRAY_SIZE(lane_regs_sdm845[0]); break; + case CAMSS_7180: + r = &lane_regs_sc7180[0][0]; + array_size = ARRAY_SIZE(lane_regs_sc7180[0]); + break; case CAMSS_8250: r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); @@ -558,6 +677,7 @@ static bool csiphy_is_gen2(u32 version) switch (version) { case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: ret = true; From patchwork Fri Jun 21 09:40:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 13707164 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD90416EB6F; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; cv=none; b=mmuxzhHWbXwekgkbbdu6fChjgcJW1bJH5+2sfCAwqXg12u+8TY5mneq2Kd6p+8/mt6SlPEX+KtUU4x8T05Mxf3c1cGAPDdywMQ21c2av4tK0Gfk8JOcKAJcP56BMJG+1eW1cRZkH2IjRCLtIOJNq3wwoPb0mSbeMUWqlmwobd5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718962857; c=relaxed/simple; bh=y0RoOWqrDNtRx3/l9S/QfF0yJ9pb9mKrBdIdyjxlfG4=; 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zSiB5aEp1GjH1SEifwzO4AtREq+2fJIJR5pMLLp9++AloSnOUpT7oiiakNmkN3byQL Xamwx6wuaFQFWTUW3mR8uzL9vMBTibF/OnMnKiqqBy+q7BtoaBoWi0eprlN3kDvVUd /h5P0tOyTVcsFPhMvy3NXnKZhbWfXlLZlsZpMncPejrRJ9GC10b8eQxoTa5PzMwALp cjzqoo86trOmAoHjWIcXIAaRC4ldYK/RbkJnDSIQf2Yfzxc94E7OJTe+jkJzUusUcW /27HDj48UAdpA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61AA8C2BA1A; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:56 +0800 Subject: [PATCH 4/6] media: qcom: camss: Add sc7180 support Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-4-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=2308; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=YnPxfplUpyI7adL5KPtpIXi5NQhvsVScDtSlkhPHhXI=; b=6N0QHkttcoYSS5SQ1fZKQ/9yXpFF+i4jfnyxFZ/YNyQ7zNoXbFOCVAxMHQm5FCGJtRgJI6iC/ LYsmZIaJH8pBbe6sVnNlv7yrOh1pHN56UuFSW8GTBg9UZ33wu+ZamU6 X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Add in functional logic throughout the code to support the sc7180. Signed-off-by: George Chan --- drivers/media/platform/qcom/camss/camss-csiphy.c | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 3 +++ drivers/media/platform/qcom/camss/camss-video.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 45b3a8e5dea4..1fb08b5ee01b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -577,6 +577,7 @@ int msm_csiphy_subdev_init(struct camss *camss, csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); break; case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: csiphy->formats = csiphy_formats_sdm845; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index d875237cf244..05fa1adc1661 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -224,6 +224,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_8x96: case CAMSS_660: case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: switch (sink_code) { @@ -1518,6 +1519,7 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, } break; case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: l->formats = formats_rdi_845; @@ -1603,6 +1605,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) switch (vfe->camss->res->version) { case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: ret = 16; diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index 54cd82f74115..5b7f3fba938c 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -1027,6 +1027,7 @@ int msm_video_register(struct camss_video *video, struct v4l2_device *v4l2_dev, } break; case CAMSS_845: + case CAMSS_7180: case CAMSS_8250: case CAMSS_8280XP: video->formats = formats_rdi_845; From patchwork Fri Jun 21 09:40:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Chan via B4 Relay X-Patchwork-Id: 13707166 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9D4716EBE8; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pLBloX56" Received: by smtp.kernel.org (Postfix) with ESMTPS id 76F84C4AF17; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718962857; bh=KVL37aI/mEK+Jaxu5LEBRdZLrd8x31HIyJv8AIRYS3k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pLBloX56cYGdDzwLdh1mobIBAH/Fd4ewnnFusdDhBv7H6nwiBBJtcT2YYocMhS8p0 D2KJWSFqdst1e3SqwB6EDTbbxTDf1thbK7jtB2TD/BkQfl3QFC3dI+rnauPEIvToBr FENowaym0w8TZjB7EbaK51JBG1+fdY5gprbns/yV65ELQO7l4iJYVJq4Yxn+b0YKVB BzmfqY3bVBdR9J8gFkRtqmThglQcFugkgCZKtYKvzXtg+KJw88XksSCXDvAf4eIlf0 2SAUqTnzH2971nKkkkTb/88pUg8jutA2HjjQg7Vn0mOFxExEIGMN67kPpdj0IgnViK C4b5ToQ0ZA6wQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DF08C2D0D0; Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:57 +0800 Subject: [PATCH 5/6] media: qcom: camss: Add sc7180 resources Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-5-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=6319; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=Nbr7Midohix3iAz4sw6Ut6JUp3rTkZVpkgm3ZSVgBf0=; b=UOtKxdLdTXVn54E94Mt1hoAQtQlJFUsvC4uZBRdD1GWc+ejxLIZDY6etCh3edg2Mo5UDQb8+X YsgN7fG3J3FBdPDwmA3UNEcWPbA25ME8Vr7LjAJXUlba6qIrYY15yTn X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan This commit describes the hardware layout for the sc7180 for the following hardware blocks: - 2 x VFE - 1 x VFE Lite - 2 x CSID - 1 x CSID Lite - 4 x CSI PHY Signed-off-by: George Chan --- drivers/media/platform/qcom/camss/camss.c | 218 +++++++++++++++++++++++++++++- 1 file changed, 217 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 1923615f0eea..d50f98565531 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -713,6 +713,210 @@ static const struct camss_subdev_resources vfe_res_845[] = { } }; +static const struct camss_subdev_resources csiphy_res_7180[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { + "csiphy0", + "csiphy0_timer" + }, + .clock_rate = { + { 150000000, 270000000, 360000000 }, + { 300000000 }, + }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { + "csiphy1", + "csiphy1_timer" + }, + .clock_rate = { + { 150000000, 270000000, 360000000 }, + { 300000000 }, + }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { + "csiphy2", + "csiphy2_timer" + }, + .clock_rate = { + { 150000000, 270000000, 360000000 }, + { 300000000 }, + }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .ops = &csiphy_ops_3ph_1_0 + }, + /* CSIPHY3 */ + { + .regulators = {}, + .clock = { + "csiphy3", + "csiphy3_timer" + }, + .clock_rate = { + { 150000000, 270000000, 360000000 }, + { 300000000 }, + }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .ops = &csiphy_ops_3ph_1_0 + } +}; + +static const struct camss_subdev_resources csid_res_7180[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { + "soc_ahb", + "vfe0", + "vfe0_cphy_rx", + "csi0" + }, + .clock_rate = { + { 0 }, + { 240000000, 360000000, 432000000, 600000000 }, + { 150000000, 270000000, 360000000 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .ops = &csid_ops_gen2 + }, + + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { + "soc_ahb", + "vfe1", + "vfe1_cphy_rx", + "csi1", + }, + .clock_rate = { + { 0 }, + { 240000000, 360000000, 432000000, 600000000 }, + { 150000000, 270000000, 360000000 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .ops = &csid_ops_gen2 + }, + + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { + "soc_ahb", + "vfe_lite", + "vfe_lite_cphy_rx", + "csi2", + }, + .clock_rate = { + { 0 }, + { 240000000, 360000000, 432000000, 600000000 }, + { 150000000, 270000000, 360000000 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .is_lite = true, + .ops = &csid_ops_gen2 + } +}; + +static const struct camss_subdev_resources vfe_res_7180[] = { + /* VFE0 */ + { + .regulators = {}, + .clock = { + "camnoc_axi", + "cpas_ahb", + "soc_ahb", + "vfe0", + "vfe0_axi", + "csi0", + }, + .clock_rate = { + { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 360000000, 432000000, 600000000 }, + { 0 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .pd_name = "ife0", + .line_num = 4, + .has_pd = true, + .ops = &vfe_ops_170 + }, + /* VFE1 */ + { + .regulators = {}, + .clock = { + "camnoc_axi", + "cpas_ahb", + "soc_ahb", + "vfe1", + "vfe1_axi", + "csi1", + }, + .clock_rate = { + { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 360000000, 432000000, 600000000 }, + { 0 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .pd_name = "ife1", + .line_num = 4, + .has_pd = true, + .ops = &vfe_ops_170 + }, + /* VFE-lite */ + { + .regulators = {}, + .clock = { + "camnoc_axi", + "cpas_ahb", + "soc_ahb", + "vfe_lite", + "csi2", + }, + .clock_rate = { + { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 360000000, 432000000, 600000000 }, + { 150000000, 270000000, 360000000, 480000000 }, + }, + .reg = { "vfe_lite" }, + .interrupt = { "vfe_lite" }, + .is_lite = true, + .line_num = 4, + .ops = &vfe_ops_170 + } +}; + static const struct camss_subdev_resources csiphy_res_8250[] = { /* CSIPHY0 */ { @@ -1263,7 +1467,7 @@ int camss_enable_clocks(int nclocks, struct camss_clock *clock, for (i = 0; i < nclocks; i++) { ret = clk_prepare_enable(clock[i].clk); if (ret) { - dev_err(dev, "clock enable failed: %d\n", ret); + dev_err(dev, "clock enable failed: %s %d\n", clock[i].name, ret); goto error; } } @@ -2105,6 +2309,17 @@ static const struct camss_resources sdm845_resources = { .vfe_num = ARRAY_SIZE(vfe_res_845), }; +static const struct camss_resources sc7180_resources = { + .version = CAMSS_7180, + .pd_name = "top", + .csiphy_res = csiphy_res_7180, + .csid_res = csid_res_7180, + .vfe_res = vfe_res_7180, + .csiphy_num = ARRAY_SIZE(csiphy_res_7180), + .csid_num = ARRAY_SIZE(csid_res_7180), + .vfe_num = ARRAY_SIZE(vfe_res_7180), +}; + static const struct camss_resources sm8250_resources = { .version = CAMSS_8250, .pd_name = "top", @@ -2137,6 +2352,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, + { .compatible = "qcom,sc7180-camss", .data = &sc7180_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } From patchwork Fri Jun 21 09:40:58 2024 Content-Type: text/plain; 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Fri, 21 Jun 2024 09:40:57 +0000 (UTC) From: George Chan via B4 Relay Date: Fri, 21 Jun 2024 17:40:58 +0800 Subject: [PATCH RFT 6/6] arm64: dts: qcom: sc7180: Add support for camss subsys Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240621-b4-sc7180-camss-v1-6-14937929f30e@gmail.com> References: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> In-Reply-To: <20240621-b4-sc7180-camss-v1-0-14937929f30e@gmail.com> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Chan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1718962855; l=4150; i=gchan9527@gmail.com; s=20240621; h=from:subject:message-id; bh=B8rhLES5xtNqCPArzEgX9w5nXV1pwjkOAbh2DRGd8HY=; b=P2glylTdS03cwFIQg4vYqmZQCnI2va7LPlU45e0jcpfBa3hgqbaEywoLDDqKmfKCqg7D+pnpg mhGmwOELNPLA4ShMM6oEpru5J/F7QDqc/VZj0md3oi/tJspGC24iV/8 X-Developer-Key: i=gchan9527@gmail.com; a=ed25519; pk=Ac2fkTqgUBlj2sns9hRIWJTYhWHO1BsmHbdBb5UpUUY= X-Endpoint-Received: by B4 Relay for gchan9527@gmail.com/20240621 with auth_id=176 X-Original-From: George Chan Reply-To: gchan9527@gmail.com From: George Chan Introduce camss subsys support to sc7180 family soc. Signed-off-by: George Chan --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 134 +++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b5ebf8980325..6ed4caafbe98 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -3150,6 +3151,139 @@ camnoc_virt: interconnect@ac00000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + camss: camss@acb3000 { + compatible = "qcom,sc7180-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0ac68000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe_lite"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "top"; + + required-opps = <&rpmhpd_opp_low_svs>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0x0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7180-camcc"; reg = <0 0x0ad00000 0 0x10000>;