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a=openpgp-sha256; l=2033; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=CRnQPNrk6tMn0RWlkSywOwQLtsZdvuYbpLeYPQfOvOQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbu+jggU2r5wb55W+ZbzfufMt2fcPzor3sSw rUcv0Se2GiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7gAKCRCLPIo+Aiko 1aqlB/9g7BBBZ26cS0eSgzqsLSSvrm6ZAuiCyVP1eUlsUiDQA5gCvnvZGreQjEHhTAjrEAQGkc8 FtKaWDgY7btLUi+DYxZ3zJiPOMy/Tqt9NaRV4HF77sS2baOrKIW41AvZk1dR7rYGACfbP3hqnlR diczBoF49Hp8YVnNuaQUs2TEFv+3SLVK6SjarADQiA0ZaLksy+0sJVIPviT8rK9l2hs3s/Pp0yE SIcj8k9POpjtz5+pSJQVF5uA4z0pjBoqLuhziHsxvOWmbXHc2oVXEe1u+nvB0Vb9vuPGHIH9N93 kRnUG9P6t6m5amGJvwOuwK2jW9XDFSKNlXZPEHbIgv4PsJ91 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A If the dpu_format_populate_layout() fails, then FB is prepared, but not cleaned up. This ends up leaking the pin_count on the GEM object and causes a splat during DRM file closure: msm_obj->pin_count WARNING: CPU: 2 PID: 569 at drivers/gpu/drm/msm/msm_gem.c:121 update_lru_locked+0xc4/0xcc [...] Call trace: update_lru_locked+0xc4/0xcc put_pages+0xac/0x100 msm_gem_free_object+0x138/0x180 drm_gem_object_free+0x1c/0x30 drm_gem_object_handle_put_unlocked+0x108/0x10c drm_gem_object_release_handle+0x58/0x70 idr_for_each+0x68/0xec drm_gem_release+0x28/0x40 drm_file_free+0x174/0x234 drm_release+0xb0/0x160 __fput+0xc0/0x2c8 __fput_sync+0x50/0x5c __arm64_sys_close+0x38/0x7c invoke_syscall+0x48/0x118 el0_svc_common.constprop.0+0x40/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x4c/0x120 el0t_64_sync_handler+0x100/0x12c el0t_64_sync+0x190/0x194 irq event stamp: 129818 hardirqs last enabled at (129817): [] console_unlock+0x118/0x124 hardirqs last disabled at (129818): [] el1_dbg+0x24/0x8c softirqs last enabled at (129808): [] handle_softirqs+0x4c8/0x4e8 softirqs last disabled at (129785): [] __do_softirq+0x14/0x20 Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 1c3a2657450c..eabc4813c649 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -680,6 +680,9 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, new_state->fb, &layout); if (ret) { DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); + if (pstate->aspace) + msm_framebuffer_cleanup(new_state->fb, pstate->aspace, + pstate->needs_dirtyfb); return ret; } From patchwork Mon Jun 24 14:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709639 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4369819FA82 for ; Mon, 24 Jun 2024 14:47:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719240439; cv=none; b=T+VMv2XqNp9uPObGvkOF3+iq/0h+WK1pqoFl0YKcDKjYgdUhNUavzjXDyp1jac2CA+CkzV6VpzlvEsU8hlSbGDEqOVEIkVL38cvU6OBfDRG+bmhn+RFtug+jVkDpbyjb+llRVoLfPj9rh1vzUhZkda2GtBZGc4t9F/rrq5q30qE= ARC-Message-Signature: i=1; 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Mon, 24 Jun 2024 07:47:15 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:08 +0300 Subject: [PATCH v4 02/16] drm/msm/dpu: fix error condition in dpu_encoder_virt_atomic_mode_set Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-2-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=957; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=7vP7o0FochLbD0Xxzl9C2B538GRcwP3COb8crkPmUOU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbuJwKa24N4M3csWqmLjl/yvXWGrIS5Dbxc/ fnHgz2KVlKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7gAKCRCLPIo+Aiko 1etuB/oC/397sgNrRpSvQW3fYMrq4rjPdn53SDAEGzYshP1DLO0GM7Axckw0GgwOGDG9SKNvfrF wA11CMfdcB1BCrgedxzmu25sDLHGQIoIB0H+a5X6fnLaQoqYt9H7jshYymwHugSNClQdSODpDJN VK0oUzbNSL8X2OwxmpVRuU2/KLdH8/BW3yc+AJL2lnFZGeGKGiSJXdjug/fz5DyVp8J/mXaa/Ek bReNuzxc5kPlv48WomDg9DjdoMUU/Lg5/FkX1scY8zojVeOsJO9J1h/u5sxuOS3zFxcTVVway4H u+f2MUbBxirh6ugA9Qyf+T/KheEQSaVndcrCZ3MJaw9EtRzC X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The commit b954fa6baaca ("drm/msm/dpu: Refactor rm iterator") removed zero-init of the hw_ctl array, but didn't change the error condition, that checked for hw_ctl[i] being NULL. Use indices check instead. Fixes: b954fa6baaca ("drm/msm/dpu: Refactor rm iterator") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 5d205e09cf45..7613005fbfea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1186,7 +1186,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } - if (!hw_ctl[i]) { + if (i >= num_ctl) { DPU_ERROR_ENC(dpu_enc, "no ctl block assigned at idx: %d\n", i); return; From patchwork Mon Jun 24 14:47:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709641 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6AED19FA8E for ; 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Mon, 24 Jun 2024 07:47:16 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ce88b0119sm212699e87.222.2024.06.24.07.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:47:15 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:09 +0300 Subject: [PATCH v4 03/16] drm/msm/dpu: move CRTC resource assignment to dpu_encoder_virt_atomic_mode_set Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-3-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5674; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+m6EcRPOVuIQ4Ug721Qf+o7LpvWeO2gPaRzcMB1CAms=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbv+lCDZcmtttJ+Vyy/aLapjmxxlpslC/UCp zEViRKo3VeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7wAKCRCLPIo+Aiko 1dXoB/oD8Bb3sqlC33TAJAskbzM1jPxUaR8zv+D4s8LxmWRJDDod4NdeKjMZfVWXRhObKnjXPWF DE9M10kPevPDUG4SVwFiLLEVJdEOQSOmXjlArP+FPTAfqCkUuMKMe7rgT+C591Bdugwyj/wVVvj VdmJdKCQgDwSYjnHou7fbHcnJwqBm2N7IcrRgA9+qDwalZKGuNn6jWdZyZtYgSD0ftf7XwSaW/Y iQqsVCiEZiDJ51tFns9pYIzODC8YXAzd2jK6zQ+Yfa9pKxdg/jMxZSHuf/qr+5+GDdqs3VFwu2G SQGXpCFuhmQ620bLb+MIoWj7XJXWrhydqa4UJNKqaUB/iamX X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Historically CRTC resources (LMs and CTLs) were assigned in dpu_crtc_atomic_begin(). The commit 9222cdd27e82 ("drm/msm/dpu: move hw resource tracking to crtc state") simply moved resources to struct dpu_crtc_state, without changing the code sequence. Later on the commit b107603b4ad0 ("drm/msm/dpu: map mixer/ctl hw blocks in encoder modeset") rearanged the code, but still kept the cstate->num_mixers assignment to happen during commit phase. This makes dpu_crtc_state inconsistent between consequent atomic_check() calls. Move CRTC resource assignment to happen at the end of dpu_encoder_virt_atomic_check(). Fixes: b107603b4ad0 ("drm/msm/dpu: map mixer/ctl hw blocks in encoder modeset") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 -- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 60 +++++++++++++++++++---------- 2 files changed, 39 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9f2164782844..7399794d75eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1094,9 +1094,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); - memset(cstate->mixers, 0, sizeof(cstate->mixers)); - cstate->num_mixers = 0; - /* disable clk & bw control until clk & bw properties are set */ cstate->bw_control = false; cstate->bw_split_vote = false; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 7613005fbfea..98f3a8d84300 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -628,6 +628,41 @@ static struct msm_display_topology dpu_encoder_get_topology( return topology; } +static void dpu_encoder_assign_crtc_resources(struct dpu_kms *dpu_kms, + struct drm_encoder *drm_enc, + struct dpu_global_state *global_state, + struct drm_crtc_state *crtc_state) +{ + struct dpu_crtc_state *cstate; + struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC]; + int num_lm, num_ctl, num_dspp, i; + + cstate = to_dpu_crtc_state(crtc_state); + + memset(cstate->mixers, 0, sizeof(cstate->mixers)); + + num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + ARRAY_SIZE(hw_dspp)); + + for (i = 0; i < num_lm; i++) { + int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); + + cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); + cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); + if (i < num_dspp) + cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); + } + + cstate->num_mixers = num_lm; +} + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state, @@ -698,6 +733,9 @@ static int dpu_encoder_virt_atomic_check( drm_enc, crtc_state, topology); } + if (!ret) + dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc, global_state, crtc_state); + trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); return ret; @@ -1097,14 +1135,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; struct dpu_kms *dpu_kms; - struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_ctl, num_pp, num_dsc; unsigned int dsc_mask = 0; int i; @@ -1133,11 +1168,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, ARRAY_SIZE(hw_pp)); num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); - num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); - dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -1163,18 +1193,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } - cstate = to_dpu_crtc_state(crtc_state); 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Mon, 24 Jun 2024 07:47:16 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ce88b0119sm212699e87.222.2024.06.24.07.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:47:16 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:10 +0300 Subject: [PATCH v4 04/16] drm/msm/dpu: check for overflow in _dpu_crtc_setup_lm_bounds() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-4-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2549; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=CZE5vDwajgZiWlqIb9olYzIUdaIeeSo/h+Ci8Lw3dmw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbv8tPawkIlNzBU4WuRY5zvu7hLWv5V80J4r b43g5OLjhqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7wAKCRCLPIo+Aiko 1aLOB/9TRPnoQotfNBwvjifZD/Pvgrbrm8iQ5GUzJNnUHUiyeYJvB1iNjVIOcXqvtv4T/QeaNQP Khr5m8POepERwJDFEt/ZTbPdHsaQ7l7piTZ+F7MGFvG6m6zQ01ng/NqeD8UNDju1QLGhjD9GhVK qyiBtOiJEfrTP6tYmBLh9fsNE9Cb9Pr7mDZW9p4x/prlW05o11nxvQvxHt4gQlbiknlb6AA6ZNQ JrbbDfVV1K9Whyu9HS5tdnPh5DSq6/4nHP6l1lco2dGyiz3RKPmNnbWHr7uSQaZlAbkWeuRUbcR cMYfWBjBS6IQpYWumvOaiyRvRTpTXHJy7ig1882+S834duvo X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Make _dpu_crtc_setup_lm_bounds() check that CRTC width is not overflowing LM requirements. Rename the function accordingly. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 7399794d75eb..2a87dd7188b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -711,12 +711,13 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc) _dpu_crtc_complete_flip(crtc); } -static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, +static int _dpu_crtc_check_and_setup_lm_bounds(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); struct drm_display_mode *adj_mode = &state->adjusted_mode; u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; + struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); int i; for (i = 0; i < cstate->num_mixers; i++) { @@ -727,7 +728,12 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, r->y2 = adj_mode->vdisplay; trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); + + if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width) + return -E2BIG; } + + return 0; } static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state, @@ -803,7 +809,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); - _dpu_crtc_setup_lm_bounds(crtc, crtc->state); + _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc->state); /* encoder will trigger pending mask now */ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) @@ -1194,8 +1200,11 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (crtc_state->active_changed) crtc_state->mode_changed = true; - if (cstate->num_mixers) - _dpu_crtc_setup_lm_bounds(crtc, crtc_state); + if (cstate->num_mixers) { + rc = _dpu_crtc_check_and_setup_lm_bounds(crtc, crtc_state); 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Mon, 24 Jun 2024 07:47:17 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:11 +0300 Subject: [PATCH v4 05/16] drm/msm/dpu: drop dpu_format_check_modified_format Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-5-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4305; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ejH+ol5T532KyZrIFuLloTm2XyxOOkDo+QG+9a6aKvc=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1pl2/sliq/t4pod9azmRz9cezTSbPmGpPR573jEX3i6e T5PmL2vk9GYhYGRi0FWTJHFp6Blasym5LAPO6bWwwxiZQKZwsDFKQATschn/+9Sm3b0peCbriX8 MgGe4uUnvJWXvTO/UbT9rNHDioisxOxFBx5YXzxRvf/sTddgP3uHCWyak17Nneyf9u683JrpPzc 9+F7VfvWBzu/bhYk9mU+7jvaacMr05m8PuK8t1/loz+SzsxJ1DppZ2N/kN0uJifASMPPkOrTCLE rc/3HKgfWZnYqTzBN/C91qbbfSKD3o+3GPdtryQL5FQvkFdRfT9NZH8U5mDY6ecPGs+tmDqzS6k pff1q+ctMr/cNGeeonQtJcKjaafE8waedh4oqS9+0XzZKVvbj4us1DcQOdVt9HvK3u3cpYs/8Sd 01G4/KhnaKSzXu2C31tvlsmEHudRy77BfujaxqQg8zQBAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The msm_kms_funcs::check_modified_format() callback is not used by the driver. Drop it completely. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 43 ----------------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 16 ----------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 - drivers/gpu/drm/msm/msm_kms.h | 6 ---- 4 files changed, 66 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 6b1e9a617da3..027eb5ecff08 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -423,46 +423,3 @@ int dpu_format_populate_layout( return ret; } - -int dpu_format_check_modified_format( - const struct msm_kms *kms, - const struct msm_format *fmt, - const struct drm_mode_fb_cmd2 *cmd, - struct drm_gem_object **bos) -{ - const struct drm_format_info *info; - struct dpu_hw_fmt_layout layout; - uint32_t bos_total_size = 0; - int ret, i; - - if (!fmt || !cmd || !bos) { - DRM_ERROR("invalid arguments\n"); - return -EINVAL; - } - - info = drm_format_info(fmt->pixel_format); - if (!info) - return -EINVAL; - - ret = dpu_format_get_plane_sizes(fmt, cmd->width, cmd->height, - &layout, cmd->pitches); - if (ret) - return ret; - - for (i = 0; i < info->num_planes; i++) { - if (!bos[i]) { - DRM_ERROR("invalid handle for plane %d\n", i); - return -EINVAL; - } - if ((i == 0) || (bos[i] != bos[0])) - bos_total_size += bos[i]->size; - } - - if (bos_total_size < layout.total_size) { - DRM_ERROR("buffers total size too small %u expected %u\n", - bos_total_size, layout.total_size); - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h index 210d0ed5f0af..ef1239c95058 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h @@ -31,22 +31,6 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats, return false; } -/** - * dpu_format_check_modified_format - validate format and buffers for - * dpu non-standard, i.e. modified format - * @kms: kms driver - * @msm_fmt: pointer to the msm_fmt base pointer of an msm_format - * @cmd: fb_cmd2 structure user request - * @bos: gem buffer object list - * - * Return: error code on failure, 0 on success - */ -int dpu_format_check_modified_format( - const struct msm_kms *kms, - const struct msm_format *msm_fmt, - const struct drm_mode_fb_cmd2 *cmd, - struct drm_gem_object **bos); - /** * dpu_format_populate_layout - populate the given format layout based on * mmu, fb, and format found in the fb diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d1e2143110f2..40e4b829b9da 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1025,7 +1025,6 @@ static const struct msm_kms_funcs kms_funcs = { .complete_commit = dpu_kms_complete_commit, .enable_vblank = dpu_kms_enable_vblank, .disable_vblank = dpu_kms_disable_vblank, - .check_modified_format = dpu_format_check_modified_format, .destroy = dpu_kms_destroy, .snapshot = dpu_kms_mdp_snapshot, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 1e0c54de3716..e60162744c66 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -92,12 +92,6 @@ struct msm_kms_funcs { * Format handling: */ - /* do format checking on format modified through fb_cmd2 modifiers */ - int (*check_modified_format)(const struct msm_kms *kms, - const struct msm_format *msm_fmt, - const struct drm_mode_fb_cmd2 *cmd, - struct drm_gem_object **bos); - /* misc: */ long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, struct drm_encoder *encoder); From patchwork Mon Jun 24 14:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709643 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D852D19FA8B for ; Mon, 24 Jun 2024 14:47:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719240441; cv=none; b=MnvIEeeuXTFGo77f/Pe7IzBNDJcJJXISAfAnGpaD2d8mGIHWRpDqgddTH05fTIMpXnDAhNGcxRTBhX4pHtISJiwUb36qiWrb3oT/g0Eg/HbbYfAumUqVSA9hZwpDKEhcuyRpuqBS6nzTF5Zmn0VpMO0F423asW2z7yz+TNAiWqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 24 Jun 2024 07:47:17 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:12 +0300 Subject: [PATCH v4 06/16] drm/msm/dpu: drop dpu_format_populate_layout from dpu_plane_sspp_atomic_update Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-6-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3364; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=EolmHRhwGXXQUzrkytdeQx4Mh8dKlNx5sMNxyMkQHl4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbv72B9V3iefGPWeIHr1+B/BabWUEjMIFcJC wUzvrn/t0uJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7wAKCRCLPIo+Aiko 1RknB/9bSdIVf5ZCOI+Rzc50netnzopJnWbRMkvL6CV+axROugiqdEMHL416YrhuSaZhYrubJbP LVOnd43VVOo4BJJfAkZhDCv8CSXUfWO5zj/RWee7YLy4m8bKqNpGxb4dMPXz3/Ni7k4EQnYsAjQ tkUcPMimbrPCTaE3zrk8bHG57NQkX4vZAuI+/sJxzeJboPLlz4c9WW1rdNwfSwVu2H3EhK5U6Du c0m+YcfQRum8gH/JjIMxe5ei44+XFIx2wBRNs62JRUtLPN8Zvqkrua6q6SpzHZVldaHgMcVQxsU HgQgFiKDqLk6DUncpBpKrKyYv4YpwLgyQWHLcnt0GId/511W X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The dpu_plane_prepare_fb() already calls dpu_format_populate_layout(). Store the generated layout in the plane state and drop this call from dpu_plane_sspp_update(). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 19 ++++--------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 3 +++ 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index eabc4813c649..241c2d7a218a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -647,7 +647,6 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, struct drm_framebuffer *fb = new_state->fb; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_state); - struct dpu_hw_fmt_layout layout; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); int ret; @@ -677,7 +676,8 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, /* validate framebuffer layout before commit */ ret = dpu_format_populate_layout(pstate->aspace, - new_state->fb, &layout); + new_state->fb, + &pstate->layout); if (ret) { DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); if (pstate->aspace) @@ -1103,17 +1103,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) msm_framebuffer_format(fb); struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; - struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - struct msm_gem_address_space *aspace = kms->base.aspace; - struct dpu_hw_fmt_layout layout; - bool layout_valid = false; - int ret; - - ret = dpu_format_populate_layout(aspace, fb, &layout); - if (ret) - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else - layout_valid = true; pstate->pending = true; @@ -1128,12 +1117,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); + &pstate->layout); if (r_pipe->sspp) { dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); + &pstate->layout); } if (pstate->needs_qos_remap) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index abd6b21a049b..348b0075d1ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -31,6 +31,7 @@ * @plane_clk: calculated clk per plane * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed * @rotation: simplified drm rotation hint + * @layout: framebuffer memory layout */ struct dpu_plane_state { struct drm_plane_state base; @@ -48,6 +49,8 @@ struct dpu_plane_state { bool needs_dirtyfb; unsigned int rotation; + + struct dpu_hw_fmt_layout layout; }; #define to_dpu_plane_state(x) \ From patchwork Mon Jun 24 14:47:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709644 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7521A00ED for ; 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Mon, 24 Jun 2024 07:47:18 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ce88b0119sm212699e87.222.2024.06.24.07.47.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:47:18 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:13 +0300 Subject: [PATCH v4 07/16] drm/msm/dpu: drop extra aspace checks in dpu_formats Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-7-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1504; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=BXjW3vQxsmZuyH1IlNRwIHSsrpZblZLTmW9M+NxSCGU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbv084XpneWPffyXo4xAWuPs5p8u2l9ugMFU bL+pUaBr2uJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7wAKCRCLPIo+Aiko 1bxfCACR9EzuNAh0cZysy87aKSG7MkjSjyEdt/RZsPW/aaLTwYXAfah8bhHwMuWeF0M957zNJFl jiZNivfmAYo615w2F507VQG5nhoM1xlZZXYNrOsfCu2pUegu6LPz49ov52QZDeQb5VIRK/0Z0RQ Znj63lqLU6qkX1jpGb9dJ92LNWT5QMzKnZJwv4fqKnICXYcvMmGOqgIKHzAxm9YG0Ivawa2+1L5 Z3FZH0PqhfkJmpAa4g35+9ZQL/smVan9AO1csAW+22Dp3pZHZGhjFswd5qH8krfToolUcyJjeLo WOnEPTc2lKqnljPmBf2vKqCXxTHKe8JuRvj7NIjbIUiC8YDx X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The DPU driver isn't expected to be used without an IOMMU. Thus the aspace will be always present. Not to mention that mdp4/mdp5 drivers call msm_framebuffer_iova() without such checks, as the whole msm_framebuffer layer is expected to support both IOMMU and IOMMU-less configurations. Drop these useless if (aspace) checks. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 027eb5ecff08..8c2dc5b59bb0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -280,8 +280,7 @@ static int _dpu_format_populate_addrs_ubwc( return -EINVAL; } - if (aspace) - base_addr = msm_framebuffer_iova(fb, aspace, 0); + base_addr = msm_framebuffer_iova(fb, aspace, 0); if (!base_addr) { DRM_ERROR("failed to retrieve base addr\n"); return -EFAULT; @@ -376,9 +375,7 @@ static int _dpu_format_populate_addrs_linear( /* Populate addresses for simple formats here */ for (i = 0; i < layout->num_planes; ++i) { - if (aspace) - layout->plane_addr[i] = - msm_framebuffer_iova(fb, aspace, i); + layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i); if (!layout->plane_addr[i]) { DRM_ERROR("failed to retrieve base addr\n"); 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a=openpgp-sha256; l=8016; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Gya5f4ZwULk71hxrRoz5QSdtb64ucMxjJc7p3y8Bcb8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbvUa3G+dgmIzjoA0aVhlyC+LGx7erNQaKBr QYhsV2Dm62JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG7wAKCRCLPIo+Aiko 1a0aB/9bel8aZo3E5z5ATF6iNEHVV63Y7LCW7v1nN1+aT01IMD+Ddi/0SdqUPcj3RtAQMP7ATqA ZEmKj3B4ylE1hy9FqTc4+qeyNuJKgucilGeQqk+mnkjM6n2scNxOtfR2k7o1sGtf01CwfgSykHt 6FhhGOnttXapAN89r6Luiyol4JUBy+fec5eIRJo5uiuEfDkUpjTgJDkew7aKQR9UvVDWrxTZino LTag5J7KlmR81CRwCU0VKOQGkw4jZ6ILLX9x39L24XjPyb1kw3xRLO/vRxsgr1LEhKMMjVc1p85 Bh/VTDGHu6MLHl8BE84yVch25Z2fbpY3bO0bZt86yky63DQz X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The struct dpu_hw_fmt_layout defines hardware data layout (addresses, sizes and pitches. Drop format field from this structure as it's not a part of the data layout. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 18 +++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 23 +++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 3 ++- 5 files changed, 21 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 882c717859ce..acbba6d4e68c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -193,12 +193,12 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, hw_wb->ops.setup_roi(hw_wb, wb_cfg); if (hw_wb->ops.setup_outformat) - hw_wb->ops.setup_outformat(hw_wb, wb_cfg); + hw_wb->ops.setup_outformat(hw_wb, wb_cfg, msm_framebuffer_format(fb)); if (hw_wb->ops.setup_cdp) { const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf; - hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format, + hw_wb->ops.setup_cdp(hw_wb, msm_framebuffer_format(fb), perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable); } @@ -584,14 +584,6 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc format = msm_framebuffer_format(job->fb); - wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base, - format->pixel_format, job->fb->modifier); - if (!wb_cfg->dest.format) { - /* this error should be detected during atomic_check */ - DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format); - return; - } - ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest); if (ret) { DPU_DEBUG("failed to populate layout %d\n", ret); @@ -600,10 +592,10 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc wb_cfg->dest.width = job->fb->width; wb_cfg->dest.height = job->fb->height; - wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes; + wb_cfg->dest.num_planes = format->num_planes; - if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) && - (wb_cfg->dest.format->element[0] == C1_B_Cb)) + if ((format->fetch_type == MDP_PLANE_PLANAR) && + (format->element[0] == C1_B_Cb)) swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]); DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n", diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 8c2dc5b59bb0..46237a1ca6a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -104,7 +104,6 @@ static int _dpu_format_get_plane_sizes_ubwc( bool meta = MSM_FORMAT_IS_UBWC(fmt); memset(layout, 0, sizeof(struct dpu_hw_fmt_layout)); - layout->format = fmt; layout->width = width; layout->height = height; layout->num_planes = fmt->num_planes; @@ -116,7 +115,7 @@ static int _dpu_format_get_plane_sizes_ubwc( return -EINVAL; } - if (MSM_FORMAT_IS_YUV(layout->format)) { + if (MSM_FORMAT_IS_YUV(fmt)) { uint32_t y_sclines, uv_sclines; uint32_t y_meta_scanlines = 0; uint32_t uv_meta_scanlines = 0; @@ -182,7 +181,6 @@ static int _dpu_format_get_plane_sizes_linear( int i; memset(layout, 0, sizeof(struct dpu_hw_fmt_layout)); - layout->format = fmt; layout->width = width; layout->height = height; layout->num_planes = fmt->num_planes; @@ -190,8 +188,8 @@ static int _dpu_format_get_plane_sizes_linear( /* Due to memset above, only need to set planes of interest */ if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) { layout->num_planes = 1; - layout->plane_size[0] = width * height * layout->format->bpp; - layout->plane_pitch[0] = width * layout->format->bpp; + layout->plane_size[0] = width * height * fmt->bpp; + layout->plane_pitch[0] = width * fmt->bpp; } else { uint32_t v_subsample, h_subsample; uint32_t chroma_samp; @@ -272,6 +270,7 @@ static int _dpu_format_populate_addrs_ubwc( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { + const struct msm_format *fmt; uint32_t base_addr = 0; bool meta; @@ -286,10 +285,11 @@ static int _dpu_format_populate_addrs_ubwc( return -EFAULT; } - meta = MSM_FORMAT_IS_UBWC(layout->format); + fmt = msm_framebuffer_format(fb); + meta = MSM_FORMAT_IS_UBWC(fmt); /* Per-format logic for verifying active planes */ - if (MSM_FORMAT_IS_YUV(layout->format)) { + if (MSM_FORMAT_IS_YUV(fmt)) { /************************************************/ /* UBWC ** */ /* buffer ** DPU PLANE */ @@ -390,6 +390,7 @@ int dpu_format_populate_layout( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { + const struct msm_format *fmt; int ret; if (!fb || !layout) { @@ -403,17 +404,17 @@ int dpu_format_populate_layout( return -ERANGE; } - layout->format = msm_framebuffer_format(fb); + fmt = msm_framebuffer_format(fb); /* Populate the plane sizes etc via get_format */ - ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height, + ret = dpu_format_get_plane_sizes(fmt, fb->width, fb->height, layout, fb->pitches); if (ret) return ret; /* Populate the addresses given the fb */ - if (MSM_FORMAT_IS_UBWC(layout->format) || - MSM_FORMAT_IS_TILE(layout->format)) + if (MSM_FORMAT_IS_UBWC(fmt) || + MSM_FORMAT_IS_TILE(fmt)) ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout); else ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index a2eff36a2224..f8806a4d317b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -293,7 +293,6 @@ enum dpu_3d_blend_mode { /** * struct dpu_hw_fmt_layout - format information of the source pixel data - * @format: pixel format parameters * @num_planes: number of planes (including meta data planes) * @width: image width * @height: image height @@ -303,7 +302,6 @@ enum dpu_3d_blend_mode { * @plane_pitch: pitch of each plane */ struct dpu_hw_fmt_layout { - const struct msm_format *format; uint32_t num_planes; uint32_t width; uint32_t height; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index 93ff01c889b5..f39db534697d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -64,10 +64,10 @@ static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx, } static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, - struct dpu_hw_wb_cfg *data) + struct dpu_hw_wb_cfg *data, + const struct msm_format *fmt) { struct dpu_hw_blk_reg_map *c = &ctx->hw; - const struct msm_format *fmt = data->dest.format; u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp; u32 write_config = 0; u32 opmode = 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index 37497473e16c..b240a4f7b33a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -37,7 +37,8 @@ struct dpu_hw_wb_ops { struct dpu_hw_wb_cfg *wb); void (*setup_outformat)(struct dpu_hw_wb *ctx, - struct dpu_hw_wb_cfg *wb); + struct dpu_hw_wb_cfg *wb, + const struct msm_format *fmt); void (*setup_roi)(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb); From patchwork Mon Jun 24 14:47:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709647 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA30E19FA82 for ; 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a=openpgp-sha256; l=7789; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=bp6A68kJPDBcsi8eZULofLfrBBdJDRmZZyWTdQOEhY4=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1pl24fvyu4akw/UT8q//WNf7ZEvz73rt3D8aWbOPXgpN oIr4VZSJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAm8n0T+/+Qyw27WgtOP7aY KZw8lefdqupELdXYwkJrro6tAapK6rsFfskdFQq3jn/EaVL8zkZO5Wufq/ty1hj5biuf98zbj4d ctBCa/cioxULkh3m3sVZbhc0S5a/yRyKPrU3WcDV8Xbwx4pJ4cezHtORvz97P9zDaeWm/hcLsp0 w1y94KSweUPfM8c0tq2fLTE2vPXm23V31vnJq05J747PeR2QHPi6/O0xYxWDBry4HkmJzXIlHt/ KtnWzsI9t01CJX9sHZbUMKfNY8+b7lS+Hm/SLZ6HnOt63v2zE9Pf/On1zvanH/bxPE4Wzt4lkNj hxz/RsaoyW7zH7qdLtHi4ug83/pN/ayoAbdT+E/fFFNPAA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Instead of passing width / height / pitches, pass drm_framebuffer directly. This allows us to drop the useless check for !pitches, since an array can not be NULL. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 73 ++++++++++++++--------------- 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 46237a1ca6a5..df046bc88715 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -95,8 +95,7 @@ static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt) static int _dpu_format_get_plane_sizes_ubwc( const struct msm_format *fmt, - const uint32_t width, - const uint32_t height, + struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { int i; @@ -104,8 +103,8 @@ static int _dpu_format_get_plane_sizes_ubwc( bool meta = MSM_FORMAT_IS_UBWC(fmt); memset(layout, 0, sizeof(struct dpu_hw_fmt_layout)); - layout->width = width; - layout->height = height; + layout->width = fb->width; + layout->height = fb->height; layout->num_planes = fmt->num_planes; color = _dpu_format_get_media_color_ubwc(fmt); @@ -121,13 +120,13 @@ static int _dpu_format_get_plane_sizes_ubwc( uint32_t uv_meta_scanlines = 0; layout->num_planes = 2; - layout->plane_pitch[0] = VENUS_Y_STRIDE(color, width); - y_sclines = VENUS_Y_SCANLINES(color, height); + layout->plane_pitch[0] = VENUS_Y_STRIDE(color, fb->width); + y_sclines = VENUS_Y_SCANLINES(color, fb->height); layout->plane_size[0] = MSM_MEDIA_ALIGN(layout->plane_pitch[0] * y_sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); - layout->plane_pitch[1] = VENUS_UV_STRIDE(color, width); - uv_sclines = VENUS_UV_SCANLINES(color, height); + layout->plane_pitch[1] = VENUS_UV_STRIDE(color, fb->width); + uv_sclines = VENUS_UV_SCANLINES(color, fb->height); layout->plane_size[1] = MSM_MEDIA_ALIGN(layout->plane_pitch[1] * uv_sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); @@ -135,13 +134,13 @@ static int _dpu_format_get_plane_sizes_ubwc( goto done; layout->num_planes += 2; - layout->plane_pitch[2] = VENUS_Y_META_STRIDE(color, width); - y_meta_scanlines = VENUS_Y_META_SCANLINES(color, height); + layout->plane_pitch[2] = VENUS_Y_META_STRIDE(color, fb->width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color, fb->height); layout->plane_size[2] = MSM_MEDIA_ALIGN(layout->plane_pitch[2] * y_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); - layout->plane_pitch[3] = VENUS_UV_META_STRIDE(color, width); - uv_meta_scanlines = VENUS_UV_META_SCANLINES(color, height); + layout->plane_pitch[3] = VENUS_UV_META_STRIDE(color, fb->width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color, fb->height); layout->plane_size[3] = MSM_MEDIA_ALIGN(layout->plane_pitch[3] * uv_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); @@ -150,16 +149,16 @@ static int _dpu_format_get_plane_sizes_ubwc( layout->num_planes = 1; - layout->plane_pitch[0] = VENUS_RGB_STRIDE(color, width); - rgb_scanlines = VENUS_RGB_SCANLINES(color, height); + layout->plane_pitch[0] = VENUS_RGB_STRIDE(color, fb->width); + rgb_scanlines = VENUS_RGB_SCANLINES(color, fb->height); layout->plane_size[0] = MSM_MEDIA_ALIGN(layout->plane_pitch[0] * rgb_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); if (!meta) goto done; layout->num_planes += 2; - layout->plane_pitch[2] = VENUS_RGB_META_STRIDE(color, width); - rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color, height); + layout->plane_pitch[2] = VENUS_RGB_META_STRIDE(color, fb->width); + rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color, fb->height); layout->plane_size[2] = MSM_MEDIA_ALIGN(layout->plane_pitch[2] * rgb_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT); } @@ -173,23 +172,21 @@ static int _dpu_format_get_plane_sizes_ubwc( static int _dpu_format_get_plane_sizes_linear( const struct msm_format *fmt, - const uint32_t width, - const uint32_t height, - struct dpu_hw_fmt_layout *layout, - const uint32_t *pitches) + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout) { int i; memset(layout, 0, sizeof(struct dpu_hw_fmt_layout)); - layout->width = width; - layout->height = height; + layout->width = fb->width; + layout->height = fb->height; layout->num_planes = fmt->num_planes; /* Due to memset above, only need to set planes of interest */ if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) { layout->num_planes = 1; - layout->plane_size[0] = width * height * fmt->bpp; - layout->plane_pitch[0] = width * fmt->bpp; + layout->plane_size[0] = fb->width * fb->height * fmt->bpp; + layout->plane_pitch[0] = fb->width * fmt->bpp; } else { uint32_t v_subsample, h_subsample; uint32_t chroma_samp; @@ -199,7 +196,7 @@ static int _dpu_format_get_plane_sizes_linear( _dpu_get_v_h_subsample_rate(chroma_samp, &v_subsample, &h_subsample); - if (width % h_subsample || height % v_subsample) { + if (fb->width % h_subsample || fb->height % v_subsample) { DRM_ERROR("mismatch in subsample vs dimensions\n"); return -EINVAL; } @@ -207,11 +204,11 @@ static int _dpu_format_get_plane_sizes_linear( if ((fmt->pixel_format == DRM_FORMAT_NV12) && (MSM_FORMAT_IS_DX(fmt))) bpp = 2; - layout->plane_pitch[0] = width * bpp; + layout->plane_pitch[0] = fb->width * bpp; layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample; - layout->plane_size[0] = layout->plane_pitch[0] * height; + layout->plane_size[0] = layout->plane_pitch[0] * fb->height; layout->plane_size[1] = layout->plane_pitch[1] * - (height / v_subsample); + (fb->height / v_subsample); if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { layout->num_planes = 2; @@ -232,8 +229,8 @@ static int _dpu_format_get_plane_sizes_linear( * all the components based on ubwc specifications. */ for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) { - if (pitches && layout->plane_pitch[i] < pitches[i]) - layout->plane_pitch[i] = pitches[i]; + if (layout->plane_pitch[i] < fb->pitches[i]) + layout->plane_pitch[i] = fb->pitches[i]; } for (i = 0; i < DPU_MAX_PLANES; i++) @@ -244,25 +241,24 @@ static int _dpu_format_get_plane_sizes_linear( static int dpu_format_get_plane_sizes( const struct msm_format *fmt, - const uint32_t w, - const uint32_t h, - struct dpu_hw_fmt_layout *layout, - const uint32_t *pitches) + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout) { if (!layout || !fmt) { DRM_ERROR("invalid pointer\n"); return -EINVAL; } - if ((w > DPU_MAX_IMG_WIDTH) || (h > DPU_MAX_IMG_HEIGHT)) { + if (fb->width > DPU_MAX_IMG_WIDTH || + fb->height > DPU_MAX_IMG_HEIGHT) { DRM_ERROR("image dimensions outside max range\n"); return -ERANGE; } if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt)) - return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout); + return _dpu_format_get_plane_sizes_ubwc(fmt, fb, layout); - return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches); + return _dpu_format_get_plane_sizes_linear(fmt, fb, layout); } static int _dpu_format_populate_addrs_ubwc( @@ -407,8 +403,7 @@ int dpu_format_populate_layout( fmt = msm_framebuffer_format(fb); /* Populate the plane sizes etc via get_format */ - ret = dpu_format_get_plane_sizes(fmt, fb->width, fb->height, - layout, fb->pitches); + ret = dpu_format_get_plane_sizes(fmt, fb, layout); if (ret) return ret; From patchwork Mon Jun 24 14:47:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709648 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84E2319D89C for ; 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Mon, 24 Jun 2024 07:47:20 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ce88b0119sm212699e87.222.2024.06.24.07.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:47:20 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:16 +0300 Subject: [PATCH v4 10/16] drm/msm/dpu: move pitch check to _dpu_format_get_plane_sizes_linear() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-10-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Move the check to the same place, demoting DPU_ERROR to DPU_DEBUG to prevent user from spamming the kernel log. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index df046bc88715..4d17eb88af40 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -229,8 +229,13 @@ static int _dpu_format_get_plane_sizes_linear( * all the components based on ubwc specifications. */ for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) { - if (layout->plane_pitch[i] < fb->pitches[i]) + if (layout->plane_pitch[i] <= fb->pitches[i]) { layout->plane_pitch[i] = fb->pitches[i]; + } else { + DRM_DEBUG("plane %u expected pitch %u, fb %u\n", + i, layout->plane_pitch[i], fb->pitches[i]); + return -EINVAL; + } } for (i = 0; i < DPU_MAX_PLANES; i++) @@ -360,15 +365,6 @@ static int _dpu_format_populate_addrs_linear( { unsigned int i; - /* Can now check the pitches given vs pitches expected */ - for (i = 0; i < layout->num_planes; ++i) { - if (layout->plane_pitch[i] > fb->pitches[i]) { - DRM_ERROR("plane %u expected pitch %u, fb %u\n", - i, layout->plane_pitch[i], fb->pitches[i]); - return -EINVAL; - } - } - /* Populate addresses for simple formats here */ for (i = 0; i < layout->num_planes; ++i) { layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i); From patchwork Mon Jun 24 14:47:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709649 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40CC913D2BC for ; Mon, 24 Jun 2024 14:47:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 8 +++++- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 32 +++++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 8 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++++-- 4 files changed, 44 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index acbba6d4e68c..d8e37400d852 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -584,7 +584,13 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc format = msm_framebuffer_format(job->fb); - ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest); + ret = dpu_format_populate_plane_sizes(job->fb, &wb_cfg->dest); + if (ret) { + DPU_DEBUG("failed to populate plane sizes%d\n", ret); + return; + } + + ret = dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest); if (ret) { DPU_DEBUG("failed to populate layout %d\n", ret); return; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 4d17eb88af40..abe3a1c0e409 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -93,7 +93,7 @@ static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt) return color_fmt; } -static int _dpu_format_get_plane_sizes_ubwc( +static int _dpu_format_populate_plane_sizes_ubwc( const struct msm_format *fmt, struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) @@ -170,7 +170,7 @@ static int _dpu_format_get_plane_sizes_ubwc( return 0; } -static int _dpu_format_get_plane_sizes_linear( +static int _dpu_format_populate_plane_sizes_linear( const struct msm_format *fmt, struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) @@ -244,12 +244,21 @@ static int _dpu_format_get_plane_sizes_linear( return 0; } -static int dpu_format_get_plane_sizes( - const struct msm_format *fmt, +/* + * dpu_format_populate_addrs - populate non-address part of the layout based on + * fb, and format found in the fb + * @fb: framebuffer pointer + * @layout: format layout structure to populate + * + * Return: error code on failure or 0 if new addresses were populated + */ +int dpu_format_populate_plane_sizes( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { - if (!layout || !fmt) { + const struct msm_format *fmt; + + if (!layout || !fb) { DRM_ERROR("invalid pointer\n"); return -EINVAL; } @@ -260,10 +269,12 @@ static int dpu_format_get_plane_sizes( return -ERANGE; } + fmt = msm_framebuffer_format(fb); + if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt)) - return _dpu_format_get_plane_sizes_ubwc(fmt, fb, layout); + return _dpu_format_populate_plane_sizes_ubwc(fmt, fb, layout); - return _dpu_format_get_plane_sizes_linear(fmt, fb, layout); + return _dpu_format_populate_plane_sizes_linear(fmt, fb, layout); } static int _dpu_format_populate_addrs_ubwc( @@ -377,7 +388,7 @@ static int _dpu_format_populate_addrs_linear( return 0; } -int dpu_format_populate_layout( +int dpu_format_populate_addrs( struct msm_gem_address_space *aspace, struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) @@ -398,11 +409,6 @@ int dpu_format_populate_layout( fmt = msm_framebuffer_format(fb); - /* Populate the plane sizes etc via get_format */ - ret = dpu_format_get_plane_sizes(fmt, fb, layout); - if (ret) - return ret; - /* Populate the addresses given the fb */ if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h index ef1239c95058..2f2bff14c0db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h @@ -32,7 +32,7 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats, } /** - * dpu_format_populate_layout - populate the given format layout based on + * dpu_format_populate_addrs - populate buffer addresses based on * mmu, fb, and format found in the fb * @aspace: address space pointer * @fb: framebuffer pointer @@ -41,9 +41,13 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats, * Return: error code on failure, -EAGAIN if success but the addresses * are the same as before or 0 if new addresses were populated */ -int dpu_format_populate_layout( +int dpu_format_populate_addrs( struct msm_gem_address_space *aspace, struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *fmtl); +int dpu_format_populate_plane_sizes( + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout); + #endif /*_DPU_FORMATS_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 241c2d7a218a..8191282b8819 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -674,10 +674,19 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, } } + ret = dpu_format_populate_plane_sizes(new_state->fb, &pstate->layout); + if (ret) { + DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); + if (pstate->aspace) + msm_framebuffer_cleanup(new_state->fb, pstate->aspace, + pstate->needs_dirtyfb); + return ret; + } + /* validate framebuffer layout before commit */ - ret = dpu_format_populate_layout(pstate->aspace, - new_state->fb, - &pstate->layout); + ret = dpu_format_populate_addrs(pstate->aspace, + new_state->fb, + &pstate->layout); if (ret) { DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); 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a=openpgp-sha256; l=6500; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=qX2/vlKkitTc/3eHEtcQg+VzMmr91mJSwt7zTMIK2v0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbwP+C8Kgs2yJXNSVMG5XxxthJCfV/2LqRY4 XR+FA5VIHiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG8AAKCRCLPIo+Aiko 1bkuB/0azRQzUUAJKmL7Pp/O+zBzpDN7D4xgBbW1LWy9yRjB/kNTRpF0VNVIl6fJ4d+7hYnt4ur 2lXVT2rxKrsg5LHM/cg0p70r4xKhLBf+2O/U+jUfONVkpJ+Ofl6YKwQdMFYNmZRHp9mwI4vL1Cn 4CWL1TNewA2UQobpkoyEuSJGQp1g4I4+TQ9lYnEBwUTaal8Fm1fqy53zPJlaOeN241qM/CbUGwH D7VMx8lzr45oGsuS39AnK8yHVFiqgnfzJWPjdJZ8OoqcEtqKeBrnQiabPJC2newYC1eEBQrBavX nmqf+bRXr15wZKktvGPy6UBvssktFQJjdRkc8xBBOT/I6t7j X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The function msm_framebuffer_iova() can not fail, it always returns a valid address. Drop the useless checks (that were already performed at the time) and make dpu_format_populate_addrs() return void. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 62 +++++----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 10 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 ++--- 4 files changed, 21 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index d8e37400d852..fcd5a073e2b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -590,11 +590,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc return; } - ret = dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest); - if (ret) { - DPU_DEBUG("failed to populate layout %d\n", ret); - return; - } + dpu_format_populate_addrs(aspace, job->fb, &wb_cfg->dest); wb_cfg->dest.width = job->fb->width; wb_cfg->dest.height = job->fb->height; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index abe3a1c0e409..095bb947f1ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -277,25 +277,15 @@ int dpu_format_populate_plane_sizes( return _dpu_format_populate_plane_sizes_linear(fmt, fb, layout); } -static int _dpu_format_populate_addrs_ubwc( - struct msm_gem_address_space *aspace, - struct drm_framebuffer *fb, - struct dpu_hw_fmt_layout *layout) +static void _dpu_format_populate_addrs_ubwc(struct msm_gem_address_space *aspace, + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout) { const struct msm_format *fmt; uint32_t base_addr = 0; bool meta; - if (!fb || !layout) { - DRM_ERROR("invalid pointers\n"); - return -EINVAL; - } - base_addr = msm_framebuffer_iova(fb, aspace, 0); - if (!base_addr) { - DRM_ERROR("failed to retrieve base addr\n"); - return -EFAULT; - } fmt = msm_framebuffer_format(fb); meta = MSM_FORMAT_IS_UBWC(fmt); @@ -330,7 +320,7 @@ static int _dpu_format_populate_addrs_ubwc( + layout->plane_size[2] + layout->plane_size[3]; if (!meta) - return 0; + return; /* configure Y metadata plane */ layout->plane_addr[2] = base_addr; @@ -361,60 +351,36 @@ static int _dpu_format_populate_addrs_ubwc( layout->plane_addr[1] = 0; if (!meta) - return 0; + return; layout->plane_addr[2] = base_addr; layout->plane_addr[3] = 0; } - return 0; } -static int _dpu_format_populate_addrs_linear( - struct msm_gem_address_space *aspace, - struct drm_framebuffer *fb, - struct dpu_hw_fmt_layout *layout) +static void _dpu_format_populate_addrs_linear(struct msm_gem_address_space *aspace, + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout) { unsigned int i; /* Populate addresses for simple formats here */ - for (i = 0; i < layout->num_planes; ++i) { + for (i = 0; i < layout->num_planes; ++i) layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i); - if (!layout->plane_addr[i]) { - DRM_ERROR("failed to retrieve base addr\n"); - return -EFAULT; - } - } - - return 0; } -int dpu_format_populate_addrs( - struct msm_gem_address_space *aspace, - struct drm_framebuffer *fb, - struct dpu_hw_fmt_layout *layout) +void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout) { const struct msm_format *fmt; - int ret; - - if (!fb || !layout) { - DRM_ERROR("invalid arguments\n"); - return -EINVAL; - } - - if ((fb->width > DPU_MAX_IMG_WIDTH) || - (fb->height > DPU_MAX_IMG_HEIGHT)) { - DRM_ERROR("image dimensions outside max range\n"); - return -ERANGE; - } fmt = msm_framebuffer_format(fb); /* Populate the addresses given the fb */ if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt)) - ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout); + _dpu_format_populate_addrs_ubwc(aspace, fb, layout); else - ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); - - return ret; + _dpu_format_populate_addrs_linear(aspace, fb, layout); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h index 2f2bff14c0db..256ca25c37a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h @@ -37,14 +37,10 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats, * @aspace: address space pointer * @fb: framebuffer pointer * @fmtl: format layout structure to populate - * - * Return: error code on failure, -EAGAIN if success but the addresses - * are the same as before or 0 if new addresses were populated */ -int dpu_format_populate_addrs( - struct msm_gem_address_space *aspace, - struct drm_framebuffer *fb, - struct dpu_hw_fmt_layout *fmtl); +void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, + struct drm_framebuffer *fb, + struct dpu_hw_fmt_layout *layout); int dpu_format_populate_plane_sizes( struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8191282b8819..1431ea753a4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -683,17 +683,9 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, return ret; } - /* validate framebuffer layout before commit */ - ret = dpu_format_populate_addrs(pstate->aspace, - new_state->fb, - &pstate->layout); - if (ret) { - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - if (pstate->aspace) - msm_framebuffer_cleanup(new_state->fb, pstate->aspace, - pstate->needs_dirtyfb); - return ret; - } + dpu_format_populate_addrs(pstate->aspace, + new_state->fb, + &pstate->layout); return 0; } From patchwork Mon Jun 24 14:47:19 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=3077; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=KA3D+m/a7g73ZaHa7e8wf9n+neLVMHpRovLAs28rnZU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbwdB+x33XFTd68Bqk8Qd+8V4zPpzKguQLAR TFcquTWZnaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG8AAKCRCLPIo+Aiko 1eSSCACG2Aiq6eqYvlJ1pnYozr1SXoRLqOGO1q+bShx1C6vjZbh5Z6y/wdiF3rAyoipMEGmQ/vD sUh5RW+GxShGjICYW8qelvlGt/5a3fGm9mhT0WDtagmkRIdqG5jLlx4LrYbfVAM0IyHmy8Voszr rgIAFFs6yXy+V3Z1tI28DUiqJ3UqSWDrM3kq3hjgJ9LG0sotymjdR3Zxid6fa9kG96sQP+1h9Dx qxM7Ctl05l0P8DMGILbqqs0MRkc0kOq2MsK/+3P3ZOcniLw2MhTHI9YYlhWWTvvSl5+rfw9b0Pl 8wDXuRZwpH1GqKEO0CIBriNoesdaxCOm+vtBXBp0ITPo+jc/ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Move the call to dpu_format_populate_plane_sizes() to the atomic_check step, so that any issues with the FB layout can be reported as early as possible. At the same time move the call to dpu_format_populate_addrs() to dpu_plane_sspp_atomic_update(). This way the all layout management is performed only for the visible planes: the .prepare_fb callback is called for not visible planes too, so keeping dpu_format_populate_addrs in dpu_plane_prepare_fb() will require dpu_format_populate_plane_sizes() to be called for !visible planes too. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 1431ea753a4f..a309b06b0992 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -674,19 +674,6 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane, } } - ret = dpu_format_populate_plane_sizes(new_state->fb, &pstate->layout); - if (ret) { - DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); - if (pstate->aspace) - msm_framebuffer_cleanup(new_state->fb, pstate->aspace, - pstate->needs_dirtyfb); - return ret; - } - - dpu_format_populate_addrs(pstate->aspace, - new_state->fb, - &pstate->layout); - return 0; } @@ -863,6 +850,12 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } + ret = dpu_format_populate_plane_sizes(new_plane_state->fb, &pstate->layout); + if (ret) { + DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret); + return ret; + } + fmt = msm_framebuffer_format(new_plane_state->fb); max_linewidth = pdpu->catalog->caps->max_linewidth; @@ -1090,7 +1083,8 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, _dpu_plane_set_qos_remap(plane, pipe); } -static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +static void dpu_plane_sspp_atomic_update(struct drm_plane *plane, + struct drm_plane_state *new_state) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; @@ -1111,6 +1105,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); pdpu->is_rt_pipe = is_rt_pipe; + dpu_format_populate_addrs(pstate->aspace, new_state->fb, &pstate->layout); + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), crtc->base.id, DRM_RECT_ARG(&state->dst), @@ -1175,7 +1171,7 @@ static void dpu_plane_atomic_update(struct drm_plane *plane, if (!new_state->visible) { _dpu_plane_atomic_disable(plane); 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Mon, 24 Jun 2024 07:47:23 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:20 +0300 Subject: [PATCH v4 14/16] drm/msm/dpu: check for the plane pitch overflow Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-14-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1824; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=+RF/P7K64SGg/tQu4deWbHOf+YbNZCIL5VEgg9w8tfc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbwypWamkbFYHq9xCHZcfNfWOlbHlrnsCxGg bTNoVOgA+iJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG8AAKCRCLPIo+Aiko 1Xz0B/9Z9dIa7gvw1tz29gjmfw9mynEEq6c75eE8Dl0jOAaIhdd8r3QXg4E4UWFWzxN/fhoglZR 795Au+mAhB/wRq4ARHBsaMjO+WTy4/ct5d9viewJWN699MF3NAmaTCDe7UQTYu6jHdmT49CEJ50 ebg5FcWkDU7LwibB/zomy9M2ZetfyXaCjHCBSvRDbW8uWZRMCwIK5zYnbOHpKP+dIlK4m6CN8ET +MoZMA6BuJBhpV9j2Xdnq3pOD9Lg+xfzjF0EJlskA8r1L063Fg/8Eoydk13Rcklc4MMxcNI1Sv8 LaZMXZRy9IwxdldlYXdU6okAgekN04HAmLheULbvg3JIXHDL X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Check that the plane pitch doesn't overflow the maximum pitch size allowed by the hardware. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 4a910b808687..8998d1862e16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -12,6 +12,8 @@ struct dpu_hw_sspp; +#define DPU_SSPP_MAX_PITCH_SIZE 0xffff + /** * Flags */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index a309b06b0992..a629eb3a6436 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -782,7 +782,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); - int ret = 0, min_scale; + int i, ret = 0, min_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; @@ -856,6 +856,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return ret; } + for (i = 0; i < pstate->layout.num_planes; i++) + if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) + return -E2BIG; + fmt = msm_framebuffer_format(new_plane_state->fb); max_linewidth = pdpu->catalog->caps->max_linewidth; From patchwork Mon Jun 24 14:47:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13709652 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88D61A01CA for ; Mon, 24 Jun 2024 14:47:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Merge these constants to remove duplication. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 095bb947f1ff..b0909cbd91cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -13,9 +13,6 @@ #define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096 -#define DPU_MAX_IMG_WIDTH 0x3FFF -#define DPU_MAX_IMG_HEIGHT 0x3FFF - /* * struct dpu_media_color_map - maps drm format to media format * @format: DRM base pixel format diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20..34e60483fbcf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -21,8 +21,8 @@ #define DPU_HW_BLK_NAME_LEN 16 -#define MAX_IMG_WIDTH 0x3fff -#define MAX_IMG_HEIGHT 0x3fff +#define DPU_MAX_IMG_WIDTH 0x3fff +#define DPU_MAX_IMG_HEIGHT 0x3fff #define CRTC_DUAL_MIXERS 2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index a629eb3a6436..4712aa6f7929 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -843,8 +843,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, fb_rect.y2 = new_plane_state->fb->height; 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Mon, 24 Jun 2024 07:47:24 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ce88b0119sm212699e87.222.2024.06.24.07.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:47:24 -0700 (PDT) From: Dmitry Baryshkov Date: Mon, 24 Jun 2024 17:47:22 +0300 Subject: [PATCH v4 16/16] drm/msm/dpu: sync mode_config limits to the FB limits in dpu_plane.c Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240624-dpu-mode-config-width-v4-16-1038c13da3a5@linaro.org> References: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> In-Reply-To: <20240624-dpu-mode-config-width-v4-0-1038c13da3a5@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2549; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=N3YZKN6loeIt7zXSx7uKEpsl5ti+ONaIe5A6G3FjkBU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmeYbxG1j08vEex/AL+/BKNEehGKP1/V7s07UNY 2qFA6lUUwaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZnmG8QAKCRCLPIo+Aiko 1cesB/9YdDl3hmZOd1LdElWwNw3tnumm7aoxG3qajMAgQoVZG9l5Af7/QSMFT5rJeg24+eT2xRR KwiOITmSJtgIX08d/mALiMq1UPSBaWRGRpT8Y+Lmtwd+lHH7HuDJbpLpQIkPjVswji7eNhr6Gyc f9qNh7lnuE+QWuockHzCMI3jGHfE7/TwlUq/G0gFzkREVIk6zILia3bs+obsGcVGsb+zogmvigQ JL5Ejw7z4DpQaBrXacCmVTY0UuFLgxxZzxTe61tuxhCuK1vZhs/d4/4KTGoU217byGDcQrKxxWQ f3WpUuRAT69uS7x/Z7Bs7Gvq78qbrbHJ2PTeeehDjzxL/aNw X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Lift mode_config limits set by the DPU driver to the actual FB limits as handled by the dpu_plane.c. Move 2*max_lm_width check where it belongs, to the drm_crtc_helper_funcs::mode_valid() callback. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 15 +++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 ++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 2a87dd7188b8..f4ec3df45536 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1235,6 +1235,20 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return 0; } +static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); + + /* + * max crtc width is equal to the max mixer width * 2 and max height is + * is 4K + */ + return drm_mode_validate_size(mode, + 2 * dpu_kms->catalog->caps->max_mixer_width, + 4096); +} + int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); @@ -1450,6 +1464,7 @@ static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { .atomic_check = dpu_crtc_atomic_check, .atomic_begin = dpu_crtc_atomic_begin, .atomic_flush = dpu_crtc_atomic_flush, + .mode_valid = dpu_crtc_mode_valid, .get_scanout_position = dpu_crtc_get_scanout_position, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 40e4b829b9da..1c86f22859fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1191,13 +1191,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; - /* - * max crtc width is equal to the max mixer width * 2 and max height is - * is 4K - */ - dev->mode_config.max_width = - dpu_kms->catalog->caps->max_mixer_width * 2; - dev->mode_config.max_height = 4096; + dev->mode_config.max_width = DPU_MAX_IMG_WIDTH; + dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT; dev->max_vblank_count = 0xffffffff; /* Disable vblank irqs aggressively for power-saving */