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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?l5+bOXbMg5FLDHtaw69tZZg7FY9F?= =?utf-8?q?N53NjsQJ1sbjG8P0JA+NA07zGWGFXoE8lw+kiou5u3M9T7vVSO0kW5wsvNAgWldHy?= =?utf-8?q?zX19nx69zeR9RQG4l4IAXqpPNyTMI7TP77ocwcCLNCPWNTSuPm9uJywQMMflgGzr8?= =?utf-8?q?I3YeWq2P7TD2xS+fXKT5g8XWQirUwfaqETF/IRqOiAsDegEEvQDX6+ys3ta8ZIue5?= =?utf-8?q?SCS67v2vOI0GEh9V+fYLYgL6hQLwawNh2Q730ZCdTwKkEIpf3xHFZdZOFli5C1j0A?= =?utf-8?q?uVnz4YQ78JAfmpyOGzvNpV+yjLkJIv/07kkpv1/S7wEpru4ek56G47lH4zx64U77Q?= =?utf-8?q?cvizcR0nyUKGFrPyKGd29w23Rwz8UzmeMgMds5DBkoA3cwdqJouPD/0STKkMWDWzX?= =?utf-8?q?V5NBO8E9MCyTh7eEMHOEGrEi10mLe23+B4tX/zdIbETche+sBfXVZdD273svYsz2u?= =?utf-8?q?Ur3xqqRdZ1MUZPUVd+ctR3NpUQnzaqe+9bDhSjOY4JhQJHzdcJaOZrbbrA7fsk3dv?= =?utf-8?q?SLKgiaeEfSfGgu2MLHObM5uqpHGo56YNoQBn4TLQQQvmWpRF4RXfexUjqPPiVGg/Y?= =?utf-8?q?jieo/k87kCyBAHhUgZgGNdW5uts+OewH16XAjQfLDmV5bwjlgbPw8V7KeF1Rf8AQ1?= =?utf-8?q?BdgHjy2pK04RpEzS0rB3DFJ+9rdcoD9Ppo62RUil3IQorsONTIT5L+vEEZT0dM+YQ?= =?utf-8?q?upWx7JFEPzqJsjSqNduGERKUEhdaS0aIehT/I7UfueJrlKg5rnr5tAlcnXI1jWqpE?= =?utf-8?q?/S4WD5HcoVW8oJ7EbtcMY6gvfRvl2skd9IefyipsAVBzzehXQ4w4feQM6Y9BYXVbH?= =?utf-8?q?FwkaYpzQUOAAMl5/TWkMR6xRYE0NuHTxDt1bzLAJLzZDaR/fMpXRmvsws8qQY+NV5?= =?utf-8?q?ihc4PLRUDSU7uAQhB47ZGAxh69ZDmNTmnG9CG+3kG5s2an2mUz7EyoUcuhBF8AHvY?= =?utf-8?q?EeCYu+LYnEkt+IG3JhVdE9Sht9W4gu+zLJ43WN1fEERuGSQncYwa/uaC5vb8wbd8F?= =?utf-8?q?ylel6QNm5/2sokl6Xg9Q7VZANj2Axok4HsRG5js4/a4st+uzdWcsxlEkgvQWEDsOG?= =?utf-8?q?6r+dfJCVFB/XB5HIKakpR96/qWM88aL+GXp5nfDyhyjF414PlZ++o3BrnxfzbSnA7?= =?utf-8?q?rGzvqk330UOljjQVNtD6D9uNfkjullcy1owHEqqlDgFWe5W11JMd97m6QmB7Qepgl?= =?utf-8?q?YvesS7RpOoJC+jrgQUE8XhU3cBgfXfKTAfLWmd2iKiNPeXpE8riVzG9jNuy5tb080?= =?utf-8?q?m9atGLGYVRzUXQgLRlBoOHOj6P0CE6PZERotcHmPML13jbbobLjP7bhH/89b/Ns4X?= =?utf-8?q?PER9KeaQACV7xzx3QwAq847s6BJKwyFd8yjUrE4to2F5y1RC0gTak6kL3kYA/GZZi?= =?utf-8?q?gUaS3Hk7jEpTHcg9A3APfSQY8r3++GTG4VaUKHUv9azyukniHf5COXWJLw8MBl9j0?= =?utf-8?q?EOS5749TCCTt/oKpib5tiY85GgcY0yC8FEg3J2/2ECDOxTkeA8X69KBnIvK349UC4?= =?utf-8?q?RzoPtzUKPNXwndQHG5iQkssZ6LkClwYkkA=3D=3D?= X-OriginatorOrg: siemens.com X-MS-Exchange-CrossTenant-Network-Message-Id: a027360a-94cd-4285-ca5c-08dc9563a842 X-MS-Exchange-CrossTenant-AuthSource: AS4PR10MB6181.EURPRD10.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jun 2024 22:10:43.7736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 38ae3bcd-9579-4fd4-adda-b42e1495d55a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MSOb1CUYH8OR0K9RvRXbppTw0lln1vzTMSK/L+AO/3lHTmV5p/+xBFHS8OsMX5IEtCJmIL0oZdWbvn+P0qEMiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR10MB3631 From: Kishon Vijay Abraham I Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 Bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Achal Verma Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ Signed-off-by: Vignesh Raghavendra Signed-off-by: Jan Kiszka --- Needed for the IOT2050 PG1 variants. Pending downstream way too long. drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..a04f1087ce91 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -562,6 +578,32 @@ static void ks_pcie_quirk(struct pci_dev *dev) pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 Bytes. Force the MRRS to + * 128 Bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);