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Wed, 26 Jun 2024 06:07:37 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Jun 2024 23:07:36 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mao Jinlong , "Alexander Shishkin" CC: , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , songchai Subject: [PATCH v3 1/3] dt-bindings: arm: Add arm,trace-id for coresight dummy source Date: Tue, 25 Jun 2024 23:07:20 -0700 Message-ID: <20240626060724.28862-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240626060724.28862-1-quic_jinlmao@quicinc.com> References: <20240626060724.28862-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gD_QM8X70ckGaL-NC8nCUVIWwDSdj0c5 X-Proofpoint-ORIG-GUID: gD_QM8X70ckGaL-NC8nCUVIWwDSdj0c5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_03,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=821 bulkscore=0 phishscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260046 Some dummy source HW has static trace id which cannot be changed via software programming. Add arm,trace-id for static id support to coresight dummy source. Signed-off-by: Mao Jinlong Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/arm/arm,coresight-dummy-source.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml index 6745b4cc8f1c..b18cfd8e137e 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml @@ -38,6 +38,12 @@ properties: enum: - arm,coresight-dummy-source + arm,trace-id: + description: If dummy source needs static id support, use this to set trace id. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 111 + out-ports: $ref: /schemas/graph.yaml#/properties/ports From patchwork Wed Jun 26 06:07:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13712324 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E80914A61E; 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Wed, 26 Jun 2024 06:07:38 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45Q67bGQ006880 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 06:07:37 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Jun 2024 23:07:37 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mao Jinlong , "Alexander Shishkin" CC: , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , songchai Subject: [PATCH v3 2/3] coresight: Add support to get preferred id for system trace sources Date: Tue, 25 Jun 2024 23:07:21 -0700 Message-ID: <20240626060724.28862-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240626060724.28862-1-quic_jinlmao@quicinc.com> References: <20240626060724.28862-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pFEpNPn-FcGPcr5vUQuA8T455m8S3wNT X-Proofpoint-ORIG-GUID: pFEpNPn-FcGPcr5vUQuA8T455m8S3wNT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_03,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 phishscore=0 adultscore=0 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260046 Dynamic trace id was introduced in coresight subsystem, so trace id is allocated dynamically. However, some hardware ATB source has static trace id and it cannot be changed via software programming. For such source, it can call coresight_get_source_traceid to get the fixed trace id from device node and pass id to coresight_trace_id_get_system_id to reserve the id. Signed-off-by: Mao Jinlong --- .../hwtracing/coresight/coresight-platform.c | 25 +++++++++++++ drivers/hwtracing/coresight/coresight-stm.c | 2 +- drivers/hwtracing/coresight/coresight-tpda.c | 2 +- .../hwtracing/coresight/coresight-trace-id.c | 35 ++++++++++++------- .../hwtracing/coresight/coresight-trace-id.h | 11 +++++- include/linux/coresight.h | 1 + 6 files changed, 61 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 9d550f5697fa..df169f3f367e 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -183,6 +183,17 @@ static int of_coresight_get_cpu(struct device *dev) return cpu; } +/* + * of_coresight_get_trace_id: Get the atid of a source device. + * + * Returns 0 on success. + */ +static int of_coresight_get_trace_id(struct device *dev, u32 *id) +{ + + return of_property_read_u32(dev->of_node, "arm,trace-id", id); +} + /* * of_coresight_parse_endpoint : Parse the given output endpoint @ep * and fill the connection information in @pdata->out_conns @@ -315,6 +326,11 @@ static inline int of_coresight_get_cpu(struct device *dev) { return -ENODEV; } + +static inline int of_coresight_get_trace_id(struct device *dev, u32 *id) +{ + return -ENODEV; +} #endif #ifdef CONFIG_ACPI @@ -794,6 +810,15 @@ int coresight_get_cpu(struct device *dev) } EXPORT_SYMBOL_GPL(coresight_get_cpu); +int coresight_get_source_traceid(struct device *dev, u32 *id) +{ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + return of_coresight_get_trace_id(dev, id); +} +EXPORT_SYMBOL_GPL(coresight_get_source_traceid); + struct coresight_platform_data * coresight_get_platform_data(struct device *dev) { diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index e1c62820dfda..34fab2ce9a76 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -901,7 +901,7 @@ static int __stm_probe(struct device *dev, struct resource *res) goto stm_unregister; } - trace_id = coresight_trace_id_get_system_id(); + trace_id = coresight_trace_id_get_system_id(TRACE_ID_ANY); if (trace_id < 0) { ret = trace_id; goto cs_unregister; diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 7739bc7adc44..46161cadb9e5 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -251,7 +251,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata) * same trace-id. When TPDA does packetization, different * port will have unique channel number for decoding. */ - atid = coresight_trace_id_get_system_id(); + atid = coresight_trace_id_get_system_id(TRACE_ID_ANY); if (atid < 0) return atid; diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c index af5b4ef59cea..59194f60362c 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -75,21 +75,26 @@ static int coresight_trace_id_find_odd_id(struct coresight_trace_id_map *id_map) * Allocate new ID and set in use * * if @preferred_id is a valid id then try to use that value if available. - * if @preferred_id is not valid and @prefer_odd_id is true, try for odd id. + * if TRACE_ID_WANT_PREFERRED is set, @preferred_id must be free, otherwise return + * error -EINVAL. + * if @preferred_id is not valid and TRACE_ID_WANT_ODD is true, try for odd id. * * Otherwise allocate next available ID. */ static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map, - int preferred_id, bool prefer_odd_id) + int preferred_id, unsigned int flags) { int id = 0; /* for backwards compatibility, cpu IDs may use preferred value */ - if (IS_VALID_CS_TRACE_ID(preferred_id) && - !test_bit(preferred_id, id_map->used_ids)) { - id = preferred_id; - goto trace_id_allocated; - } else if (prefer_odd_id) { + if (IS_VALID_CS_TRACE_ID(preferred_id)) { + if (!test_bit(preferred_id, id_map->used_ids)) { + id = preferred_id; + goto trace_id_allocated; + } else if (WARN((flags & TRACE_ID_WANT_PREFERRED), "Trace ID %d is used.\n", + preferred_id)) + return -EINVAL; + } else if (flags & TRACE_ID_WANT_ODD) { /* may use odd ids to avoid preferred legacy cpu IDs */ id = coresight_trace_id_find_odd_id(id_map); if (id) @@ -175,7 +180,7 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_ */ id = coresight_trace_id_alloc_new_id(id_map, CORESIGHT_LEGACY_CPU_TRACE_ID(cpu), - false); + TRACE_ID_ANY); if (!IS_VALID_CS_TRACE_ID(id)) goto get_cpu_id_out_unlock; @@ -222,14 +227,20 @@ static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id DUMP_ID_MAP(id_map); } -static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) +static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map, + int preferred_id) { unsigned long flags; int id; + unsigned int traceid_flags = 0; spin_lock_irqsave(&id_map_lock, flags); + /* prefer odd IDs for system components to avoid legacy CPU IDS */ - id = coresight_trace_id_alloc_new_id(id_map, 0, true); + traceid_flags = TRACE_ID_WANT_ODD; + traceid_flags |= preferred_id > 0 ? TRACE_ID_WANT_PREFERRED : 0; + + id = coresight_trace_id_alloc_new_id(id_map, preferred_id, traceid_flags); spin_unlock_irqrestore(&id_map_lock, flags); DUMP_ID(id); @@ -269,9 +280,9 @@ int coresight_trace_id_read_cpu_id(int cpu) } EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); -int coresight_trace_id_get_system_id(void) +int coresight_trace_id_get_system_id(int id) { - return coresight_trace_id_map_get_system_id(&id_map_default); + return coresight_trace_id_map_get_system_id(&id_map_default, id); } EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h index 3797777d367e..a236cf87c169 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.h +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -61,6 +61,12 @@ struct coresight_trace_id_map { DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); }; +enum trace_id_flags { + TRACE_ID_ANY = 0x0, + TRACE_ID_WANT_ODD = 0x1, + TRACE_ID_WANT_PREFERRED = 0x2, +}; + /* Allocate and release IDs for a single default trace ID map */ /** @@ -118,9 +124,12 @@ int coresight_trace_id_read_cpu_id(int cpu); * * Used to allocate IDs for system trace sources such as STM. * + * @id: Preferred id value. If id is TRACE_ID_ANY, get a free id from id map. + * If id is greater than TRACE_ID_ANY, get a preferred id. + * * return: Trace ID or -EINVAL if allocation is impossible. */ -int coresight_trace_id_get_system_id(void); +int coresight_trace_id_get_system_id(int id); /** * Release an allocated system trace ID. diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f09ace92176e..0599303be326 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -643,6 +643,7 @@ void coresight_relaxed_write64(struct coresight_device *csdev, void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); extern int coresight_get_cpu(struct device *dev); +extern int coresight_get_source_traceid(struct device *dev, u32 *id); struct coresight_platform_data *coresight_get_platform_data(struct device *dev); struct coresight_connection * From patchwork Wed Jun 26 06:07:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mao Jinlong X-Patchwork-Id: 13712325 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3E6914D458; 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Wed, 26 Jun 2024 06:07:38 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45Q67b7M031741 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 06:07:37 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Jun 2024 23:07:37 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mao Jinlong , "Alexander Shishkin" CC: , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , songchai Subject: [PATCH v3 3/3] coresight: dummy: Add reserve atid support for dummy source Date: Tue, 25 Jun 2024 23:07:22 -0700 Message-ID: <20240626060724.28862-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240626060724.28862-1-quic_jinlmao@quicinc.com> References: <20240626060724.28862-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 83P1BVmXosURPGaT7_ELyW2CNm31sSDl X-Proofpoint-GUID: 83P1BVmXosURPGaT7_ELyW2CNm31sSDl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_03,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260046 Some dummy source has static trace id configured in HW and it cannot be changed via software programming. Configure the trace id in device tree and reserve the id when device probe. Signed-off-by: Mao Jinlong --- .../sysfs-bus-coresight-devices-dummy-source | 15 +++++ drivers/hwtracing/coresight/coresight-dummy.c | 59 +++++++++++++++++-- 2 files changed, 70 insertions(+), 4 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source new file mode 100644 index 000000000000..dff31c304b5b --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source @@ -0,0 +1,15 @@ +What: /sys/bus/coresight/devices/dummy_source/enable_source +Date: June 2024 +KernelVersion: 6.9 +Contact: Mao Jinlong +Description: (RW) Enable/disable tracing of dummy source. A sink should be activated + before enabling the source. The path of coresight components linking + the source to the sink is configured and managed automatically by the + coresight framework. + +What: /sys/bus/coresight/devices/dummy_source/traceid +Date: June 2024 +KernelVersion: 6.9 +Contact: Mao Jinlong +Description: (R) Show the trace ID that will appear in the trace stream + coming from this trace entity. diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c index ac70c0b491be..5bff3baae1b5 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -11,10 +11,12 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" struct dummy_drvdata { struct device *dev; struct coresight_device *csdev; + u8 traceid; }; DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); @@ -67,6 +69,32 @@ static const struct coresight_ops dummy_sink_cs_ops = { .sink_ops = &dummy_sink_ops, }; +/* User can get the trace id of dummy source from this node. */ +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct dummy_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->traceid; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + +static struct attribute *coresight_dummy_attrs[] = { + &dev_attr_traceid.attr, + NULL, +}; + +static const struct attribute_group coresight_dummy_group = { + .attrs = coresight_dummy_attrs, +}; + +static const struct attribute_group *coresight_dummy_groups[] = { + &coresight_dummy_group, + NULL, +}; + static int dummy_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -74,6 +102,11 @@ static int dummy_probe(struct platform_device *pdev) struct coresight_platform_data *pdata; struct dummy_drvdata *drvdata; struct coresight_desc desc = { 0 }; + int ret, trace_id; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; if (of_device_is_compatible(node, "arm,coresight-dummy-source")) { @@ -85,6 +118,25 @@ static int dummy_probe(struct platform_device *pdev) desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; desc.ops = &dummy_source_cs_ops; + desc.groups = coresight_dummy_groups; + + ret = coresight_get_source_traceid(dev, &trace_id); + if (!ret) { + /* Get the preferred id if id is set in device tree. */ + ret = coresight_trace_id_get_system_id(trace_id); + if (ret < 0) + return ret; + + } else { + /* Get next available id if id is not set in device tree. */ + trace_id = coresight_trace_id_get_system_id(TRACE_ID_ANY); + if (trace_id < 0) { + ret = trace_id; + return ret; + } + } + drvdata->traceid = (u8)trace_id; + } else if (of_device_is_compatible(node, "arm,coresight-dummy-sink")) { desc.name = coresight_alloc_device_name(&sink_devs, dev); if (!desc.name) @@ -103,10 +155,6 @@ static int dummy_probe(struct platform_device *pdev) return PTR_ERR(pdata); pdev->dev.platform_data = pdata; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) - return -ENOMEM; - drvdata->dev = &pdev->dev; platform_set_drvdata(pdev, drvdata); @@ -126,7 +174,10 @@ static void dummy_remove(struct platform_device *pdev) { struct dummy_drvdata *drvdata = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + if (of_device_is_compatible(node, "arm,coresight-dummy-source")) + coresight_trace_id_put_system_id(drvdata->traceid); pm_runtime_disable(dev); coresight_unregister(drvdata->csdev); }