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Wed, 26 Jun 2024 03:26:47 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:37 +0300 Subject: [PATCH vhost v2 01/24] vdpa/mlx5: Clarify meaning thorough function rename Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-1-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C8:EE_|SJ2PR12MB9190:EE_ X-MS-Office365-Filtering-Correlation-Id: 935bdde2-4d71-4c42-1e46-08dc95ca88db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?yA0Z8VobTA5xT8uAUxWOTQyn1mqQcTP?= =?utf-8?q?T/pSrlR1uUJCisSgUctHmjfDpbs8joIxguBGQ/QxTazJMOd13MH3BiDm+H+5pMN22?= =?utf-8?q?exfLY5UMSn5gzl+vGOoDkEmaa6DiBXmoWF3IA5aDd73iLMyuy49mFER9NPO6SgVUS?= =?utf-8?q?B/ZZWFfIe6QhzyRagNM8iJimz/S8fsgCHkHK561lAl09VHX3DHft4DsJ7jsCqVes1?= =?utf-8?q?YUpcRgKeZpDZ4nFaBcgsLQVb9A2Z4vK5dRTRfFY+sjUPA3jVklSY/daPf1p3jEQIQ?= =?utf-8?q?QNj0WlVQLPF0mZjbHtNFqRv9UW8lRBakTU1FfhMLp2h669uhm/EEI3xaO7KIbXh5b?= =?utf-8?q?QuPJwB59PJmm5McQ7Fm0qak2JZEVDW2o1vVcXFmxDuy/dupd7Y8m7f4k5zfte5uP4?= =?utf-8?q?VXJdt6DQ/cfNHh4LhV4wRVnTfUDQ5herVU5ptj5jhyw/mmhaPe4eLb85y6b6fbpi5?= =?utf-8?q?VByOKI9m0uiMVa+OhrQt46ioViaakUAmcoLtF5gL4JkD7ZvCWwAkawGaVQRwCkvcV?= =?utf-8?q?A//5ai847FAbmSqM/ue0bVOMvenx8e1IMXQh4o95RbrnYeiUwqjajJiZQnlCMMD1q?= =?utf-8?q?Gd3ta8fGPdJl/LiC5czKR1MpZ8WnNFkrGEc417PV9RC2QuY8Je9crkVfFPXsVHaU1?= =?utf-8?q?qK1xrmh+ITbZUPaW+yFX7qGRusZTyLbNQOVKmsM7YO7g6WQMaY8rWze0SQ5Sx8UAq?= =?utf-8?q?VWg409s1ELt/upgvZ2wtHBgXg4pahaXdlvcwdxGbaUJxder6OFz3xh8mRb45Pttd+?= =?utf-8?q?3sh3bl52eHdVzjjC2Bf3o3wtLwEHjGu/iltXOEfIXDvt7a/aY0DqM1oBE6qP0sQgC?= =?utf-8?q?wSGwu9MIP1ikHJr7VBrCTCjYZv8v1w2pg19/LwDFyCLoZrvY/2duKJBeRqPAN2tPo?= =?utf-8?q?DnAC2prXxrvZFOHZ35lYQ3bIAyCBueKe+XrbpzUtA/I+RAewE77W+AcFk5UNDF0GN?= =?utf-8?q?GKNv4k97lG9wDM2JT1dMIUSUKg4cDPzS01XqYAkML4YRc4l7vHMWH8mItEVTkQett?= =?utf-8?q?LYlmwqrapPjDx9odRhzEWioUwhZusTKq+5KbpmxZeEBC0HJgX+6yi0vvwy09oy7yk?= =?utf-8?q?G+JNe2bTzyjQ1QewfZHr4aWYRhAgSlB5u0fSdlR4AMKPDkjTNGmAZELku5PMAUU/0?= =?utf-8?q?G2gW6+0G7qOc/WJfQXryp/gEj7fZ8OeXKD2N9TCyJpFRf8bFaXB8Y37znj99Z04pe?= =?utf-8?q?E9yTXagemURqyQ2NGsQ3a/DNWnpe8uXfbQdt18JB9MxSEgJJt2NCVmCzDVNWB1JGU?= =?utf-8?q?dr8z3YG0jORAH7u/iFKHBYsj29s0FeKrqWt6arI9uNYv0ElfZm827mfteM3n3U27R?= =?utf-8?q?aBpYMiEvF1RsM6BehZ0TVd2pXss1z0l+ag=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:09.0511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 935bdde2-4d71-4c42-1e46-08dc95ca88db X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9190 setup_driver()/teardown_driver() are a bit vague. These functions are used for virtqueue resources. Same for alloc_resources()/teardown_resources(): they represent fixed resources that are meant to exist during the device lifetime. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index ecfc16151d61..3422da0e344b 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -144,10 +144,10 @@ static bool is_index_valid(struct mlx5_vdpa_dev *mvdev, u16 idx) return idx <= mvdev->max_idx; } -static void free_resources(struct mlx5_vdpa_net *ndev); +static void free_fixed_resources(struct mlx5_vdpa_net *ndev); static void init_mvqs(struct mlx5_vdpa_net *ndev); -static int setup_driver(struct mlx5_vdpa_dev *mvdev); -static void teardown_driver(struct mlx5_vdpa_net *ndev); +static int setup_vq_resources(struct mlx5_vdpa_dev *mvdev); +static void teardown_vq_resources(struct mlx5_vdpa_net *ndev); static bool mlx5_vdpa_debug; @@ -2848,7 +2848,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, if (err) return err; - teardown_driver(ndev); + teardown_vq_resources(ndev); } mlx5_vdpa_update_mr(mvdev, new_mr, asid); @@ -2862,7 +2862,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, if (teardown) { restore_channels_info(ndev); - err = setup_driver(mvdev); + err = setup_vq_resources(mvdev); if (err) return err; } @@ -2873,7 +2873,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, } /* reslock must be held for this function */ -static int setup_driver(struct mlx5_vdpa_dev *mvdev) +static int setup_vq_resources(struct mlx5_vdpa_dev *mvdev) { struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); int err; @@ -2931,7 +2931,7 @@ static int setup_driver(struct mlx5_vdpa_dev *mvdev) } /* reslock must be held for this function */ -static void teardown_driver(struct mlx5_vdpa_net *ndev) +static void teardown_vq_resources(struct mlx5_vdpa_net *ndev) { WARN_ON(!rwsem_is_locked(&ndev->reslock)); @@ -2997,7 +2997,7 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); - err = setup_driver(mvdev); + err = setup_vq_resources(mvdev); if (err) { mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); goto err_driver; @@ -3040,7 +3040,7 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) down_write(&ndev->reslock); unregister_link_notifier(ndev); - teardown_driver(ndev); + teardown_vq_resources(ndev); clear_vqs_ready(ndev); if (flags & VDPA_RESET_F_CLEAN_MAP) mlx5_vdpa_destroy_mr_resources(&ndev->mvdev); @@ -3197,7 +3197,7 @@ static void mlx5_vdpa_free(struct vdpa_device *vdev) ndev = to_mlx5_vdpa_ndev(mvdev); - free_resources(ndev); + free_fixed_resources(ndev); mlx5_vdpa_destroy_mr_resources(mvdev); if (!is_zero_ether_addr(ndev->config.mac)) { pfmdev = pci_get_drvdata(pci_physfn(mvdev->mdev->pdev)); @@ -3467,7 +3467,7 @@ static int query_mtu(struct mlx5_core_dev *mdev, u16 *mtu) return 0; } -static int alloc_resources(struct mlx5_vdpa_net *ndev) +static int alloc_fixed_resources(struct mlx5_vdpa_net *ndev) { struct mlx5_vdpa_net_resources *res = &ndev->res; int err; @@ -3494,7 +3494,7 @@ static int alloc_resources(struct mlx5_vdpa_net *ndev) return err; } -static void free_resources(struct mlx5_vdpa_net *ndev) +static void free_fixed_resources(struct mlx5_vdpa_net *ndev) { struct mlx5_vdpa_net_resources *res = &ndev->res; @@ -3735,7 +3735,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, goto err_res; } - err = alloc_resources(ndev); + err = alloc_fixed_resources(ndev); if (err) goto err_mr; @@ -3758,7 +3758,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, err_reg: destroy_workqueue(mvdev->wq); err_res2: - free_resources(ndev); + free_fixed_resources(ndev); err_mr: mlx5_vdpa_destroy_mr_resources(mvdev); err_res: From patchwork Wed Jun 26 10:26:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712567 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2081.outbound.protection.outlook.com [40.107.237.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42A5A17DE02; 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Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 3422da0e344b..1ad281cbc541 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -146,7 +146,7 @@ static bool is_index_valid(struct mlx5_vdpa_dev *mvdev, u16 idx) static void free_fixed_resources(struct mlx5_vdpa_net *ndev); static void init_mvqs(struct mlx5_vdpa_net *ndev); -static int setup_vq_resources(struct mlx5_vdpa_dev *mvdev); +static int setup_vq_resources(struct mlx5_vdpa_net *ndev); static void teardown_vq_resources(struct mlx5_vdpa_net *ndev); static bool mlx5_vdpa_debug; @@ -2862,7 +2862,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, if (teardown) { restore_channels_info(ndev); - err = setup_vq_resources(mvdev); + err = setup_vq_resources(ndev); if (err) return err; } @@ -2873,9 +2873,9 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, } /* reslock must be held for this function */ -static int setup_vq_resources(struct mlx5_vdpa_dev *mvdev) +static int setup_vq_resources(struct mlx5_vdpa_net *ndev) { - struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + struct mlx5_vdpa_dev *mvdev = &ndev->mvdev; int err; WARN_ON(!rwsem_is_locked(&ndev->reslock)); @@ -2997,7 +2997,7 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); - err = setup_vq_resources(mvdev); + err = setup_vq_resources(ndev); if (err) { mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); goto err_driver; From patchwork Wed Jun 26 10:26:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712568 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2054.outbound.protection.outlook.com [40.107.96.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FD0B17B428; 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But (acde3929492b ("vdpa/mlx5: Use consistent RQT size") initialized all the queues in the first loop, so the second iteration in init_mvqs() is never called because the first one will iterate up to max_vqs. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 1ad281cbc541..b4d9ef4f66c8 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -3519,12 +3519,6 @@ static void init_mvqs(struct mlx5_vdpa_net *ndev) mvq->fwqp.fw = true; mvq->fw_state = MLX5_VIRTIO_NET_Q_OBJECT_NONE; } - for (; i < ndev->mvdev.max_vqs; i++) { - mvq = &ndev->vqs[i]; - memset(mvq, 0, offsetof(struct mlx5_vdpa_virtqueue, ri)); - mvq->index = i; - mvq->ndev = ndev; - } } struct mlx5_vdpa_mgmtdev { From patchwork Wed Jun 26 10:26:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712569 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2070.outbound.protection.outlook.com [40.107.101.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B81AF17F4FF; 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Reviewed-by: Cosmin Ratiu Reviewed-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index b4d9ef4f66c8..96782b34e2b2 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2559,16 +2559,10 @@ static int setup_virtqueues(struct mlx5_vdpa_dev *mvdev) static void teardown_virtqueues(struct mlx5_vdpa_net *ndev) { - struct mlx5_vdpa_virtqueue *mvq; int i; - for (i = ndev->mvdev.max_vqs - 1; i >= 0; i--) { - mvq = &ndev->vqs[i]; - if (!mvq->initialized) - continue; - - teardown_vq(ndev, mvq); - } + for (i = ndev->mvdev.max_vqs - 1; i >= 0; i--) + teardown_vq(ndev, &ndev->vqs[i]); } static void update_cvq_info(struct mlx5_vdpa_dev *mvdev) From patchwork Wed Jun 26 10:26:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712570 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2040.outbound.protection.outlook.com [40.107.101.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9F9B18132B; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CB:EE_|PH8PR12MB6698:EE_ X-MS-Office365-Filtering-Correlation-Id: 254fd3ac-3824-4797-c323-08dc95ca91b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|82310400024|376012|7416012|36860700011|1800799022; X-Microsoft-Antispam-Message-Info: =?utf-8?q?gDAdsE74lzB7g8oSWn8YWPn95qHqwkt?= =?utf-8?q?uKAA+H98o7mtM1Cs8Ug+e7iDXjUntNes6xFYyExf0qq7xxefKB1o6xZ8QD8zBaqh4?= =?utf-8?q?MdqsskwMsCS44zC/CkzxjH/AdTsAVgqxNF9tGpV8V4EGhCQgPhj8xTyWPpmh+fDlv?= =?utf-8?q?pExqkDmyX5OAeYBmjdFcFyPATTURC8cPremL9zuMKDZENwlJ8Si/muOy12SNZUrGI?= =?utf-8?q?hIcpWHKxZHJC3skDyS6LZJJZbq1xRrLtf3qNOBPSzQw9j3NwKGuzwzQtSEEMPUDED?= =?utf-8?q?ik9t6VXjKDZMROYfhRAvD3UHrm78xdJ8sQtHAdyO4dqSrb8SB+yNdMb/lQwvbqpwD?= =?utf-8?q?zcG4itii8gc1vQemmKLxh4xdQY0VxTKBYohc0j5BDnS+ru1+9ymrRnzf0rrKMVp/U?= =?utf-8?q?JgvV8AoyIS1wibILRH/J0ZOHKrJ3/jytgEx7Ff76kB07cK0xRBbzBiJQ4MbgZ5P9/?= =?utf-8?q?nTgX7BVFXgIn99/9409RAxelTWYJDwEHnuDGn1lQctjqdvCC8csQdQMdVxgYqjy5d?= =?utf-8?q?JWuowN2jFP+0Iayof/zJLZIYJYvNv08/YMrt8b5eEuTJ0pJUaf7kDhw2eAL6e5Ssm?= =?utf-8?q?NG5aAkszG9MwjlRs7qsErUXoaHKGY5K7ht5saItib60qfR46E1Mt1lEwJF9j9IfST?= =?utf-8?q?SmLmnMtN9ePYPL5FSecXBzaW5X+yZQUy8x/3jEXr9t2ng3tVDTCOLFsuXHaI2cUgL?= =?utf-8?q?Z0KonBVs065M/gATv52W+JhAm72w+EBralBA+2az5sJMPBqAdcS9XNuvFb4MP0I1s?= =?utf-8?q?oY/AmrbyDieosSPCdsYZ2ez+BkfQ3p3YaS3ymJJW4TZSSbqBwdQfe3KReSqpmmavN?= =?utf-8?q?LLDQmtX2l9cAwEvQf4t98+ntqe3MIgBxK4AeFp6HaTcfJnjUjsjBuouJ5xhSkg+Iw?= =?utf-8?q?5w+wtqniABlopk2T1mk9kRU1igyGIGGZUenqY1qO4x8/YUB8xn2POA0uMYjGr0+tB?= =?utf-8?q?k4xCDRJSlNeoo0Cnp89jU94z474SbeigSfgDzq480spt9xMvu7ScvtkZGo0BRLzyG?= =?utf-8?q?ai0g1ctKyIID6UzamofX2sk1sncPTCWhgsnPogxPfWjyGt7cCzQpZk5ZYKVy0DpTG?= =?utf-8?q?pDJJz926ybgaVy7dFqJElCq4u2vBH/Mb4Ny/g1ZUuWGxK5eJ9kq0MZcdH35FcpErf?= =?utf-8?q?/klr5xPINViCP/rlJrq4RDAtOWvmTJbf1yyuf5W2n6SFBUe+OXbcQAdos5jSaRWXa?= =?utf-8?q?YtaXG3kwfrJl3YgV5JMW7ln9BfnjN75HxiPyB5fsMiKMeDPavuzEimkq6Ff8ES7LQ?= =?utf-8?q?G3gVswNPnkqee3EYcC4oj1WIKebUmBbbPhVN2fShIObvtegcdz+8BeBrJMwcqhHfL?= =?utf-8?q?/Q6iK4EJ+PrHUJb+2ooe2gdKhfUmAM+rIQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(82310400024)(376012)(7416012)(36860700011)(1800799022);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:23.9421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 254fd3ac-3824-4797-c323-08dc95ca91b1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6698 No need to iterate over max number of VQs. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 96782b34e2b2..51630b1935f4 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1504,7 +1504,7 @@ static void suspend_vqs(struct mlx5_vdpa_net *ndev) { int i; - for (i = 0; i < ndev->mvdev.max_vqs; i++) + for (i = 0; i < ndev->cur_num_vqs; i++) suspend_vq(ndev, &ndev->vqs[i]); } @@ -1522,7 +1522,7 @@ static void resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mv static void resume_vqs(struct mlx5_vdpa_net *ndev) { - for (int i = 0; i < ndev->mvdev.max_vqs; i++) + for (int i = 0; i < ndev->cur_num_vqs; i++) resume_vq(ndev, &ndev->vqs[i]); } From patchwork Wed Jun 26 10:26:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712571 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2071.outbound.protection.outlook.com [40.107.92.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BA5A17F4FF; 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Reviewed-by: Cosmin Ratiu Reviewed-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 51630b1935f4..eca6f68c2eda 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -3355,17 +3355,12 @@ static int mlx5_vdpa_suspend(struct vdpa_device *vdev) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); - struct mlx5_vdpa_virtqueue *mvq; - int i; mlx5_vdpa_info(mvdev, "suspending device\n"); down_write(&ndev->reslock); unregister_link_notifier(ndev); - for (i = 0; i < ndev->cur_num_vqs; i++) { - mvq = &ndev->vqs[i]; - suspend_vq(ndev, mvq); - } + suspend_vqs(ndev); mlx5_vdpa_cvq_suspend(mvdev); mvdev->suspended = true; up_write(&ndev->reslock); From patchwork Wed Jun 26 10:26:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712572 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9172217C7CD; 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Wed, 26 Jun 2024 03:27:16 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:27:15 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:27:12 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:43 +0300 Subject: [PATCH vhost v2 07/24] vdpa/mlx5: Initialize and reset device with one queue pair Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-7-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|IA0PR12MB7554:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b52adba-f165-475e-9d2b-08dc95ca97e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|82310400024|376012|7416012|36860700011|1800799022; X-Microsoft-Antispam-Message-Info: =?utf-8?q?R+/1vfT56aOq+kihR06wrbzocWIQaP5?= =?utf-8?q?AAJL/UB/kd4kaeQhx7WK4jiNE/+v/5ua1Ws4og3SQ43T8/nXv71Y6t0+/gn9LB6k5?= =?utf-8?q?kQLSRkIj/dOZzMXT56l+4TQ6hV+Cpy1MJhSNpvwy8LuCPFxHTRLYEfdYYlrsVGTZR?= =?utf-8?q?dHSm6w1JyD2eCYyrsMru60pXO5NLcyOg9ZbSFu1e1RPB61GVVLjpv+sGpR3kGdCge?= =?utf-8?q?3DXnxjtiixBbTaz3hNWd/J07R8Rnhllh883yBDkNDspo3SKAx8xvc32aqEbngiPxt?= =?utf-8?q?M9+wY1ODdWLe7z/to2c02NZrWXO7m07sXId1oZ/F/dIRLUTgUev3BQs2ugzTdm59N?= =?utf-8?q?RBTv12R1GTib50Wo15wVyzEwOH9S+Lr0iQY6I1SIpxu96nu+ihbvCsXKo1pfNWkXl?= =?utf-8?q?WMdQ8YlqzwFtc2vlzpdgsUTuwRHWTHJTIXmYujYjV5l6Jf9rapLst8Wf8rU+cAi1c?= =?utf-8?q?ST7ym1fe0YaC1JUIPPVgfw2Ot2j3bnJwGsxXxi7146mGUV+XMJML6D+Z83BjeC9qW?= =?utf-8?q?qWOJL+PGb/rU8oHFCn5BIvLddjM2OIUsJJhUvHanAe/1lqqdR+yGK/UCPOEwtQaMZ?= =?utf-8?q?wffdqIR1+FOQDBG73Nzy4xOsRjt8HQk2A+dV+BcvupSErrAQfAL7vv/wa5Tg1ptv8?= =?utf-8?q?yjkJWnZ0LsOSyo/iGEOiD6ZYyTGcdSrsvX4hpCxdZIb76mBGkg9pDgUxzAP6ahHAl?= =?utf-8?q?kgWlbp5IdfBgmRSGba3XABT4w7+MlSbEGNb6RZD0yKlN9eh0HPd6La06UD4Bzl17q?= =?utf-8?q?GzG/isQJ6Gs1gsaZa27tSlwdIWF58b74WizrlPCU+YLHtv5MOm2oN8DTpi9RDT9S6?= =?utf-8?q?nfgd0mco3vPRuJKJq9857WCReos/ZGahGWtbfc4KbcBP/uAhh3tmHUZHUPMmAKxH0?= =?utf-8?q?7I7u6+TKGptdIpZp6eHLWYvXtOcwQo02uQxCW3vdugFDr4nOfM8lEFcs9Ag6y+F9J?= =?utf-8?q?WF+1kO7pyHYY3WwXEZM4k9OFcwsNz9ubUW5Kn9CzpWdl619+ATz1qLeC/mMjkcw2C?= =?utf-8?q?hnPja5BZDWnAJIelEQiVYGShyJDSzUJoij5/XiereMXypPeMuovuqeuegnOOfzcfh?= =?utf-8?q?OwGLdnvPxh+G4fAIkT+o4YcwAZ5mwqZ2ScOqETzpQFOx3N1X4/jGEdyV/G7gRlGj7?= =?utf-8?q?vbxthNdeQNuL9kolgCtLSQWFoPp+dxUZqHCrKX3pSPsPuW/GiazdaJBPJ3V1X2fZT?= =?utf-8?q?XSDkFv33BJYN/m2sDoX0c9DffQZK/gKiqLUJyKQYj08CRt6Fw0O2zJ0JNlsiJSiG/?= =?utf-8?q?bmJiQzGzl1evTNKfG0XZ+JO/nkD+p0RpxD6dJcsiMguluZlLv+eyzWU5lTh45u5Z5?= =?utf-8?q?K/xg+0hsbbffyTTIFyLSK3bwFQY/TJ5vcQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(82310400024)(376012)(7416012)(36860700011)(1800799022);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:34.2923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b52adba-f165-475e-9d2b-08dc95ca97e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7554 The virtio spec says that a vdpa device should start off with one queue pair. The driver is already compliant. This patch moves the initialization to device add and reset times. This is done in preparation for the pre-creation of hardware virtqueues at device add time. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index eca6f68c2eda..c8b5c87f001d 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -48,6 +48,16 @@ MODULE_LICENSE("Dual BSD/GPL"); #define MLX5V_UNTAGGED 0x1000 +/* Device must start with 1 queue pair, as per VIRTIO v1.2 spec, section + * 5.1.6.5.5 "Device operation in multiqueue mode": + * + * Multiqueue is disabled by default. + * The driver enables multiqueue by sending a command using class + * VIRTIO_NET_CTRL_MQ. The command selects the mode of multiqueue + * operation, as follows: ... + */ +#define MLX5V_DEFAULT_VQ_COUNT 2 + struct mlx5_vdpa_cq_buf { struct mlx5_frag_buf_ctrl fbc; struct mlx5_frag_buf frag_buf; @@ -2713,16 +2723,6 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) else ndev->rqt_size = 1; - /* Device must start with 1 queue pair, as per VIRTIO v1.2 spec, section - * 5.1.6.5.5 "Device operation in multiqueue mode": - * - * Multiqueue is disabled by default. - * The driver enables multiqueue by sending a command using class - * VIRTIO_NET_CTRL_MQ. The command selects the mode of multiqueue - * operation, as follows: ... - */ - ndev->cur_num_vqs = 2; - update_cvq_info(mvdev); return err; } @@ -3040,7 +3040,7 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) mlx5_vdpa_destroy_mr_resources(&ndev->mvdev); ndev->mvdev.status = 0; ndev->mvdev.suspended = false; - ndev->cur_num_vqs = 0; + ndev->cur_num_vqs = MLX5V_DEFAULT_VQ_COUNT; ndev->mvdev.cvq.received_desc = 0; ndev->mvdev.cvq.completed_desc = 0; memset(ndev->event_cbs, 0, sizeof(*ndev->event_cbs) * (mvdev->max_vqs + 1)); @@ -3643,6 +3643,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, err = -ENOMEM; goto err_alloc; } + ndev->cur_num_vqs = MLX5V_DEFAULT_VQ_COUNT; init_mvqs(ndev); allocate_irqs(ndev); From patchwork Wed Jun 26 10:26:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712574 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2069.outbound.protection.outlook.com [40.107.94.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E695183096; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CE:EE_|CH3PR12MB9099:EE_ X-MS-Office365-Filtering-Correlation-Id: b2199088-bf62-4827-23c7-08dc95ca99d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?YXQcb07SVxetIqMghgn5MpjrewFpnaF?= =?utf-8?q?JalT3DRbGXiugC5sGpnu5rQ3XsNKy65Q6e7DMJ+aGjdazVi+tFyBVPkb/+6PvO9DL?= =?utf-8?q?KIu+ipWnE/PO5BwThEiGsmXubUDF6KdLIStWVu4azCWR4hMhgT5+RZK4ftUe+l2+2?= =?utf-8?q?T/7acNQvC+gtsj/2EjCvuA7Y0OqGAqZ55CCfdr4NDTeWJeZljMviaqlzd+TQLXwJ3?= =?utf-8?q?4s5kPuqu8nvLswyBl9D9jz9WSnMQpa9NpHPMqqRlqUBf3oilPvZmrPrT1r3wOTzrw?= =?utf-8?q?QJILt6SWeHR6e5Yzv8O168kcXVzEi5K20ZmO3xulp0L7XZztwV+8qYxrNZPjCopqB?= =?utf-8?q?zYxXupgEoaZwYM9GmSfejqC/h7xoFYy322WKuiJtrvMfkSmcVcrDNvp5cCwFW+CR2?= =?utf-8?q?6YxcCY45fu5/Qo0LhDAkALtkUfCG+2v6tHabh3eUbvcOaK+wNkihAdTz4ligTaDIV?= =?utf-8?q?a7eenZINFxOTsfI1nnGrM1r4Eof/7IC+hifcguzxWkYr7mmuDDQiRWU/vpqaNPNZU?= =?utf-8?q?XEO2J8orKA5SgtJv6YHzL4yQTM1L2zUJDLHUW+3lqMdBiTu7Eg+JUI336OgBjXoo1?= =?utf-8?q?noXYvQ5vBaUBvDCcs34EKJ+/AemxwtpegBO/NAXboYzhzh2YbCDhFUwLZg6dgF1oR?= =?utf-8?q?/O3HYV8GYAI7Qb80cGqFO9/ixRNn1WxmAHLmfKlQVytJMDAv2v+foIevCfgW7n/Y/?= =?utf-8?q?ULGoTEE0o/CJ+ptYOkALN3cXKayBl5xx+1PbNxFk00mO/qn7dCyS/CQ3S7MLzi0f4?= =?utf-8?q?AntTucSA5tbuVFIOB3v9qqBlp6bbZFNyNQxB0dLXwfmHfRA0swKAR1dPCHDPag5YA?= =?utf-8?q?EEVYx41o37+/kQVsRrIkQHcJHp9nqJxzs5hllCM5rCNw4Z7QQTohDLQjuhsR973R3?= =?utf-8?q?R+b24vztE8uFrXVI8E9itS8UC5TsWWgmw/MtGZOtFBpCjAx6foUZ2akoHui472Aj8?= =?utf-8?q?15FAqd1tK9+l3yCbzxXrng5QNHcKkzQ/y2fGjIw4iruIRFwvXX+NU2qs39StWYYuv?= =?utf-8?q?k64AYBSIEu5uf40Rr3+/CVb8uvjc8FhFvnVNeJbeVPzLKT6ntYaieN3MmuwdU4nc6?= =?utf-8?q?a/yF4XIE6hUU8gJ8Y/saGfiFMIETNUkA/pOpG0RxwlGX259VTAjxLRgI8L+qGoLH5?= =?utf-8?q?83xaCT0equUp+7cpkSQ1lV9O8lFEvGlqA0HQ8rz1uDef6na5IqUM+k+1+Ui9BLC2w?= =?utf-8?q?JKI/vTMTwZzGm/rxwy5HVhfQbvCVbcuE1BzwYDZkEmB9wZhXo/ip1cvv7H7Y9qqbC?= =?utf-8?q?T13lzgdrQDk+7UFEvMxXoBTkHhBs06SGiL6qpJ5wzunSIRk65PxGpddnqA9G2Rqz5?= =?utf-8?q?zBR16ARGc+m0mkcAcWXTBKPizVGLra9H2g=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:37.5267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2199088-bf62-4827-23c7-08dc95ca99d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9099 The hardware VQ configuration is mirrored by data in struct mlx5_vdpa_virtqueue . Instead of clearing just a few fields at reset, fully clear the struct and initialize with the appropriate default values. As clear_vqs_ready() is used only during reset, get rid of it. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index c8b5c87f001d..de013b5a2815 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2941,18 +2941,6 @@ static void teardown_vq_resources(struct mlx5_vdpa_net *ndev) ndev->setup = false; } -static void clear_vqs_ready(struct mlx5_vdpa_net *ndev) -{ - int i; - - for (i = 0; i < ndev->mvdev.max_vqs; i++) { - ndev->vqs[i].ready = false; - ndev->vqs[i].modified_fields = 0; - } - - ndev->mvdev.cvq.ready = false; -} - static int setup_cvq_vring(struct mlx5_vdpa_dev *mvdev) { struct mlx5_control_vq *cvq = &mvdev->cvq; @@ -3035,12 +3023,14 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) down_write(&ndev->reslock); unregister_link_notifier(ndev); teardown_vq_resources(ndev); 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Signed-off-by: Dragos Tatulea Reviewed-by: Eugenio Pérez --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index de013b5a2815..739c2886fc33 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -155,7 +155,7 @@ static bool is_index_valid(struct mlx5_vdpa_dev *mvdev, u16 idx) } static void free_fixed_resources(struct mlx5_vdpa_net *ndev); -static void init_mvqs(struct mlx5_vdpa_net *ndev); +static void mvqs_set_defaults(struct mlx5_vdpa_net *ndev); static int setup_vq_resources(struct mlx5_vdpa_net *ndev); static void teardown_vq_resources(struct mlx5_vdpa_net *ndev); @@ -2810,7 +2810,7 @@ static void restore_channels_info(struct mlx5_vdpa_net *ndev) int i; mlx5_clear_vqs(ndev); - init_mvqs(ndev); + mvqs_set_defaults(ndev); for (i = 0; i < ndev->mvdev.max_vqs; i++) { mvq = &ndev->vqs[i]; ri = &mvq->ri; @@ -3023,7 +3023,7 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) down_write(&ndev->reslock); unregister_link_notifier(ndev); teardown_vq_resources(ndev); - init_mvqs(ndev); + mvqs_set_defaults(ndev); if (flags & VDPA_RESET_F_CLEAN_MAP) mlx5_vdpa_destroy_mr_resources(&ndev->mvdev); @@ -3485,7 +3485,7 @@ static void free_fixed_resources(struct mlx5_vdpa_net *ndev) res->valid = false; } -static void init_mvqs(struct mlx5_vdpa_net *ndev) +static void mvqs_set_defaults(struct mlx5_vdpa_net *ndev) { struct mlx5_vdpa_virtqueue *mvq; int i; @@ -3635,7 +3635,7 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, } ndev->cur_num_vqs = MLX5V_DEFAULT_VQ_COUNT; - init_mvqs(ndev); + mvqs_set_defaults(ndev); allocate_irqs(ndev); init_rwsem(&ndev->reslock); config = &ndev->config; From patchwork Wed Jun 26 10:26:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712575 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2086.outbound.protection.outlook.com [40.107.236.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 095E6184124; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E65:EE_|DS7PR12MB6069:EE_ X-MS-Office365-Filtering-Correlation-Id: bdefe25e-b6b9-4796-b0b6-08dc95ca9aea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?LeMgQxMPTIUQkiJT393knukObbwY1t2?= =?utf-8?q?lEZNq6CrsyJ8BCdqUFrN5gQKyNYh8djumM/sWAbZnbduS9W9UNih0/6DAv9UnhMFS?= =?utf-8?q?3ITlWPd3W4z+eswCjeqjz7Si5b61NowyeYn0Lt0M2i2FopBUX1cq0M7PuAc5tPpp2?= =?utf-8?q?72Kdc+hrPNXf4ik0i2E54bdGzpaD14vwj8A8lLq8GvOZXVHUHs99YOQVnWbo1EIEr?= =?utf-8?q?mNCdJx/RmJsIqKVwVSntyBx+WJcxhx0F+RTF2ZsyGqK72KpxLdY3X9aoWEgOkx1oT?= =?utf-8?q?aVT0GIBuJXWEePOpBy/NadGAmhj+coqNFtDrvglUXdEKt4bdav19PP4HvXHnNGm6c?= =?utf-8?q?0zsvEA27X8/OpT9YNoJm11x2WoZXXolVkicAj14M0ECA0z73yPkdcvDKhah7DiXIV?= =?utf-8?q?jyvA8amdKwl5KuD9kIayZZVN8tNuT40busgP2RE+xakXSzrvtJOS5KgORGT0BTc73?= =?utf-8?q?X5gxDn7HFjWuo3pgsbJTuvKd9Yz6/kM/cKENQ/oI8swZb9q8KRGqWY5owh2ROWiT0?= =?utf-8?q?g1h5J4CWh1LhK2X8+Hou5Mmp6dy5U3eHKd3eVn+X03+ih+MkQzFCPxcf9mrgTu2f+?= =?utf-8?q?PW4a58sdH8rfpTajEFlv97osFH8el9JEzfDyup855yWLBrproKFZWf1J36Jlvy7OM?= =?utf-8?q?cftR+OWRXM/jTkHxl1WonajyHUVsR7lVVdnUJgMUb6UV2fSrWrBm1ZW2w1r9X12Cs?= =?utf-8?q?padND6A5vR+tFdP/QAFUXA4/zXRIhrLolPObt3fNaS6yvjL2TIEvO2po+8/TZVeRZ?= =?utf-8?q?iNBbMejTPUc+aI31e0/o1J94iojTlrcawKw9XFq1oULp31Xrz0J9mtrDew4BFYtQ/?= =?utf-8?q?qfLT9BY865cv2NqJfIazOtZlOr5+ArEQ/CNy2qTwu0TaV3HckLxZKZ/tkku09vKpR?= =?utf-8?q?3ZqWq8N4yeGHJbiXeq3NoX8F6yQ46KMWEfaDVlRCOY2sNv48wYL+TdoJCL21ys164?= =?utf-8?q?794yGEKvnX6Ev2C9yIrASpYs8rbfUlMbcsFFpd6S3yAq9iOul/B1Utx4Vp3CnBwJc?= =?utf-8?q?uvDLAHfWws/ELPcMEUp20PcL8e+gDvbzhvbwf0CKoZGZ1R3CmtHWHZxZ0PewOazil?= =?utf-8?q?C9pbsQ0R81JrX5feWsr5ACfxLZ4QZRcK2kLq//ab3NwDwg3VsWHPDLylomgK1b3Ya?= =?utf-8?q?PVvNUsFGOrZELNO4mvwLgTfxvq2gvvHZ0OSBktm5YMuQEaFOyknihMDtNyaTFesks?= =?utf-8?q?2Ypd2ntPTXkf3f9VTT3Om7aO/wTDy0l8JLaMDdCl6LeXw/0SxGt8rxaBmjZFUi5A2?= =?utf-8?q?hM+GcazuTOJjdEKzJAhrSGtoX47qf13C1Yyjqn7ZLvkGeru1LYsm2U98bhqbiD69u?= =?utf-8?q?8DVV4TED2yPL6UIcZEffz6FJOi2S5CWUfw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:39.2740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdefe25e-b6b9-4796-b0b6-08dc95ca9aea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6069 This is done in preparation for the pre-creation of hardware virtqueues at device add time. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 16 ++++++++++++++++ include/linux/mlx5/mlx5_ifc_vdpa.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 739c2886fc33..b104849f8477 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1283,6 +1283,10 @@ static int modify_virtqueue(struct mlx5_vdpa_net *ndev, if (mvq->modified_fields & MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX) MLX5_SET(virtio_net_q_object, obj_context, hw_used_index, mvq->used_idx); + if (mvq->modified_fields & MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION) + MLX5_SET(virtio_q, vq_ctx, virtio_version_1_0, + !!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_F_VERSION_1))); + if (mvq->modified_fields & MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY) { vq_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP]]; @@ -2709,6 +2713,7 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + u64 old_features = mvdev->actual_features; int err; print_features(mvdev, features, true); @@ -2723,6 +2728,17 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) else ndev->rqt_size = 1; + /* Interested in changes of vq features only. */ + if (get_features(old_features) != get_features(mvdev->actual_features)) { + for (int i = 0; i < mvdev->max_vqs; ++i) { + struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[i]; + + mvq->modified_fields |= ( + MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION + ); + } + } + update_cvq_info(mvdev); return err; } diff --git a/include/linux/mlx5/mlx5_ifc_vdpa.h b/include/linux/mlx5/mlx5_ifc_vdpa.h index 40371c916cf9..34f27c01cec9 100644 --- a/include/linux/mlx5/mlx5_ifc_vdpa.h +++ b/include/linux/mlx5/mlx5_ifc_vdpa.h @@ -148,6 +148,7 @@ enum { MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_ADDRS = (u64)1 << 6, MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_AVAIL_IDX = (u64)1 << 7, MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX = (u64)1 << 8, + MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION = (u64)1 << 10, MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY = (u64)1 << 11, MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY = (u64)1 << 14, }; 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Wed, 26 Jun 2024 03:27:28 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:47 +0300 Subject: [PATCH vhost v2 11/24] vdpa/mlx5: Add support for modifying the VQ features field Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-11-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|LV8PR12MB9263:EE_ X-MS-Office365-Filtering-Correlation-Id: 81bdc33a-989b-4787-f46a-08dc95ca9fab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?97uaTpTsUwFZySpYLgVBFcVtBDyMyEZ?= =?utf-8?q?Qoi1Hy//WIrsE4CJOtr9HaU5ZF5DJSuph45NAKfIJZUkzaIJaUHMTuz1eXibINCOS?= =?utf-8?q?U/Zp0ddQzpMz3OPkG22gg61vWulUI9Wt9zBzYBr/CmYBDPZMdUwcE8wrXQA8vhY/h?= =?utf-8?q?okaOWon08UPLjTiLA97UPXgvB44y2EOE4O4rZ+P2zzJhCkCH9/7eFhAgB1PIR88zK?= =?utf-8?q?ew8PAImd/ShuketPnhi06d7qdF5u99iU71w/DDNHOZc8Mzxr/2fA52Pqxfc7Fu98z?= =?utf-8?q?4igPN94gAISCCZkR1yT4tXuPPbiLFIWqoZob6iABbNPcaY3TkmnqJfL/RSTtbtG/I?= =?utf-8?q?scYHOC590Ny3Lne0QFgMBbEjuSx6C4+HMKw1DjsJDeqm8FPAjAgrnwfqjQ4wL4a8G?= =?utf-8?q?jzma2dsPuK+EmnzGMH4JJVljvjy2ZbUX8mAhJt7jVOCyZUhYTcrqZo6LxV9U6CU5F?= =?utf-8?q?zXrwtHyWtbskGstCY/0I1kh2WXEGYEgUjWfMx+16mLTJO8YPpbR3YpJg7g9q7bQ9K?= =?utf-8?q?0rzXfTfaFVJjIiZFvz6zNQ0J/NWWHgIDkshCwBqpO6brnMiwHl4c6vOicVUOD2171?= =?utf-8?q?21Jjjn/0fkPOOxnvG+shMTvIBp3BYc1KqNsibGa7NpRBVfHKHTuH0Uwzwb2eQoVw1?= =?utf-8?q?2KMkx5OsIdePuHUTZ7zIPSFpeEjMXHE3Za/l8AxSm9AxpXovWtPYnD8wUDMKHF+oc?= =?utf-8?q?VZYjfJnglrEGPrSQpPux321bjUvuSF6ecxye/EirtAUpbrWhhXOfkfgn3JnDcFsDq?= =?utf-8?q?dkASSQGqkzP1szcd1wlO0lRhYoba8Jvj6crugwW79jC4dZKmTW5jqE7uJn2CIKqnv?= =?utf-8?q?6ngQsoSEGKPP7fRcdFJ/4O9vSYcLNHQxM5T2Zcosqa7GJyZsYkmCe7EtWp6H4DA2n?= =?utf-8?q?iFirECzcxwpucMMyAFH5P1UqRTcdjq0wWYPQaUrWXvghBYVHxg6fs5UKF9gFSpkiS?= =?utf-8?q?BVTykO3laHXmX8jdbwA+amIr9zQN+wT/m0xzJD0H0BtLQgKy7gWEk7+x9ekoFlfTa?= =?utf-8?q?5lcUZ5m/EpKh8mF9RCmOXFenZBQ71gU9p+Xwc/l2DiGvO7vowIRrQcernWpfSH7UB?= =?utf-8?q?pNv9dhpNi5LCxR/xpNCSQdH6PTOiXjhHThpkWlW2u9aTIBdGnOsJ/UNri+d+1NtsU?= =?utf-8?q?FhqoosXt03841/g8mq/rl/1650EhR3TFiaJAiG1lTHXzjJevS4OockCXO7MPFNHM4?= =?utf-8?q?1GQigDqbYzLJiyv9545QWek3zYJM6vHxR6lGSx7UKTLwickmPNAxwMA23QjiHM0ea?= =?utf-8?q?Glg/zYyX7JUltu5pnhaateo9CjcIF7YQRaRWbMEuhdF4zf3WZ0UqgkowmNonWnU2g?= =?utf-8?q?GHasxE3h+a8IRX8FjPSJCl3gW1XKDFe4I6zgs6SLviAYtXFhWHx5Dhxg5QCRBYl0m?= =?utf-8?q?UeoBnrS+bOH?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:47.3453 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81bdc33a-989b-4787-f46a-08dc95ca9fab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9263 This is done in preparation for the pre-creation of hardware virtqueues at device add time. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 12 +++++++++++- include/linux/mlx5/mlx5_ifc_vdpa.h | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index b104849f8477..db86e541b788 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1287,6 +1287,15 @@ static int modify_virtqueue(struct mlx5_vdpa_net *ndev, MLX5_SET(virtio_q, vq_ctx, virtio_version_1_0, !!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_F_VERSION_1))); + if (mvq->modified_fields & MLX5_VIRTQ_MODIFY_MASK_QUEUE_FEATURES) { + u16 mlx_features = get_features(ndev->mvdev.actual_features); + + MLX5_SET(virtio_net_q_object, obj_context, queue_feature_bit_mask_12_3, + mlx_features >> 3); + MLX5_SET(virtio_net_q_object, obj_context, queue_feature_bit_mask_2_0, + mlx_features & 7); + } + if (mvq->modified_fields & MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY) { vq_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP]]; @@ -2734,7 +2743,8 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[i]; mvq->modified_fields |= ( - MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION + MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION | + MLX5_VIRTQ_MODIFY_MASK_QUEUE_FEATURES ); } } diff --git a/include/linux/mlx5/mlx5_ifc_vdpa.h b/include/linux/mlx5/mlx5_ifc_vdpa.h index 34f27c01cec9..58dfa2ee7c83 100644 --- a/include/linux/mlx5/mlx5_ifc_vdpa.h +++ b/include/linux/mlx5/mlx5_ifc_vdpa.h @@ -150,6 +150,7 @@ enum { MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX = (u64)1 << 8, MLX5_VIRTQ_MODIFY_MASK_QUEUE_VIRTIO_VERSION = (u64)1 << 10, MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY = (u64)1 << 11, + MLX5_VIRTQ_MODIFY_MASK_QUEUE_FEATURES = (u64)1 << 12, MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY = (u64)1 << 14, }; From patchwork Wed Jun 26 10:26:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712577 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2077.outbound.protection.outlook.com [40.107.236.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF92A186283; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|MW6PR12MB8833:EE_ X-MS-Office365-Filtering-Correlation-Id: 5519cbad-342a-4a98-bfa8-08dc95caa091 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?VTjpy12BR6/Y7M5rTN203kAyRDXY9y0?= =?utf-8?q?S5cu3u3U3BeUEG+39rvaf8W/vl/yECjsjHzKZWt2Aq2iTIF0LVlNGrCyYHkJMhBcl?= =?utf-8?q?VN2kjr1aXv88MG3OLmCbua9PisHfDGp16ZvMlTT5uwiNBYcgJjArACPO9AcDTMwRe?= =?utf-8?q?m+bIKmPYEqOq8P9Rul/WCICJtUX0t6lF9tAAI4l2IJJMZMAth+YmFge28YoTJv+Hh?= =?utf-8?q?Ulvz8KYdFv21Ws6DeU2J966kxg0qvWvHFwqNHQ+E8mUcUXEmCZMD5fwFGqc6pso/U?= =?utf-8?q?tplrGkAI47LwTrxEXqTDQCTAWr6E0JOQ9+PCHgwo/8lyD9v3hfly2mEIFFFLXwuix?= =?utf-8?q?swffawE8qXvADHv/9zYlIxRhbSGzXoaXk+PDVqoPAVsdxNy+TJzs4tbSv5G2APNVx?= =?utf-8?q?fKGRDU+LFIBYPHK4gj7CiD5d6UUI3kCeuJHGjlVUfKAFa5Gh2qNgBgt01U70f7isA?= =?utf-8?q?SDf1ze1HJZwfYgm84TJWlz0AbwbXMz6G/L2Fc8dGEtiLs+hhw9jsgm5SNtyME9i8T?= =?utf-8?q?UKhjTOLSOozPpX8xV+hAZvkMo0K7nKlQLPCJgoVaz0788DVRo/ITWWq9HNGYw99Tj?= =?utf-8?q?1f1yPkutTBbSYzQCDsPrx6lkjYQYW0OKz5bRX3KaFPRQJ/2fhm3jNL4NSc2OZ3Hrz?= =?utf-8?q?cnD7wEpUFZBeGHPhTdAGsRXWXbO0n7iTiY499QnES+VPuruzyTx0o8xxHQG7Lnyeh?= =?utf-8?q?4xYP1mIcGymIstC55HgnO3nAqcRcZVD7ZD2yVfile+dUKLen9J0SUcUfNmV498Zi/?= =?utf-8?q?Fb3+NQsRGtp83wFJo2IIhfA5GTyvEoAylVD+N/xT2JSrTssfq+LuBZ4SpLaxD2bLL?= =?utf-8?q?FdxBMZXAIus86ggQKeQxSuM2DT4hqxnBGBl6lTkPybN38/lxP4WRMiizv297VwMkL?= =?utf-8?q?3qNGBaqldNt8Wi8ZOjN6Bbhy3vRojJT1BR+ybGLJ6ICXg3Gfr1h2r5G7T7N+8/Gxf?= =?utf-8?q?KfeC805o/il5eaxI3DnLap3avU3YOFb4m4b/nl3qWjO43+q2Hw3JcZLMC+rAdYhYe?= =?utf-8?q?i+YG4C2kpOsYrrIPBqrJAiXRnJomo/WZjR1VtjvS2mhbAKgXan9kHa0bkn09r12AX?= =?utf-8?q?bUR2RFT7777ZVvW6DL29qvuctaf3exU9yfKwNVZd5ljDKa1bAEowiqBq2Xhk4kvHj?= =?utf-8?q?VD7R/RTLQ7GqzEBRTN5EXmWIFihWexN/VyDydgXXLUg4K7Jlu+6vymE7/v540aSzq?= =?utf-8?q?sD9a1mBv3VsqyUq6AjdOCFcZIvhPuAu52fuOh4EB3O/A+C9AIZ7dlpfa+tySnPr/g?= =?utf-8?q?0b/n5u5Mz5H+eLPykqxHQkdQ1p16k8WbkE2HPt7T6Hg2tOm0G0VAgKy4zdfWzrTY9?= =?utf-8?q?VieoX2bUduFK+C/B50onzQmTNxTe1BJNow=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:48.7575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5519cbad-342a-4a98-bfa8-08dc95caa091 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8833 The virtqueue size is a pre-requisite for setting up any virtqueue resources. For the upcoming optimization of creating virtqueues at device add, the virtqueue size has to be configured. The queue size check in setup_vq() will always be false. So remove it. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index db86e541b788..406cc590fe42 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -58,6 +58,8 @@ MODULE_LICENSE("Dual BSD/GPL"); */ #define MLX5V_DEFAULT_VQ_COUNT 2 +#define MLX5V_DEFAULT_VQ_SIZE 256 + struct mlx5_vdpa_cq_buf { struct mlx5_frag_buf_ctrl fbc; struct mlx5_frag_buf frag_buf; @@ -1445,9 +1447,6 @@ static int setup_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) u16 idx = mvq->index; int err; - if (!mvq->num_ent) - return 0; - if (mvq->initialized) return 0; @@ -3523,6 +3522,7 @@ static void mvqs_set_defaults(struct mlx5_vdpa_net *ndev) mvq->ndev = ndev; mvq->fwqp.fw = true; mvq->fw_state = MLX5_VIRTIO_NET_Q_OBJECT_NONE; + mvq->num_ent = MLX5V_DEFAULT_VQ_SIZE; } } From patchwork Wed Jun 26 10:26:49 2024 Content-Type: text/plain; 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Wed, 26 Jun 2024 03:27:36 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:49 +0300 Subject: [PATCH vhost v2 13/24] vdpa/mlx5: Start off rqt_size with max VQPs Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-13-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|DM4PR12MB7598:EE_ X-MS-Office365-Filtering-Correlation-Id: 6af08097-f8f0-4baf-85a7-08dc95caa469 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?4UmGM31w6Hzjt0GXAbW8YyTu9c75lu0?= =?utf-8?q?hw3KIUW0TTYmBDbiVTS7wKVQMODqcTgOuxCWpgD8pZ9Ef0JOCnxFTH/Lfn9n8R0Yc?= =?utf-8?q?uhhSYB4WK5+72vvKkUEwOY/1bR2OGkcEJ2T0Hu/BCN1aHB+h0ltQtjo/jKlJw63ZW?= =?utf-8?q?IzilTXR69bJ1iwgnpjCRzeYiB/40qM8BafuowTx8maxZC7/J1QN6qWvgSfuf684Td?= =?utf-8?q?isBh/sGGRK2UnIK3WnWvhaCASNYagKnJ2lo5jxF05fGV74rDgpNKFzKjritHoDwLS?= =?utf-8?q?ogEXT6BgwUTKbuPv9OHZREj5ILbf/HMT9rb5TJ9advrVLb7ykeebK0VaNKcpWJr4Q?= =?utf-8?q?BigKIU65ukwtkzSQQJN6K8/zhbLpTNBptCSIg5sCnpIwxOHbm+9vByK/2q4qceKvB?= =?utf-8?q?nkQNvfoQoPEP3P0jRAiDF0YWoikKatxdD6gSqJoXEfGGIW3s9SrZqxPF8CeOl/2Vu?= =?utf-8?q?DMNsn+CidHTtxM/lgjaghOniq1kEbO8yjvZxb9gQxctmomJg1BX/jtnFnfMGUfXVw?= =?utf-8?q?4mqcC7viXzd5InjsdRCSz8TIYgDOVlYmHkwDnvWGKpLI/HGJeaVObi/opmXKLToU0?= =?utf-8?q?c5sq8+3y8Dv3pEu+Syon7ZdArHss6zFDmqV3806rjTvAwKOMxBWGz6Dd9V2NMCQEE?= =?utf-8?q?qh1o+bfxcVE55Z0oht09wtwzezCAO6I4jYIn9GRGIIcqi3CIXjb3JJNpKTDa/4RW2?= =?utf-8?q?kNsSw206arnQwkCPZ51D4po9gNQ5DtUpwF0mdNHOINEpqjd0XV/BIzxGmrMpEctfl?= =?utf-8?q?wfD8YuW7hfoKUeZQ4OltUyc0Xve7zDGJuKHKCKB3xEFp/hkcEEgAH8rQ0dPnmzH8f?= =?utf-8?q?GZasZNO3m4/g1OhCEMg5oST9KEOr73Wf5+KkIFCl6Pzo6EfUGf2jSvNZVjdD7MgIY?= =?utf-8?q?PA26Ms7ZzFQw1DQyQCbD8BxoOLS9aLGWZb3Y19bW4vvrK5IfAP8j/CvS5Rfb2RpLT?= =?utf-8?q?Fp4+EXA8mzT5E63qZtPGqa5R9YlwM/ks1R6N/Dm1j+Azp7OQRWl94BFVMsZaNgFeR?= =?utf-8?q?7ifo1eU1Mom7UzogHjCQsWP7maFaVRqqVqBCk6k0SI2XFbyHyGi3jVTE+JojTm/xq?= =?utf-8?q?5x5JsR0sjB1+CvdgM7fxg7/fGq5cFeGCqGgJYtYJgCRcA2Vn5aazhqHsUpGCUnn5R?= =?utf-8?q?04iWrcyYpdMqTLQ8hOxR4OPn7JiWgI7M0pmHaZbhN2/qzEtzGK82ZfYOBbnKhTiIb?= =?utf-8?q?2Znq3h2Oj8thjJ2gpPEOFIJkqpwBC7yOSgzV5u6VTpSXq8i6s4BLLS1Zw1dnqws0t?= =?utf-8?q?DfUs0D/1HLHzahjh5UCwb90I8gJ0ifroHzKrTAWi9pQstPDIPlqi3v8+9zhGIt8yX?= =?utf-8?q?IIw+FTn3Ic2VyupR2YtWpjiyfX3XT+WvEw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:27:55.2829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6af08097-f8f0-4baf-85a7-08dc95caa469 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7598 Currently rqt_size is initialized during device flag configuration. That's because it is the earliest moment when device knows if MQ (multi queue) is on or off. Shift this configuration earlier to device creation time. This implies that non-MQ devices will have a larger RQT size. But the configuration will still be correct. This is done in preparation for the pre-creation of hardware virtqueues at device add time. When that change will be added, RQT will be created at device creation time so it needs to be initialized to its max size. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 406cc590fe42..7f1551aa1f78 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2731,10 +2731,6 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) return err; ndev->mvdev.actual_features = features & ndev->mvdev.mlx_features; - if (ndev->mvdev.actual_features & BIT_ULL(VIRTIO_NET_F_MQ)) - ndev->rqt_size = mlx5vdpa16_to_cpu(mvdev, ndev->config.max_virtqueue_pairs); - else - ndev->rqt_size = 1; /* Interested in changes of vq features only. */ if (get_features(old_features) != get_features(mvdev->actual_features)) { @@ -3718,8 +3714,12 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, goto err_alloc; } - if (device_features & BIT_ULL(VIRTIO_NET_F_MQ)) + if (device_features & BIT_ULL(VIRTIO_NET_F_MQ)) { config->max_virtqueue_pairs = cpu_to_mlx5vdpa16(mvdev, max_vqs / 2); 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Wed, 26 Jun 2024 03:27:44 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:27:43 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:27:40 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:50 +0300 Subject: [PATCH vhost v2 14/24] vdpa/mlx5: Set mkey modified flags on all VQs Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-14-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. 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Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 7f1551aa1f78..a8ac542f30f7 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2868,7 +2868,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, mlx5_vdpa_update_mr(mvdev, new_mr, asid); - for (int i = 0; i < ndev->cur_num_vqs; i++) + for (int i = 0; i < mvdev->max_vqs; i++) ndev->vqs[i].modified_fields |= MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY | MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY; From patchwork Wed Jun 26 10:26:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712580 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2050.outbound.protection.outlook.com [40.107.100.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF83187336; 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Wed, 26 Jun 2024 03:27:48 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:27:47 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:27:44 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:51 +0300 Subject: [PATCH vhost v2 15/24] vdpa/mlx5: Allow creation of blank VQs Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-15-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. 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Blank VQs will be filled in later through VQ modify. Downstream patches will make use of this to pre-create blank VQs at vdpa device creation. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 85 +++++++++++++++++++++++++-------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index a8ac542f30f7..0a62ce0b4af8 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -158,7 +158,7 @@ static bool is_index_valid(struct mlx5_vdpa_dev *mvdev, u16 idx) static void free_fixed_resources(struct mlx5_vdpa_net *ndev); static void mvqs_set_defaults(struct mlx5_vdpa_net *ndev); -static int setup_vq_resources(struct mlx5_vdpa_net *ndev); +static int setup_vq_resources(struct mlx5_vdpa_net *ndev, bool filled); static void teardown_vq_resources(struct mlx5_vdpa_net *ndev); static bool mlx5_vdpa_debug; @@ -874,13 +874,16 @@ static bool msix_mode_supported(struct mlx5_vdpa_dev *mvdev) pci_msix_can_alloc_dyn(mvdev->mdev->pdev); } -static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) +static int create_virtqueue(struct mlx5_vdpa_net *ndev, + struct mlx5_vdpa_virtqueue *mvq, + bool filled) { int inlen = MLX5_ST_SZ_BYTES(create_virtio_net_q_in); u32 out[MLX5_ST_SZ_DW(create_virtio_net_q_out)] = {}; struct mlx5_vdpa_dev *mvdev = &ndev->mvdev; struct mlx5_vdpa_mr *vq_mr; struct mlx5_vdpa_mr *vq_desc_mr; + u64 features = filled ? mvdev->actual_features : mvdev->mlx_features; void *obj_context; u16 mlx_features; void *cmd_hdr; @@ -898,7 +901,7 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque goto err_alloc; } - mlx_features = get_features(ndev->mvdev.actual_features); + mlx_features = get_features(features); cmd_hdr = MLX5_ADDR_OF(create_virtio_net_q_in, in, general_obj_in_cmd_hdr); MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, opcode, MLX5_CMD_OP_CREATE_GENERAL_OBJECT); @@ -906,8 +909,6 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque MLX5_SET(general_obj_in_cmd_hdr, cmd_hdr, uid, ndev->mvdev.res.uid); obj_context = MLX5_ADDR_OF(create_virtio_net_q_in, in, obj_context); - MLX5_SET(virtio_net_q_object, obj_context, hw_available_index, mvq->avail_idx); - MLX5_SET(virtio_net_q_object, obj_context, hw_used_index, mvq->used_idx); MLX5_SET(virtio_net_q_object, obj_context, queue_feature_bit_mask_12_3, mlx_features >> 3); MLX5_SET(virtio_net_q_object, obj_context, queue_feature_bit_mask_2_0, @@ -929,17 +930,36 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque MLX5_SET(virtio_q, vq_ctx, queue_index, mvq->index); MLX5_SET(virtio_q, vq_ctx, queue_size, mvq->num_ent); MLX5_SET(virtio_q, vq_ctx, virtio_version_1_0, - !!(ndev->mvdev.actual_features & BIT_ULL(VIRTIO_F_VERSION_1))); - MLX5_SET64(virtio_q, vq_ctx, desc_addr, mvq->desc_addr); - MLX5_SET64(virtio_q, vq_ctx, used_addr, mvq->device_addr); - MLX5_SET64(virtio_q, vq_ctx, available_addr, mvq->driver_addr); - vq_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP]]; - if (vq_mr) - MLX5_SET(virtio_q, vq_ctx, virtio_q_mkey, vq_mr->mkey); - - vq_desc_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_DESC_GROUP]]; - if (vq_desc_mr && MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, desc_group_mkey_supported)) - MLX5_SET(virtio_q, vq_ctx, desc_group_mkey, vq_desc_mr->mkey); + !!(features & BIT_ULL(VIRTIO_F_VERSION_1))); + + if (filled) { + MLX5_SET(virtio_net_q_object, obj_context, hw_available_index, mvq->avail_idx); + MLX5_SET(virtio_net_q_object, obj_context, hw_used_index, mvq->used_idx); + + MLX5_SET64(virtio_q, vq_ctx, desc_addr, mvq->desc_addr); + MLX5_SET64(virtio_q, vq_ctx, used_addr, mvq->device_addr); + MLX5_SET64(virtio_q, vq_ctx, available_addr, mvq->driver_addr); + + vq_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP]]; + if (vq_mr) + MLX5_SET(virtio_q, vq_ctx, virtio_q_mkey, vq_mr->mkey); + + vq_desc_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_DESC_GROUP]]; + if (vq_desc_mr && + MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, desc_group_mkey_supported)) + MLX5_SET(virtio_q, vq_ctx, desc_group_mkey, vq_desc_mr->mkey); + } else { + /* If there is no mr update, make sure that the existing ones are set + * modify to ready. + */ + vq_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_GROUP]]; + if (vq_mr) + mvq->modified_fields |= MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_MKEY; + + vq_desc_mr = mvdev->mr[mvdev->group2asid[MLX5_VDPA_DATAVQ_DESC_GROUP]]; + if (vq_desc_mr) + mvq->modified_fields |= MLX5_VIRTQ_MODIFY_MASK_DESC_GROUP_MKEY; + } MLX5_SET(virtio_q, vq_ctx, umem_1_id, mvq->umem1.id); MLX5_SET(virtio_q, vq_ctx, umem_1_size, mvq->umem1.size); @@ -959,12 +979,15 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque kfree(in); mvq->virtq_id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); - mlx5_vdpa_get_mr(mvdev, vq_mr); - mvq->vq_mr = vq_mr; + if (filled) { + mlx5_vdpa_get_mr(mvdev, vq_mr); + mvq->vq_mr = vq_mr; - if (vq_desc_mr && MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, desc_group_mkey_supported)) { - mlx5_vdpa_get_mr(mvdev, vq_desc_mr); - mvq->desc_mr = vq_desc_mr; + if (vq_desc_mr && + MLX5_CAP_DEV_VDPA_EMULATION(mvdev->mdev, desc_group_mkey_supported)) { + mlx5_vdpa_get_mr(mvdev, vq_desc_mr); + mvq->desc_mr = vq_desc_mr; + } } return 0; @@ -1442,7 +1465,9 @@ static void dealloc_vector(struct mlx5_vdpa_net *ndev, } } -static int setup_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) +static int setup_vq(struct mlx5_vdpa_net *ndev, + struct mlx5_vdpa_virtqueue *mvq, + bool filled) { u16 idx = mvq->index; int err; @@ -1471,7 +1496,7 @@ static int setup_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) goto err_connect; alloc_vector(ndev, mvq); - err = create_virtqueue(ndev, mvq); + err = create_virtqueue(ndev, mvq, filled); if (err) goto err_vq; @@ -2062,7 +2087,7 @@ static int change_num_qps(struct mlx5_vdpa_dev *mvdev, int newqps) } else { ndev->cur_num_vqs = 2 * newqps; for (i = cur_qps * 2; i < 2 * newqps; i++) { - err = setup_vq(ndev, &ndev->vqs[i]); + err = setup_vq(ndev, &ndev->vqs[i], true); if (err) goto clean_added; } @@ -2558,14 +2583,14 @@ static int verify_driver_features(struct mlx5_vdpa_dev *mvdev, u64 features) return 0; } -static int setup_virtqueues(struct mlx5_vdpa_dev *mvdev) +static int setup_virtqueues(struct mlx5_vdpa_dev *mvdev, bool filled) { struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); int err; int i; for (i = 0; i < mvdev->max_vqs; i++) { - err = setup_vq(ndev, &ndev->vqs[i]); + err = setup_vq(ndev, &ndev->vqs[i], filled); if (err) goto err_vq; } @@ -2877,7 +2902,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, if (teardown) { restore_channels_info(ndev); - err = setup_vq_resources(ndev); + err = setup_vq_resources(ndev, true); if (err) return err; } @@ -2888,7 +2913,7 @@ static int mlx5_vdpa_change_map(struct mlx5_vdpa_dev *mvdev, } /* reslock must be held for this function */ -static int setup_vq_resources(struct mlx5_vdpa_net *ndev) +static int setup_vq_resources(struct mlx5_vdpa_net *ndev, bool filled) { struct mlx5_vdpa_dev *mvdev = &ndev->mvdev; int err; @@ -2906,7 +2931,7 @@ static int setup_vq_resources(struct mlx5_vdpa_net *ndev) if (err) goto err_setup; - err = setup_virtqueues(mvdev); + err = setup_virtqueues(mvdev, filled); if (err) { mlx5_vdpa_warn(mvdev, "setup_virtqueues\n"); goto err_setup; @@ -3000,7 +3025,7 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); - err = setup_vq_resources(ndev); + err = setup_vq_resources(ndev, true); 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This change also allows calling resume_vq() to bring it from Init to Ready state (VQ initialization). Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 0a62ce0b4af8..adcc4d63cf83 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1557,11 +1557,31 @@ static void suspend_vqs(struct mlx5_vdpa_net *ndev) static void resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) { - if (!mvq->initialized || !is_resumable(ndev)) + if (!mvq->initialized) return; - if (mvq->fw_state != MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND) + switch (mvq->fw_state) { + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT: + /* Due to a FW quirk we need to modify the VQ fields first then change state. + * This should be fixed soon. After that, a single command can be used. + */ + if (modify_virtqueue(ndev, mvq, 0)) + mlx5_vdpa_warn(&ndev->mvdev, + "modify vq properties failed for vq %u\n", mvq->index); + break; + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND: + if (!is_resumable(ndev)) { + mlx5_vdpa_warn(&ndev->mvdev, "vq %d is not resumable\n", mvq->index); + return; + } + break; + case MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY: return; + default: + mlx5_vdpa_warn(&ndev->mvdev, "resume vq %u called from bad state %d\n", + mvq->index, mvq->fw_state); + return; + } if (modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY)) mlx5_vdpa_warn(&ndev->mvdev, "modify to resume failed for vq %u\n", mvq->index); From patchwork Wed Jun 26 10:26:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712582 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2059.outbound.protection.outlook.com [40.107.96.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51CC718754A; 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To keep compatibility, keep suspending or resuming VQs on error and return the last error code. The assumption here is that the error code would be the same. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 77 +++++++++++++++++++++++++++------------ 1 file changed, 54 insertions(+), 23 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index adcc4d63cf83..8ab5cf1bbc43 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1526,71 +1526,102 @@ static int setup_vq(struct mlx5_vdpa_net *ndev, return err; } -static void suspend_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) +static int suspend_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) { struct mlx5_virtq_attr attr; + int err; if (!mvq->initialized) - return; + return 0; if (mvq->fw_state != MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY) - return; + return 0; - if (modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND)) - mlx5_vdpa_warn(&ndev->mvdev, "modify to suspend failed\n"); + err = modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND); + if (err) { + mlx5_vdpa_warn(&ndev->mvdev, "modify to suspend failed, err: %d\n", err); + return err; + } - if (query_virtqueue(ndev, mvq, &attr)) { - mlx5_vdpa_warn(&ndev->mvdev, "failed to query virtqueue\n"); - return; + err = query_virtqueue(ndev, mvq, &attr); + if (err) { + mlx5_vdpa_warn(&ndev->mvdev, "failed to query virtqueue, err: %d\n", err); + return err; } + mvq->avail_idx = attr.available_index; mvq->used_idx = attr.used_index; + + return 0; } -static void suspend_vqs(struct mlx5_vdpa_net *ndev) +static int suspend_vqs(struct mlx5_vdpa_net *ndev) { + int err = 0; int i; - for (i = 0; i < ndev->cur_num_vqs; i++) - suspend_vq(ndev, &ndev->vqs[i]); + for (i = 0; i < ndev->cur_num_vqs; i++) { + int local_err = suspend_vq(ndev, &ndev->vqs[i]); + + err = local_err ? local_err : err; + } + + return err; } -static void resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) +static int resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq) { + int err; + if (!mvq->initialized) - return; + return 0; switch (mvq->fw_state) { case MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT: /* Due to a FW quirk we need to modify the VQ fields first then change state. * This should be fixed soon. After that, a single command can be used. */ - if (modify_virtqueue(ndev, mvq, 0)) + err = modify_virtqueue(ndev, mvq, 0); + if (err) { mlx5_vdpa_warn(&ndev->mvdev, - "modify vq properties failed for vq %u\n", mvq->index); + "modify vq properties failed for vq %u, err: %d\n", + mvq->index, err); + return err; + } break; case MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND: if (!is_resumable(ndev)) { mlx5_vdpa_warn(&ndev->mvdev, "vq %d is not resumable\n", mvq->index); - return; + return -EINVAL; } break; case MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY: - return; + return 0; default: mlx5_vdpa_warn(&ndev->mvdev, "resume vq %u called from bad state %d\n", mvq->index, mvq->fw_state); - return; + return -EINVAL; } - if (modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY)) - mlx5_vdpa_warn(&ndev->mvdev, "modify to resume failed for vq %u\n", mvq->index); + err = modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY); + if (err) + mlx5_vdpa_warn(&ndev->mvdev, "modify to resume failed for vq %u, err: %d\n", + mvq->index, err); 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E60:EE_|PH7PR12MB9202:EE_ X-MS-Office365-Filtering-Correlation-Id: 410338ca-e137-46c1-a3c3-08dc95caaec6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?rcXI5QFBWrJ8RRqtW0s/Ym0GZdqQ0GE?= =?utf-8?q?YpCWAj5GE7n5uMc+EYXCLE7pOtFvvsDnRPuBJnqBJ5i9VDPqeaPd96Ni4Nl/+OpBg?= =?utf-8?q?lZMK3SPDza4nMtYM1qbqkGaktXmADfWDA5OF0VGRnPZYhcuOE29SWBBlwNYWTAJ7Q?= =?utf-8?q?kvdfySZm6/FUhh8l//0B3sHDbkRfSDVDjDCzwdPrgRak7pIACIuUHIiJSaYFZ94oc?= =?utf-8?q?Ej+mN87gWXlWgRQnmgEprLMQ4+Xr0CABkM/VNSDEXJOdCcxd3w/Tkk+Ye8KGReq5o?= =?utf-8?q?KV48oA1p6brcsXzn0XGXUz30cX8HXmAFp3iEzdR/wYoTSFDBIiAxq+4HWd7WRFo7n?= =?utf-8?q?ckkHGnbIdRuAxMejVXdyE9WTAeb+n4/s3qXHSUCk41V4C7oDRJq4schOXjaOCkx5S?= =?utf-8?q?WAJ47eeDcyMOex0ebdSMUerHdbCqPrYgWKJiF29yUffwlmdEBpgCzpSqb+Q4hq9CO?= =?utf-8?q?Tci0C1Ly0J+ET5qsfdRKLIfseU3RyUL1PuHJUruJLN4qH8O5Hc5DQva2Ok4H41Fcy?= =?utf-8?q?wOJ5aSzzmx26IA87OuW9G1xI3PM3f0/O63mMpQSEnt9ElezD5hygssHXZVeCXOIwy?= =?utf-8?q?8fTvZ/dZ7ySnn2H2/u3hEcbZeavM9fE3K452KtEXl+WY/1V8kl+SDOEw/nStn8GQM?= =?utf-8?q?flS9QuizpK2C2Jg+pfclrL/dFXNRx3NDhb8dwdYJqpnJFLKKfb8snm2DiznVuupyE?= =?utf-8?q?IHY3TBVQRSEmorrPYCTS7A79kUFqpnadWA1VWpMlF7lktJ4GQjWaPBl1oiIeOtYnb?= =?utf-8?q?M7LdpsDd4vPzytjof6azycTnFRD0fk/EwUtCFszgXuy+4DxO43wEzHnlxhCoIX88M?= =?utf-8?q?EtdQLddi6Ko/K2LrncbRYCMjUEeaoHgxT7UR0G6X4y3GrfOfCOfhDcTEcxsY8wfWf?= =?utf-8?q?JK1Pq7iGWOXjuA7IvqvD9RbVW3kd+Xh4TjuFe0Z1umFFAWjpyBxWIUs9wrT2mqp76?= =?utf-8?q?DIFYMMZ52fyBt9RQoLX1Ifa3I1srfdqgsjFUFOiIwwcKtLsJg19kt2b2UafPBO2Fa?= =?utf-8?q?tUt1m3XYq/6R5G7XtAm+3O1469LOR75c39kZL225Viza4pahoYEbUlzTwHQ5EB+fk?= =?utf-8?q?Ahq2QJCVis5AxeeJUpCt7nwxONvZY6np2zqT6CpbVySMcqSTC9M1paAeEpeCFB7Xe?= =?utf-8?q?x4USvFJ15eZFsBjZnBRcir/eovCTNwtbfRs/VdPPT52MLm/8ikFjgrOb2Wn5h5i1J?= =?utf-8?q?raUMEv0E/YU4l7z5zEjrJ7vQEGY65SpVb2UvGOCf6p02CQL9MBTmslKSnbeOwdNxZ?= =?utf-8?q?+3OCHOMZhYGSOVPRYxW+wsf0cxcIBAc47Xm+ADVT/paZissKOjQ3pzWXLoKVVeuVP?= =?utf-8?q?jtIDwGZWok0kUpc5KNTLD1oaWlOE6WDO3g=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:12.6078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 410338ca-e137-46c1-a3c3-08dc95caaec6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E60.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9202 There are a few more places modifying the VQ to Ready directly. Let's consolidate them into resume_vq(). The redundant warnings for resume_vq() errors can also be dropped. There is one special case that needs to be handled for virtio-vdpa: the initialized flag must be set to true earlier in setup_vq() so that resume_vq() doesn't return early. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 8ab5cf1bbc43..e65d488f7a08 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -160,6 +160,7 @@ static void free_fixed_resources(struct mlx5_vdpa_net *ndev); static void mvqs_set_defaults(struct mlx5_vdpa_net *ndev); static int setup_vq_resources(struct mlx5_vdpa_net *ndev, bool filled); static void teardown_vq_resources(struct mlx5_vdpa_net *ndev); +static int resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq); static bool mlx5_vdpa_debug; @@ -1500,16 +1501,14 @@ static int setup_vq(struct mlx5_vdpa_net *ndev, if (err) goto err_vq; + mvq->initialized = true; + if (mvq->ready) { - err = modify_virtqueue_state(ndev, mvq, MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY); 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Reviewed-by: Cosmin Ratiu Reviewed-by: Zhu Yanjun Signed-off-by: Dragos Tatulea Reviewed-by: Eugenio Pérez --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index e65d488f7a08..ce1f6a1f36cd 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -3436,22 +3436,25 @@ static int mlx5_vdpa_suspend(struct vdpa_device *vdev) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + int err; mlx5_vdpa_info(mvdev, "suspending device\n"); down_write(&ndev->reslock); unregister_link_notifier(ndev); - suspend_vqs(ndev); + err = suspend_vqs(ndev); mlx5_vdpa_cvq_suspend(mvdev); mvdev->suspended = true; up_write(&ndev->reslock); - return 0; + + return err; } static int mlx5_vdpa_resume(struct vdpa_device *vdev) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|CH3PR12MB9078:EE_ X-MS-Office365-Filtering-Correlation-Id: f1b5f09c-f89a-486f-3efa-08dc95cab438 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|82310400024|7416012|376012|1800799022|36860700011; X-Microsoft-Antispam-Message-Info: =?utf-8?q?15hFon5AQXG/pyM+qD4PFgyesSOuSRd?= =?utf-8?q?aJYeCV3/pAyj4HOV8nNPGVRzfTVC+yX4KfXCg8H+rCekicxKRd58zezVU6d1HEviy?= =?utf-8?q?g7PpVBgq1LPaAuloua/VFvAz1gVX1RVgn6mVZlNARvR80eYcyE5kCbzmdBZby7h0U?= =?utf-8?q?DSdPsAmcgU5Aec8tVe7fOZ4m0l/WuP961bNVI85dti03csBzruJRYVtIaWFZa3cnR?= =?utf-8?q?3sZizVlzZ6d2F4F5fUfNtppNC+Ibzvc9UQNttOptabKs+btFIrgkj67WkQE/tPyT3?= =?utf-8?q?aCBbOA5Y3J6H/9XxVOPkg+XqEa9gFF5BOe4ar/OaP0a+i9BlZZ/v1IbG45b+CU6tS?= =?utf-8?q?N7jIV+05yK2o8G9MYD8ahDR5dSePf6ahWC17S17jOmjuwJ7jHcmzydZ+5f1pSBBAm?= =?utf-8?q?1eyVZ59jp+O4xJ2msKxhsIQ+0NkeLPlxF3Qcnd5C2TQZTq3qb+7Z+vCUHFRX6ZV2n?= =?utf-8?q?3IFm3l0VjD9WpH6fhbEq+ftjs3dRoLnR+G+4Kwd2hnVfdu1kdUOz9+rZBQUSjypJH?= =?utf-8?q?A7ou0cyABA/VjbDvpb0iitNDTF1Z4eBOT31Cq5ybfBwRvv3Y8ENdAyoU7OiEU+z3A?= =?utf-8?q?yhkRSZukWoiJOoPR7RlLojAhzzs344A5hPiEdNZtHX1JofIpLZjj7n62sp3ZecYfr?= =?utf-8?q?AROpthcgQZKOnAbbl3idqxaKY3PCvWK/BF5Jhmf67gU1GRFhTpIrfpoChNeKrJUkX?= =?utf-8?q?FNYM1mpyjbckw3Z4qFgCA91JP9nXeLMcV5dOK6G2IOD+5B16nsrD+G4Wsp7/sSssL?= =?utf-8?q?pkrPdHyEATWGRkSx/FDCC2jotJSMRw4H8pzgEjU/WrNhwrxCPAp7v1VyYPTyXT4Xz?= =?utf-8?q?SGTKJ5AlumYw1THiHuiWegACX7xd2QiIS4tcT8jnhAHSuL2UjRedNFV95EuthpiDr?= =?utf-8?q?2I1gmAx1Oim/eLDzji6CmZK8oqRtvKwvNgpdIZNUR0LriXaFEqAgTQ3q511+R8jrR?= =?utf-8?q?6RSumZQTih2xl0ZGKFny8j0E1QWtzzn8C9xCLCGfnco5F9g6mZ60gWIGCTXhZrdoN?= =?utf-8?q?vweZLuZFEJ+whI6SWvPxj7FCOheOBZHHnyzt5ScQ8YLuXV+V8YKPUbW4kgGy32tRh?= =?utf-8?q?6I3Uxwsiw3LLbBRTX2jp1CVV/dmTjM3MeVYMDlY3Lspk70lYW4bkraMASaCDMP0Wv?= =?utf-8?q?K2jFz+UnxjBHAI5kd0CXSZncwQubmLqtQlt65dXE6s/vg2BKe/XcT8uRLNJjdh7KY?= =?utf-8?q?7ZP89G0MMsgvtvmsDo0J8zxQlArmYrSXMopirjtHZxSdhsSiU6cABBovyUIvtw2LG?= =?utf-8?q?H0XewfgG4T96AF1oImotC5NVgv0zUOAA4kefE7FKCSTpPbT8ewxyxtfDJVc5b/IPf?= =?utf-8?q?DBfeC/pFg3loDODHEQLisHhr+b3CuQzYEg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(82310400024)(7416012)(376012)(1800799022)(36860700011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:21.8347 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1b5f09c-f89a-486f-3efa-08dc95cab438 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9078 Resume a VQ if it is already created when the number of VQ pairs increases. This is done in preparation for VQ pre-creation which is coming in a later patch. It is necessary because calling setup_vq() on an already created VQ will return early and will not enable the queue. For symmetry, suspend a VQ instead of tearing it down when the number of VQ pairs decreases. But only if the resume operation is supported. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index ce1f6a1f36cd..324604b16b91 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2130,14 +2130,22 @@ static int change_num_qps(struct mlx5_vdpa_dev *mvdev, int newqps) if (err) return err; - for (i = ndev->cur_num_vqs - 1; i >= 2 * newqps; i--) - teardown_vq(ndev, &ndev->vqs[i]); + for (i = ndev->cur_num_vqs - 1; i >= 2 * newqps; i--) { + struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[i]; + + if (is_resumable(ndev)) + suspend_vq(ndev, mvq); + else + teardown_vq(ndev, mvq); + } ndev->cur_num_vqs = 2 * newqps; } else { ndev->cur_num_vqs = 2 * newqps; for (i = cur_qps * 2; i < 2 * newqps; i++) { - err = setup_vq(ndev, &ndev->vqs[i], true); + struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[i]; 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Wed, 26 Jun 2024 03:28:13 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:28:12 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:28:09 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:57 +0300 Subject: [PATCH vhost v2 21/24] vdpa/mlx5: Pre-create hardware VQs at vdpa .dev_add time Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-21-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|BL3PR12MB6450:EE_ X-MS-Office365-Filtering-Correlation-Id: f55e93d6-11a9-4267-a025-08dc95cab5ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|376012|7416012|1800799022|82310400024; X-Microsoft-Antispam-Message-Info: =?utf-8?q?tWs1Y4tYg6IY1fXc9xMugkbxp6eENEC?= =?utf-8?q?pn8OrprqN+DO4p0nMak06uOQhQSiKl8/8/cKnTURC3NE0Q3CjwNkVVhX/0aqDl4qG?= =?utf-8?q?aBu61ULTeulcbQ9CQg5vTCWfZxJ2Q2zUHIaWajJ81FpucoeA454dsKNircaMWIye9?= =?utf-8?q?epnt0uC3N3iXyJRlrHN8ipW1Emw3d4nDWiXkZ7UyvAtdGRBW3wmFfX0iOqBYNUfEj?= =?utf-8?q?O8GxN5K6n86qE9xzgE+gE71xDmOGaHCp/Opni442bB+t0WnB1veOHiFi7ElCdo3hQ?= =?utf-8?q?+0uvZHWFvOLjpbdetLXwxTLtZSR/fVna3txAjV8O3oDoB/0/3xVt934uJVO6bFRsJ?= =?utf-8?q?AgQpqAXpuYTtTRNKFO+mxWoU1RyjPd4gDaEzKDZNIDI8dGqTu0kMW6xVqca9/rBHh?= =?utf-8?q?a9aPiPuPHnyFaokB/19CBy0h2qlhSRN4CTViHHNGBCLHTFXXTcTogP2QiLFu0+KZX?= =?utf-8?q?CIrjI9fHj223O7J3QnU+S/VYdR6LN135dyWdGsdHMLRLonIUOgDQAnCmjbqW52+eQ?= =?utf-8?q?nInKTfOHFGbu8+CpcbJYzSxKDUlBzkCOV/SeO3VXHuAmuHDXZbJVQZEu4oPp8ra8f?= =?utf-8?q?pzH8QKeKE21C3iumOsxnj7WenOi+WkRXnISbb40rpRc3wNe1SvMrCL84+ldrZNi/O?= =?utf-8?q?bzRgME7q50EFYLTDWNc0PZ0OPPsFyY2tImPYFrvKTKyFZEjRBRTm3SJAZxoZSaOkv?= =?utf-8?q?xCI5SvWxZfUNgPCS6P0TRKKY/N6lDGXEXrV56uQv8UHCdFQDxgLsbiaAkrM0zNmam?= =?utf-8?q?56Qs/skcrVt1QtF+SAr+Je6STfb7hirDe7dhUXYHhFI9qitqyQZpMHvlHhDKf12WE?= =?utf-8?q?S7Yfulgn6vWVJuFWAzW++GML1g6YRe6bVYnD0yT6rlYZN37Dht5f8kgTjcpb5j0lB?= =?utf-8?q?DaK+CUB4bsEJr/3XxwUdK6HgGutMDYxzDKAD8TTJO/kUlSVn5bg6kfcbp5tdK35wl?= =?utf-8?q?X5LkUjaolu0LKzd5JDhuuWg+G+j8MPHrHcmOw/Vri8eKZPGqGZhQ35Rp3T0P+4DY1?= =?utf-8?q?ef9eAOB0SMOvtPny78SyO6xVlHeUN9rCg0MIJ+uuMDcE632NFfGkuSM88OMHMqMt+?= =?utf-8?q?fiipgbm+CP5CEqyoSfHnI6aweiFG3FzMiAwdIuf593BQtChkOfjfuB+Kj5a1nV/zc?= =?utf-8?q?cSvpqk+2IzErucV+X+nAHo5gsCPGdjF0iNfGE5ND7DIaNDLguQJpW7A7zli9a0KWL?= =?utf-8?q?7UXP9W/1Ao/R9uaLEcd6yJ7pDlszO6jOWcNUuupVemUJ9D8VxvOlbYcMDK5vUAKSm?= =?utf-8?q?CkzUshseFf1s/B3YQW3tzb4yBP3pMPRm2kihYgG8vmLIkNSC/Pu5hS0HXpQCM4k9+?= =?utf-8?q?ULVVjIIXnRWM+VD+avDKFrUYIxmS4Q8BYVwvSDfH9+MRhlxaLFShviQTfbbGXu31j?= =?utf-8?q?haYi78T8Vb5?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(376012)(7416012)(1800799022)(82310400024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:24.8816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f55e93d6-11a9-4267-a025-08dc95cab5ff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6450 Currently, hardware VQs are created right when the vdpa device gets into DRIVER_OK state. That is easier because most of the VQ state is known by then. This patch switches to creating all VQs and their associated resources at device creation time. The motivation is to reduce the vdpa device live migration downtime by moving the expensive operation of creating all the hardware VQs and their associated resources out of downtime on the destination VM. The VQs are now created in a blank state. The VQ configuration will happen later, on DRIVER_OK. Then the configuration will be applied when the VQs are moved to the Ready state. When .set_vq_ready() is called on a VQ before DRIVER_OK, special care is needed: now that the VQ is already created a resume_vq() will be triggered too early when no mr has been configured yet. Skip calling resume_vq() in this case, let it be handled during DRIVER_OK. For virtio-vdpa, the device configuration is done earlier during .vdpa_dev_add() by vdpa_register_device(). Avoid calling setup_vq_resources() a second time in that case. On a 64 CPU, 256 GB VM with 1 vDPA device of 16 VQps, the full VQ resource creation + resume time was ~370ms. Now it's down to 60 ms (only VQ config and resume). The measurements were done on a ConnectX6DX based vDPA device. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 324604b16b91..8ef703f4c23d 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2444,7 +2444,7 @@ static void mlx5_vdpa_set_vq_ready(struct vdpa_device *vdev, u16 idx, bool ready mvq = &ndev->vqs[idx]; if (!ready) { suspend_vq(ndev, mvq); - } else { + } else if (mvdev->status & VIRTIO_CONFIG_S_DRIVER_OK) { if (resume_vq(ndev, mvq)) ready = false; } @@ -3078,10 +3078,18 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); - err = setup_vq_resources(ndev, true); - if (err) { - mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); - goto err_driver; + if (ndev->setup) { + err = resume_vqs(ndev); + if (err) { + mlx5_vdpa_warn(mvdev, "failed to resume VQs\n"); + goto err_driver; + } + } else { + err = setup_vq_resources(ndev, true); + if (err) { + mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); + goto err_driver; + } } } else { mlx5_vdpa_warn(mvdev, "did not expect DRIVER_OK to be cleared\n"); @@ -3142,6 +3150,7 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) if (mlx5_vdpa_create_dma_mr(mvdev)) mlx5_vdpa_warn(mvdev, "create MR failed\n"); } + setup_vq_resources(ndev, false); up_write(&ndev->reslock); return 0; @@ -3835,8 +3844,21 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, goto err_reg; mgtdev->ndev = ndev; + + /* For virtio-vdpa, the device was set up during device register. */ + if (ndev->setup) + return 0; + + down_write(&ndev->reslock); + err = setup_vq_resources(ndev, false); + up_write(&ndev->reslock); + if (err) + goto err_setup_vq_res; + return 0; +err_setup_vq_res: + _vdpa_unregister_device(&mvdev->vdev); err_reg: destroy_workqueue(mvdev->wq); err_res2: @@ -3862,6 +3884,11 @@ static void mlx5_vdpa_dev_del(struct vdpa_mgmt_dev *v_mdev, struct vdpa_device * unregister_link_notifier(ndev); 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Wed, 26 Jun 2024 03:28:17 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:28:16 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:28:13 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:58 +0300 Subject: [PATCH vhost v2 22/24] vdpa/mlx5: Re-create HW VQs under certain conditions Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-22-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|SA1PR12MB8985:EE_ X-MS-Office365-Filtering-Correlation-Id: b23490ed-89d9-4fbe-6f6f-08dc95cab8ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|82310400024|7416012|376012|36860700011|1800799022; X-Microsoft-Antispam-Message-Info: =?utf-8?q?MS9LVFiRUVvnNtBFn+WpY2TPYrG1YSL?= =?utf-8?q?53RYfH3T4PFl2avOSPFCY3T2nWnUG3wigKsj36LREYpzj8Q6nZ6e2Nx6yb4HOea6r?= =?utf-8?q?0EBu4+lrxeheIMqya0UFUALQFz4im42i1r+Nvs6XDQzM4+eXvY1zTOLU3FIqNfEw4?= =?utf-8?q?zBvmXucb7ZN56cXpseVALsioZo7GjGNJQC+5zuzIyvwkGQndsc3z/ki9fVGd7Sb/a?= =?utf-8?q?lPPgVDxMp50jJdPCVyTBXRN4jGUxIhmtMK1hLI/x/QBl5t/HfOxm76opmGTdoh65l?= =?utf-8?q?K2g7QmQmTA2dASauLTgjgxBvVrrgOfQR2OGWtNLOpk8WmHpa8VPnZnOIu6UGkqEhZ?= =?utf-8?q?Sn7ajC1DSSJLDA+A58zeQNZhPiBkOnwWjdHn0b5Akkt3Fo4KCeVpRBh4HO1avB22i?= =?utf-8?q?iZsYgaWO/I4W4r+MRudwEiknsYPo8lQZTjr53bTEHhveW1RtI+wIiwLRhyXwLemO9?= =?utf-8?q?VYbGQh7Wtv5Fdgl9OCruVSxt9Vc9olnxHNefgyf94+Rkh99gELbxXPA6hwiDIBL7Z?= =?utf-8?q?VL8UEL8EyWEZSwSVHuJgoNELOelJ0wjlumprTbuPzsJly+3acKhFZn1CcK+7XFpEn?= =?utf-8?q?Rn+y618Bl9TACVX7Fot7NoGxBccLQHpt8x8Leg6uUEViERBxFnSxXh1W7U0mxwcJY?= =?utf-8?q?go01yUnCtxuZndn2fQHTqjtUclUscdcYLPXDfhqQt9+zpq0u85y8SzYv6ubHuGkhh?= =?utf-8?q?WFa9m6Wr8v2/0LsLeQx7Hkly7Zvv7zqVn4b4lz+LTwHo8XeYYd5Xf8iQXXDgohyxk?= =?utf-8?q?3Eb7vNlWxz50h/rqvNxPcefdBRmSlabhFrPyMBL+oDTPaoeumtTWXQMMnbZU5+bdM?= =?utf-8?q?EufalWUnWhEsnJYUTmXUiSE9DImbgQxv0sQeT5xaSXdupauxg9i/qcLVVQSrKil5S?= =?utf-8?q?mOvLu09WfS6DDHhCUbkj7U96ZdT7aWnz9Xb3LKMfVVq0I1azDKMG+DoZGkhptihri?= =?utf-8?q?Nn9y+ZAAccu5PA/0BNJv15N1N2jrEBKc3XuDHYp7JcNJxREtrSQhgt5RDz6iIai1I?= =?utf-8?q?kBHrxrEdKYI0Lnf6iUHXrz0fNtHMEJdLFsDJpdQlWB5gmuxRuV5ErFcn1T9nhL89E?= =?utf-8?q?pN3oVBxMhyzcqvtDYl0LxhHVRlFqGUN9OnpJvV0V+JmD8aMGnMjWCgh6Ppfo6clqy?= =?utf-8?q?KqiTaKHL6+fH9oYDXUh1eC1a6rv9uWjnr+ARKrX0+Ff2tr+w2CEmv0ZgpMmpS4kaY?= =?utf-8?q?EMcpE6oRgs5xiNvXc0zrN/fcQBPVnbpBx8KkFi83+XHu1SnQG4Ys18yR0U63QXTpT?= =?utf-8?q?dcDqLLGZCKpsXYwHAj0P864le2pj4r2CSWE56Ra8x16xd1wYWDdgvXzpvBcc4Unb5?= =?utf-8?q?VT3lS6USIaj2HeM+0iZwzqlNSt4cq86U6wGlFIsxeRCIMSifUAbqpDVcM0d3GTqt2?= =?utf-8?q?Nr3+etbndSI?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230038)(82310400024)(7416012)(376012)(36860700011)(1800799022);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:29.4881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b23490ed-89d9-4fbe-6f6f-08dc95cab8ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8985 There are a few conditions under which the hardware VQs need a full teardown and setup: - VQ size changed to something else than default value. Hardware VQ size modification is not supported. - User turns off certain device features: mergeable buffers, checksum virtio 1.0 compliance. In these cases, the TIR and RQT need to be re-created. Add a needs_teardown configuration variable and set it when detecting the above scenarios. On next DRIVER_OK, the resources will be torn down first. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 15 +++++++++++++++ drivers/vdpa/mlx5/net/mlx5_vnet.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 8ef703f4c23d..ea4bfd9afce9 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2390,6 +2390,7 @@ static void mlx5_vdpa_set_vq_num(struct vdpa_device *vdev, u16 idx, u32 num) } mvq = &ndev->vqs[idx]; + ndev->needs_teardown = num != mvq->num_ent; mvq->num_ent = num; } @@ -2800,6 +2801,7 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); u64 old_features = mvdev->actual_features; + u64 diff_features; int err; print_features(mvdev, features, true); @@ -2822,6 +2824,14 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_device *vdev, u64 features) } } + /* When below features diverge from initial device features, VQs need a full teardown. */ +#define NEEDS_TEARDOWN_MASK (BIT_ULL(VIRTIO_NET_F_MRG_RXBUF) | \ + BIT_ULL(VIRTIO_NET_F_CSUM) | \ + BIT_ULL(VIRTIO_F_VERSION_1)) + + diff_features = mvdev->mlx_features ^ mvdev->actual_features; + ndev->needs_teardown = !!(diff_features & NEEDS_TEARDOWN_MASK); + update_cvq_info(mvdev); return err; } @@ -3038,6 +3048,7 @@ static void teardown_vq_resources(struct mlx5_vdpa_net *ndev) destroy_rqt(ndev); teardown_virtqueues(ndev); ndev->setup = false; + ndev->needs_teardown = false; } static int setup_cvq_vring(struct mlx5_vdpa_dev *mvdev) @@ -3078,6 +3089,10 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); + + if (ndev->needs_teardown) + teardown_vq_resources(ndev); + if (ndev->setup) { err = resume_vqs(ndev); if (err) { diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.h b/drivers/vdpa/mlx5/net/mlx5_vnet.h index 90b556a57971..00e79a7d0be8 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.h +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.h @@ -56,6 +56,7 @@ struct mlx5_vdpa_net { struct dentry *rx_dent; struct dentry *rx_table_dent; bool setup; + bool needs_teardown; u32 cur_num_vqs; u32 rqt_size; bool nb_registered; From patchwork Wed Jun 26 10:26:59 2024 Content-Type: text/plain; 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Wed, 26 Jun 2024 03:28:17 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:59 +0300 Subject: [PATCH vhost v2 23/24] vdpa/mlx5: Don't reset VQs more than necessary Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-23-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|IA0PR12MB8304:EE_ X-MS-Office365-Filtering-Correlation-Id: ca6f368a-d223-42ad-efa2-08dc95cabafc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|1800799022|7416012|82310400024|376012; X-Microsoft-Antispam-Message-Info: =?utf-8?q?yVMy4U1ywP4uTJNfm+8Ec5O0aWEGbZZ?= =?utf-8?q?EkljXBX+3BUMtMjsTfBeZxDXrpn3J/G2jr1aMUMDsISP5ksFQlWl+Aw+c6j40+85F?= =?utf-8?q?8iURQvxvm81NrZWXWmCssb69hpk8Lwr+CKDvl2LMaLosv+mNm7QlhxMz7TFu9HXZE?= =?utf-8?q?atPdKHCTa9jXS8fe1Hq6ThQeS6aI9Lz1HrJwUUzcbzUr5rVlcdbfiubHDNFMS2r/C?= =?utf-8?q?hBlaIYce81fxyRYoeNnlvWE67OHZszlmWYEQ/FQH8cGhByMSGob2jTGNEreJhP8YZ?= =?utf-8?q?GKQ6Xk64UaSv3LF8tI3jxNkvxiVKNfqSbqxeXrq/8qjJzubaa3eteHRu9P3nh2Ggu?= =?utf-8?q?KIrGeYggKb3PkCKDAhnox5dALSuzX2yo1zq0BtYmUwHu2GzCPnBa6YBtabn3TTwab?= =?utf-8?q?dYRRYHqzRLLrL5BrLPV5RcnS8fGznwPcnrgWtdLGzTNq4ww3DTJqrY9P2uHyo442z?= =?utf-8?q?np7vtsyLSp1bTEOpHEDfrn0QDNqLp9BsV7DfpYo4bt+1laHPUweiZF2ltfO4+Oz+Q?= =?utf-8?q?9UDh/yPGfsF2YpTqVurl+oF96/VoEbxjuZP3I5jOUnoDZZHQhrE517fMQ2IZ1XIP9?= =?utf-8?q?t6x9DJ7h+C3wVnON14hSUnD8XF4RQ28ejt2r8Vm5bZfTZgd/xQnhkTx9u0Q2l7qG0?= =?utf-8?q?+Z8FetIpyaWYS7SyeBOj0Fqv6lxt1tIaSJ/60ZbqoPr4WLa+t42eQymocIG15UBAK?= =?utf-8?q?j9InlHIfBcKKVTGTlliL+WSfuFXzxpXsJNQXrGw4CXWiiIbAzFxAomP2siAT37roK?= =?utf-8?q?NSsjSZUDQwkhW6Xk4SANUU22J95TQiJjSipwICXib6llekP7IAFRC1JmYUItXceI9?= =?utf-8?q?zRZE+EYVmFF8k0brC96OOKDUzvKR6VibHEGL03xEv3tAKF9NQO3d2mO/XdWeLabp/?= =?utf-8?q?SFXVowmv4Ta8jddMq9cbZIdqEeioirBGZ5DDJp+AHP8oTbcmVeT1Gw3eEgqStc3/c?= =?utf-8?q?y1CUUmsgJoA3xwOHFFwXDNYo6IuQRLR3JBWuu/+ROpVKkW6VHZ9LZe5SMlABPLFlS?= =?utf-8?q?F3K+97bfz9L/7v8YUoFKM+hD6yyGU6onapnzG2SMUqhQveIzsmsKpCx9DBjYiEut+?= =?utf-8?q?wFIlUcITJpED9USJVbN6FfMd+akQ9jHCgZeHe+8hU7kFb9vF99KbXa9MgWR1eumwk?= =?utf-8?q?HyTsM8ZzhTPkLTLUMacYHOC7VYIyzF5Ygl/8Xt1Ag5XfC/oLh/0BBMGPPI0ls9w6P?= =?utf-8?q?Wv0Y/gIQzaOiQ0rxgR5TmuznuuZ8d4GiOqTdsxfD2orpGGGD8/gHsUe4THmJuEZeF?= =?utf-8?q?EQEmjKGQpcjDtAwHdp5Z/6Uvzi3iZlNFhF3TrrHkbhnwxqwQxmJuuLsSB3rgEKbUq?= =?utf-8?q?w90JPu6jATR4EBFOOBTzoITrZ195G5g8QA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(1800799022)(7416012)(82310400024)(376012);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:33.2057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca6f368a-d223-42ad-efa2-08dc95cabafc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8304 The vdpa device can be reset many times in sequence without any significant state changes in between. Previously this was not a problem: VQs were torn down only on first reset. But after VQ pre-creation was introduced, each reset will delete and re-create the hardware VQs and their associated resources. To solve this problem, avoid resetting hardware VQs if the VQs are still in a blank state. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index ea4bfd9afce9..573dc01df8c3 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -3134,18 +3134,41 @@ static void init_group_to_asid_map(struct mlx5_vdpa_dev *mvdev) mvdev->group2asid[i] = 0; } +static bool needs_vqs_reset(const struct mlx5_vdpa_dev *mvdev) +{ + struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + struct mlx5_vdpa_virtqueue *mvq = &ndev->vqs[0]; + + if (mvdev->status & VIRTIO_CONFIG_S_DRIVER_OK) + return true; + + if (mvq->fw_state != MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT) + return true; + + return mvq->modified_fields & ( + MLX5_VIRTQ_MODIFY_MASK_STATE | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_ADDRS | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_AVAIL_IDX | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX + ); +} + static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) { struct mlx5_vdpa_dev *mvdev = to_mvdev(vdev); struct mlx5_vdpa_net *ndev = to_mlx5_vdpa_ndev(mvdev); + bool vq_reset; print_status(mvdev, 0, true); mlx5_vdpa_info(mvdev, "performing device reset\n"); down_write(&ndev->reslock); unregister_link_notifier(ndev); - teardown_vq_resources(ndev); - mvqs_set_defaults(ndev); + vq_reset = needs_vqs_reset(mvdev); + if (vq_reset) { + teardown_vq_resources(ndev); + mvqs_set_defaults(ndev); + } if (flags & VDPA_RESET_F_CLEAN_MAP) mlx5_vdpa_destroy_mr_resources(&ndev->mvdev); @@ -3165,7 +3188,8 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) if (mlx5_vdpa_create_dma_mr(mvdev)) mlx5_vdpa_warn(mvdev, "create MR failed\n"); } - setup_vq_resources(ndev, false); + if (vq_reset) + setup_vq_resources(ndev, false); up_write(&ndev->reslock); return 0; From patchwork Wed Jun 26 10:27:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13712589 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2054.outbound.protection.outlook.com [40.107.94.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F4AE18EFEB; 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Wed, 26 Jun 2024 03:28:25 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 26 Jun 2024 03:28:24 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 26 Jun 2024 03:28:21 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:27:00 +0300 Subject: [PATCH vhost v2 24/24] vdpa/mlx5: Don't enable non-active VQs in .set_vq_ready() Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-stage-vdpa-vq-precreate-v2-24-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. 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Reviewed-by: Cosmin Ratiu Acked-by: Eugenio Pérez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 573dc01df8c3..fa78e8288ebb 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -1575,6 +1575,9 @@ static int resume_vq(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtqueue *mvq if (!mvq->initialized) return 0; + if (mvq->index >= ndev->cur_num_vqs) + return 0; + switch (mvq->fw_state) { case MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT: /* Due to a FW quirk we need to modify the VQ fields first then change state.