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Signed-off-by: Stanimir Varbanov --- .../brcm,bcm2712-msix.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml new file mode 100644 index 000000000000..ca610e4467d9 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom bcm2712 MSI-X Interrupt Peripheral support + +maintainers: + - Stanimir Varbanov + +description: > + This interrupt controller is used to provide intterupt vectors to the + generic interrupt controller (GIC) on bcm2712. It will be used as + external MSI-X controller for PCIe root complex. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - "brcm,bcm2712-mip-intc" + reg: + maxItems: 1 + description: > + Specifies the base physical address and size of the registers + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + msi-controller: true + + brcm,msi-base-spi: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SGI number that MSIs start. + + brcm,msi-num-spis: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of SGIs for MSIs. + + brcm,msi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Shift the allocated MSIs up by N. + + brcm,msi-pci-addr: + $ref: /schemas/types.yaml#/definitions/uint64 + description: MSI-X message address. + +additionalProperties: false + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - msi-controller + +examples: + - | + msi-controller@130000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x00130000 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <128>; + brcm,msi-num-spis = <64>; + brcm,msi-offset = <0>; + brcm,msi-pci-addr = <0xff 0xfffff000>; + }; From patchwork Wed Jun 26 10:45:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13712658 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40AD01662E5; Wed, 26 Jun 2024 10:46:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398805; cv=none; b=omx52adXeVDpEIo3pLVmqORDleyxS4f8VX4sUqpu6J7uzC5/iA7uLFXqn4d4OMIUsHGzwPF1Yy4Cd+HFcCcZBtJWxzsOYUmr1ZLRV1YIoVsqssKW4J+WkdJw14rC1j96v1pv4S/hi4S/5NtEfRY71bi/+USwo7xOWNYnGNeRtyw= ARC-Message-Signature: i=1; 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Wed, 26 Jun 2024 10:46:41 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH 2/7] dt-bindings: PCI: brcmstb: Update bindings for PCIe on bcm2712 Date: Wed, 26 Jun 2024 13:45:39 +0300 Message-ID: <20240626104544.14233-3-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240626104544.14233-1-svarbanov@suse.de> References: <20240626104544.14233-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spamd-Result: default: False [-1.30 / 50.00]; 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Signed-off-by: Stanimir Varbanov Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/pci/brcm,stb-pcie.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 22491f7f8852..7c7b3d25ff89 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - brcm,bcm2711-pcie # The Raspberry Pi 4 + - brcm,bcm2712-pcie # Raspberry Pi 5 - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - brcm,bcm7278-pcie # Broadcom 7278 Arm @@ -147,6 +148,22 @@ allOf: - resets - reset-names + - if: + properties: + compatible: + contains: + const: brcm,bcm2712-pcie + then: + properties: + resets: + items: + - description: phandle pointing to the RESCAL reset controller + - description: phandle pointing to the bridge reset controller + reset-names: + items: + - const: rescal + - const: bridge + unevaluatedProperties: false examples: From patchwork Wed Jun 26 10:45:40 2024 Content-Type: text/plain; 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BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.de:email]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FREEMAIL_ENVRCPT(0.00)[gmail.com] Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) hardware block found in bcm2712. The interrupt controller is used to handle MSI-X interrupts from peripherials behind PCIe endpoints like RP1 south bridge found in RPi5. There are two MIPs on bcm2712, the first has 64 consecutive SPIs assigned to 64 output vectors, and the second has 17 SPIs, but only 8 of them are consecutive starting at the 8th output vector. Signed-off-by: Stanimir Varbanov --- drivers/irqchip/Kconfig | 12 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-bcm2712-mip.c | 287 ++++++++++++++++++++++++++++++ 3 files changed, 300 insertions(+) create mode 100644 drivers/irqchip/irq-bcm2712-mip.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 72c07a12f5e1..4297bd1c0e13 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -111,6 +111,18 @@ config I8259 bool select IRQ_DOMAIN +config BCM2712_MIP + bool "Broadcom BCM2712 MSI-X Interrupt Peripheral support" + depends on ARCH_BRCMSTB + default ARCH_BRCMSTB + depends on ARM_GIC + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + help + Enable support for the Broadcom BCM2712 MSI-X target peripheral + (MIP) needed by PCIe brcmstb to handle MSI-X interrupts on + Raspberry Pi 5. + config BCM6345_L1_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ec4a18380998..7df7b7338a9f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o +obj-$(CONFIG_BCM2712_MIP) += irq-bcm2712-mip.o obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o diff --git a/drivers/irqchip/irq-bcm2712-mip.c b/drivers/irqchip/irq-bcm2712-mip.c new file mode 100644 index 000000000000..c95fef488d6d --- /dev/null +++ b/drivers/irqchip/irq-bcm2712-mip.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Raspberry Pi Ltd., All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MIP_INT_RAISED 0x00 +#define MIP_INT_CLEARED 0x10 +#define MIP_INT_CFGL_HOST 0x20 +#define MIP_INT_CFGH_HOST 0x30 +#define MIP_INT_MASKL_HOST 0x40 +#define MIP_INT_MASKH_HOST 0x50 +#define MIP_INT_MASKL_VPU 0x60 +#define MIP_INT_MASKH_VPU 0x70 +#define MIP_INT_STATUSL_HOST 0x80 +#define MIP_INT_STATUSH_HOST 0x90 +#define MIP_INT_STATUSL_VPU 0xa0 +#define MIP_INT_STATUSH_VPU 0xb0 + +struct mip_priv { + /* used to protect alloc/free bitmap ops */ + spinlock_t msi_map_lock; + void __iomem *base; + phys_addr_t msg_addr; + u32 msi_base; /* The SGI number that MSIs start */ + u32 num_msis; /* The number of SGIs for MSIs */ + u32 msi_offset; /* Shift the allocated msi up by N */ + unsigned long *msi_map; +}; + +static void mip_mask_msi_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void mip_unmask_msi_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct mip_priv *priv = irq_data_get_irq_chip_data(d); + + msg->address_hi = upper_32_bits(priv->msg_addr); + msg->address_lo = lower_32_bits(priv->msg_addr); + msg->data = d->hwirq; +} + +static struct irq_chip mip_msi_irq_chip = { + .name = "MIP-MSI", + .irq_unmask = mip_unmask_msi_irq, + .irq_mask = mip_mask_msi_irq, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, +}; + +static struct msi_domain_info mip_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), + .chip = &mip_msi_irq_chip, +}; + +static struct irq_chip mip_middle_irq_chip = { + .name = "MIP", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_compose_msi_msg = mip_compose_msi_msg, +}; + +static int mip_allocate_sgi(struct mip_priv *priv, int nr_irqs) +{ + int irq; + + spin_lock(&priv->msi_map_lock); + irq = bitmap_find_free_region(priv->msi_map, priv->num_msis, + ilog2(nr_irqs)); + spin_unlock(&priv->msi_map_lock); + + if (irq < 0) + return -ENOSPC; + + return irq + priv->msi_offset; +} + +static void mip_free_sgi(struct mip_priv *priv, unsigned int sgi, int nr_irqs) +{ + unsigned int irq = sgi - priv->msi_offset; + + if (sgi < priv->msi_offset) { + pr_err("MIP: sgi should be greater than %u\n", priv->msi_offset); + return; + } + + spin_lock(&priv->msi_map_lock); + bitmap_release_region(priv->msi_map, irq, ilog2(nr_irqs)); + spin_unlock(&priv->msi_map_lock); +} + +static int mip_gic_domain_alloc(struct irq_domain *domain, unsigned int virq, + int sgi) +{ + struct mip_priv *priv = domain->host_data; + struct irq_fwspec fwspec; + struct irq_data *irqd; + int ret; + + if (!is_of_node(domain->parent->fwnode)) + return -EINVAL; + + fwspec.fwnode = domain->parent->fwnode; + fwspec.param_count = 3; + fwspec.param[0] = 0; + fwspec.param[1] = sgi + priv->msi_base; + fwspec.param[2] = IRQ_TYPE_EDGE_RISING; + + ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); + if (ret) + return ret; + + irqd = irq_domain_get_irq_data(domain->parent, virq); + irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING); + + return 0; +} + +static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct mip_priv *priv = domain->host_data; + struct irq_data *irqd; + int hwirq, ret, i; + + hwirq = mip_allocate_sgi(priv, nr_irqs); + if (hwirq < 0) + return hwirq; + + for (i = 0; i < nr_irqs; i++) { + ret = mip_gic_domain_alloc(domain, virq + i, hwirq + i); + if (ret) + goto err_sgi; + + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &mip_middle_irq_chip, priv); + irqd = irq_get_irq_data(virq + i); + irqd_set_single_target(irqd); + irqd_set_affinity_on_activate(irqd); + } + + return 0; + +err_sgi: + irq_domain_free_irqs_parent(domain, virq, i - 1); + mip_free_sgi(priv, hwirq, nr_irqs); + return ret; +} + +static void mip_middle_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct mip_priv *priv = irq_data_get_irq_chip_data(d); + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + mip_free_sgi(priv, d->hwirq, nr_irqs); +} + +static const struct irq_domain_ops mip_middle_domain_ops = { + .alloc = mip_middle_domain_alloc, + .free = mip_middle_domain_free, +}; + +static int mip_init_domains(struct mip_priv *priv, struct device_node *node) +{ + struct irq_domain *middle_domain, *msi_domain, *gic_domain; + struct device_node *gic_node; + + gic_node = of_irq_find_parent(node); + if (!gic_node) + return -ENODEV; + + gic_domain = irq_find_host(gic_node); + of_node_put(gic_node); + if (!gic_domain) + return -ENXIO; + + middle_domain = irq_domain_add_hierarchy(gic_domain, 0, 0, NULL, + &mip_middle_domain_ops, + priv); + if (!middle_domain) + return -ENOMEM; + + msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node), + &mip_msi_domain_info, + middle_domain); + if (!msi_domain) { + irq_domain_remove(middle_domain); + return -ENOMEM; + } + + return 0; +} + +static int __init mip_of_msi_init(struct device_node *node, + struct device_node *parent) +{ + struct mip_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->msi_map_lock); + + if (of_property_read_u32(node, "brcm,msi-base-spi", &priv->msi_base)) { + ret = -EINVAL; + goto err_priv; + } + + if (of_property_read_u32(node, "brcm,msi-num-spis", &priv->num_msis)) { + ret = -EINVAL; + goto err_priv; + } + + if (of_property_read_u32(node, "brcm,msi-offset", &priv->msi_offset)) + priv->msi_offset = 0; + + if (of_property_read_u64(node, "brcm,msi-pci-addr", &priv->msg_addr)) { + ret = -EINVAL; + goto err_priv; + } + + priv->base = of_iomap(node, 0); + if (!priv->base) { + ret = -ENOMEM; + goto err_priv; + } + + priv->msi_map = bitmap_zalloc(priv->num_msis, GFP_KERNEL); + if (!priv->msi_map) { + ret = -ENOMEM; + goto err_base; + } + + /* + * Begin with all MSI-X masked in for the host, masked out for the + * VPU, and edge-triggered. + */ + writel(0, priv->base + MIP_INT_MASKL_HOST); + writel(0, priv->base + MIP_INT_MASKH_HOST); + writel(~0, priv->base + MIP_INT_MASKL_VPU); + writel(~0, priv->base + MIP_INT_MASKH_VPU); + writel(~0, priv->base + MIP_INT_CFGL_HOST); + writel(~0, priv->base + MIP_INT_CFGH_HOST); + + ret = mip_init_domains(priv, node); + if (ret) + goto err_map; + + pr_debug("Registered %u MSI-X, starting at %u\n", + priv->num_msis, priv->msi_base); + + return 0; + +err_map: + bitmap_free(priv->msi_map); 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Wed, 26 Jun 2024 10:46:43 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH 4/7] PCI: brcmstb: Reuse config structure Date: Wed, 26 Jun 2024 13:45:41 +0300 Message-ID: <20240626104544.14233-5-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240626104544.14233-1-svarbanov@suse.de> References: <20240626104544.14233-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Score: -1.30 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-1.30 / 50.00]; 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Signed-off-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 44 ++++++++++++--------------- 1 file changed, 20 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index c08683febdd4..4ca509502336 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -184,9 +184,9 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 -#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) -#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) -#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) +#define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) /* Rescal registers */ #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 @@ -261,22 +261,19 @@ struct brcm_pcie { int gen; u64 msi_target_addr; struct brcm_msi *msi; - const int *reg_offsets; - enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - void (*perst_set)(struct brcm_pcie *pcie, u32 val); - void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; + const struct pcie_cfg_data *cfg; }; static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->type == BCM7435 || pcie->type == BCM7425; + return pcie->cfg->type == BCM7435 || pcie->cfg->type == BCM7425; } /* @@ -878,16 +875,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) int ret, memc; /* Reset the bridge */ - pcie->bridge_sw_init_set(pcie, 1); + pcie->cfg->bridge_sw_init_set(pcie, 1); /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->type == BCM2711) - pcie->perst_set(pcie, 1); + if (pcie->cfg->type == BCM2711) + pcie->cfg->perst_set(pcie, 1); usleep_range(100, 200); /* Take the bridge out of reset */ - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); if (is_bmips(pcie)) @@ -905,9 +902,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst = 0x1; /* 256 bytes */ - else if (pcie->type == BCM2711) + else if (pcie->cfg->type == BCM2711) burst = 0x0; /* 128 bytes */ - else if (pcie->type == BCM7278) + else if (pcie->cfg->type == BCM7278) burst = 0x3; /* 512 bytes */ else burst = 0x2; /* 512 bytes */ @@ -1120,7 +1117,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) int ret, i; /* Unassert the fundamental reset */ - pcie->perst_set(pcie, 0); + pcie->cfg->perst_set(pcie, 0); /* * Wait for 100ms after PERST# deassertion; see PCIe CEM specification @@ -1320,7 +1317,7 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - pcie->perst_set(pcie, 1); + pcie->cfg->perst_set(pcie, 1); /* Deassert request for L23 in case it was asserted */ tmp = readl(base + PCIE_MISC_PCIE_CTRL); @@ -1333,7 +1330,7 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); /* Shutdown PCIe bridge */ - pcie->bridge_sw_init_set(pcie, 1); + pcie->cfg->bridge_sw_init_set(pcie, 1); } static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) @@ -1413,7 +1410,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) goto err_reset; /* Take bridge out of reset so we can access the SERDES reg */ - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); /* SERDES_IDDQ = 0 */ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); @@ -1595,10 +1592,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = &pdev->dev; pcie->np = np; - pcie->reg_offsets = data->offsets; - pcie->type = data->type; - pcie->perst_set = data->perst_set; - pcie->bridge_sw_init_set = data->bridge_sw_init_set; + pcie->cfg = data; pcie->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) @@ -1645,7 +1639,8 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; 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Wed, 26 Jun 2024 10:46:44 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id yJqxLJTxe2ZuDQAAD6G6ig (envelope-from ); Wed, 26 Jun 2024 10:46:44 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH 5/7] PCI: brcmstb: add phy_controllable flag Date: Wed, 26 Jun 2024 13:45:42 +0300 Message-ID: <20240626104544.14233-6-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240626104544.14233-1-svarbanov@suse.de> References: <20240626104544.14233-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Queue-Id: DA24E21AE3 X-Spam-Score: -1.44 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-1.44 / 50.00]; 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R_RATELIMIT(0.00)[to_ip_from(RLw7mkaud87zuqqztkur5718rm)]; RCVD_VIA_SMTP_AUTH(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Not all PCIe can control the phy block, add a flag in config structure to take that fact into account. Signed-off-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 4ca509502336..ff8e5e672ff0 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -224,6 +224,7 @@ enum pcie_type { struct pcie_cfg_data { const int *offsets; const enum pcie_type type; + bool phy_controllable; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); }; @@ -1301,11 +1302,17 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) static inline int brcm_phy_start(struct brcm_pcie *pcie) { + if (!pcie->cfg->phy_controllable) + return 0; + return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; } static inline int brcm_phy_stop(struct brcm_pcie *pcie) { + if (!pcie->cfg->phy_controllable) + return 0; + return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; } @@ -1498,6 +1505,7 @@ static const int pcie_offsets_bmips_7425[] = { static const struct pcie_cfg_data generic_cfg = { .offsets = pcie_offsets, .type = GENERIC, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; @@ -1505,6 +1513,7 @@ static const struct pcie_cfg_data generic_cfg = { static const struct pcie_cfg_data bcm7425_cfg = { .offsets = pcie_offsets_bmips_7425, .type = BCM7425, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; @@ -1512,6 +1521,7 @@ static const struct pcie_cfg_data bcm7425_cfg = { static const struct pcie_cfg_data bcm7435_cfg = { .offsets = pcie_offsets, .type = BCM7435, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; @@ -1519,6 +1529,7 @@ static const struct pcie_cfg_data bcm7435_cfg = { static const struct pcie_cfg_data bcm4908_cfg = { .offsets = pcie_offsets, .type = BCM4908, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_4908, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; @@ -1532,6 +1543,7 @@ static const int pcie_offset_bcm7278[] = { static const struct pcie_cfg_data bcm7278_cfg = { .offsets = pcie_offset_bcm7278, .type = BCM7278, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, }; @@ -1539,6 +1551,7 @@ static const struct pcie_cfg_data bcm7278_cfg = { static const struct pcie_cfg_data bcm2711_cfg = { .offsets = pcie_offsets, .type = BCM2711, + .phy_controllable = true, .perst_set = brcm_pcie_perst_set_generic, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; From patchwork Wed Jun 26 10:45:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13712662 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA7C617F50F; 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Wed, 26 Jun 2024 10:46:45 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id UCvzNpXxe2ZuDQAAD6G6ig (envelope-from ); Wed, 26 Jun 2024 10:46:45 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH 6/7] PCI: brcmstb: Add bcm2712 support Date: Wed, 26 Jun 2024 13:45:43 +0300 Message-ID: <20240626104544.14233-7-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240626104544.14233-1-svarbanov@suse.de> References: <20240626104544.14233-1-svarbanov@suse.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Queue-Id: 12CCD21AB1 X-Spam-Score: -1.51 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-1.51 / 50.00]; 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DKIM_TRACE(0.00)[suse.de:+]; R_RATELIMIT(0.00)[to_ip_from(RLw7mkaud87zuqqztkur5718rm)]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Add bare minimum amount of changes in order to support PCIe RC hardware IP found in RPi5. Signed-off-by: Stanimir Varbanov --- drivers/pci/controller/pcie-brcmstb.c | 257 +++++++++++++++++++++++++- 1 file changed, 250 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index ff8e5e672ff0..ec0a66ae06e4 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -55,6 +55,10 @@ #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_RC_PL_PHY_CTL_15 0x184c +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff + #define PCIE_MISC_MISC_CTRL 0x4008 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 @@ -77,6 +81,7 @@ #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR1_CONFIG_HI 0x4030 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f @@ -92,6 +97,8 @@ #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540 +#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c + #define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4 @@ -122,8 +129,9 @@ #define PCIE_MEM_WIN0_LIMIT_HI(win) \ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) -#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG (pcie->cfg->offsets[PCIE_HARD_DEBUG]) #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 @@ -131,7 +139,37 @@ (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) -#define PCIE_INTR2_CPU_BASE 0x4300 +#define PCIE_MISC_UBUS_CTRL 0x40a4 +#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13) +#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19) + +#define PCIE_MISC_UBUS_TIMEOUT 0x40a8 + +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x40b0 + +#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4 +#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0) + +/* Additional RC BARs */ +#define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 +#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8 +#define PCIE_MISC_RC_BAR10_CONFIG_LO 0x4104 +#define PCIE_MISC_RC_BAR10_CONFIG_HI 0x4108 + +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1 +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000 +#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110 +#define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_LO 0x413c +#define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_HI 0x4140 + +#define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170 + +#define PCIE_INTR2_CPU_BASE (pcie->cfg->offsets[INTR2_CPU]) #define PCIE_MSI_INTR2_BASE 0x4500 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */ #define MSI_INT_STATUS 0x0 @@ -205,6 +243,8 @@ enum { RGR1_SW_INIT_1, EXT_CFG_INDEX, EXT_CFG_DATA, + PCIE_HARD_DEBUG, + INTR2_CPU, }; enum { @@ -219,6 +259,7 @@ enum pcie_type { BCM4908, BCM7278, BCM2711, + BCM2712, }; struct pcie_cfg_data { @@ -264,6 +305,7 @@ struct brcm_pcie { struct brcm_msi *msi; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -288,8 +330,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) if (log2_in >= 12 && log2_in <= 15) /* Covers 4KB to 32KB (inclusive) */ return (log2_in - 12) + 0x1c; - else if (log2_in >= 16 && log2_in <= 35) - /* Covers 64KB to 32GB, (inclusive) */ + else if (log2_in >= 16 && log2_in <= 36) + /* Covers 64KB to 64GB, (inclusive) */ return log2_in - 15; /* Something is awry so disable */ return 0; @@ -444,7 +486,7 @@ static struct irq_chip brcm_msi_irq_chip = { static struct msi_domain_info brcm_msi_domain_info = { .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI), + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), .chip = &brcm_msi_irq_chip, }; @@ -668,6 +710,41 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) return 0; } +static int brcm_pcie_enable_external_msix(struct brcm_pcie *pcie, + struct device_node *msi_np) +{ + u64 msi_pci_addr, msi_phys_addr; + u32 val; + + if (of_property_read_u64(msi_np, "brcm,msi-pci-addr", &msi_pci_addr)) { + dev_err(pcie->dev, "Unable to find MSI PCI address\n"); + return -EINVAL; + } + + if (of_property_read_u64(msi_np, "reg", &msi_phys_addr)) { + dev_err(pcie->dev, "Unable to find MSI physical address\n"); + return -EINVAL; + } + + /* Use RC_BAR1 for MIP access */ + + val = lower_32_bits(msi_pci_addr); + val |= brcm_pcie_encode_ibar_size(0x1000); + writel(val, pcie->base + PCIE_MISC_RC_BAR1_CONFIG_LO); + + val = upper_32_bits(msi_pci_addr); + writel(val, pcie->base + PCIE_MISC_RC_BAR1_CONFIG_HI); + + val = lower_32_bits(msi_phys_addr); + val |= PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK; + writel(val, pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP); + + val = upper_32_bits(msi_phys_addr); + writel(val, pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI); + + return 0; +} + /* The controller is capable of serving in both RC and EP roles */ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) { @@ -748,6 +825,18 @@ static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } +static void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val) +{ + if (WARN_ONCE(!pcie->bridge_reset, + "missing bridge reset controller\n")) + return; + + if (val) + reset_control_assert(pcie->bridge_reset); + else + reset_control_deassert(pcie->bridge_reset); +} + static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) { if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) @@ -769,6 +858,16 @@ static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); } +static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + /* Perst bit has moved and assert value is 0 */ + tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); + u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK); + writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); +} + static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp; @@ -795,6 +894,9 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, size += entry->res->end - entry->res->start + 1; if (pcie_beg < lowest_pcie_addr) lowest_pcie_addr = pcie_beg; + /* Only consider the first entry */ + if (pcie->cfg->type == BCM2711 || pcie->cfg->type == BCM2712) + break; } if (lowest_pcie_addr == ~(u64)0) { @@ -865,6 +967,30 @@ static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, return 0; } +static int brcm_pcie_get_rc_bar_n(struct brcm_pcie *pcie, + int idx, + u64 *rc_bar_cpu, + u64 *rc_bar_size, + u64 *rc_bar_pci) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + struct resource_entry *entry; + int i = 0; + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + if (i == idx) { + *rc_bar_cpu = entry->res->start; + *rc_bar_size = entry->res->end - entry->res->start + 1; + *rc_bar_pci = entry->res->start - entry->offset; + return 0; + } + + i++; + } + + return -EINVAL; +} + static int brcm_pcie_setup(struct brcm_pcie *pcie) { u64 rc_bar2_offset, rc_bar2_size; @@ -873,7 +999,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) struct resource_entry *entry; u32 tmp, burst, aspm_support; int num_out_wins = 0; - int ret, memc; + int ret, memc, count, i; /* Reset the bridge */ pcie->cfg->bridge_sw_init_set(pcie, 1); @@ -907,6 +1033,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) burst = 0x0; /* 128 bytes */ else if (pcie->cfg->type == BCM7278) burst = 0x3; /* 512 bytes */ + else if (pcie->cfg->type == BCM2712) + burst = 0x1; /* 128 bytes */ else burst = 0x2; /* 512 bytes */ @@ -934,7 +1062,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) writel(upper_32_bits(rc_bar2_offset), base + PCIE_MISC_RC_BAR2_CONFIG_HI); + tmp = readl(base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP); + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK); + writel(tmp, base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP); tmp = readl(base + PCIE_MISC_MISC_CTRL); + for (memc = 0; memc < pcie->num_memc; memc++) { u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; @@ -945,8 +1077,32 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) else if (memc == 2) u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2)); } + writel(tmp, base + PCIE_MISC_MISC_CTRL); + if (pcie->cfg->type == BCM2712) { + /* Suppress AXI error responses and return 1s for read failures */ + tmp = readl(base + PCIE_MISC_UBUS_CTRL); + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK); + u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK); + writel(tmp, base + PCIE_MISC_UBUS_CTRL); + writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA); + + /* + * Adjust timeouts. The UBUS timeout also affects CRS + * completion retries, as the request will get terminated if + * either timeout expires, so both have to be a large value + * (in clocks of 750MHz). + * Set UBUS timeout to 250ms, then set RC config retry timeout + * to be ~240ms. + * + * Setting CRSVis=1 will stop the core from blocking on a CRS + * response, but does require the device to be well-behaved... + */ + writel(0xb2d0000, base + PCIE_MISC_UBUS_TIMEOUT); + writel(0xaba0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT); + } + /* * We ideally want the MSI target address to be located in the 32bit * addressable memory area. Some devices might depend on it. This is @@ -983,6 +1139,38 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); + /* Program additional inbound windows (RC_BAR4..RC_BAR10) */ + count = (pcie->cfg->type == BCM2712) ? 7 : 0; + for (i = 0; i < count; i++) { + u64 bar_cpu, bar_size, bar_pci; + + ret = brcm_pcie_get_rc_bar_n(pcie, 1 + i, &bar_cpu, &bar_size, + &bar_pci); + if (ret) + break; + + tmp = lower_32_bits(bar_pci); + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size), + PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK); + writel(tmp, base + PCIE_MISC_RC_BAR4_CONFIG_LO + i * 8); + writel(upper_32_bits(bar_pci), + base + PCIE_MISC_RC_BAR4_CONFIG_HI + i * 8); + + tmp = upper_32_bits(bar_cpu) & + PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK; + writel(tmp, + base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI + i * 8); + tmp = lower_32_bits(bar_cpu) & + PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK; + writel(tmp | PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE, + base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + i * 8); + } + + if (pcie->gen) { + dev_info(pcie->dev, "Forcing gen %d\n", pcie->gen); + brcm_pcie_set_gen(pcie, pcie->gen); + } + /* * For config space accesses on the RC, show the right class for * a PCIe-PCIe bridge (the default setting is to be EP mode). @@ -1043,6 +1231,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + /* BCM2712 doesn't have an RGR bridge */ + if (pcie->cfg->type == BCM2712) + return; + /* Each unit in timeout register is 1/216,000,000 seconds */ writel(216 * timeout_us, pcie->base + REG_OFFSET); } @@ -1113,7 +1305,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) { struct device *dev = pcie->dev; void __iomem *base = pcie->base; - u16 nlw, cls, lnksta; + u16 nlw, cls, lnksta, tmp16; bool ssc_good = false; int ret, i; @@ -1159,6 +1351,17 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); + /* + * RootCtl bits are reset by perst_n, which undoes pci_enable_crs() + * called prior to pci_add_new_bus() during probe. Re-enable here. + */ + tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCAP); + if (tmp16 & PCI_EXP_RTCAP_CRSVIS) { + tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL); + u16p_replace_bits(&tmp16, 1, PCI_EXP_RTCTL_CRSSVE); + writew(tmp16, base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL); + } + return 0; } @@ -1336,6 +1539,13 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + /* + * Shutting down this bridge on pcie1 means accesses to rescal block + * will hang the chip if another RC wants to assert/deassert rescal. + */ + if (pcie->cfg->type == BCM2712) + return; + /* Shutdown PCIe bridge */ pcie->cfg->bridge_sw_init_set(pcie, 1); } @@ -1494,12 +1704,16 @@ static const int pcie_offsets[] = { [RGR1_SW_INIT_1] = 0x9210, [EXT_CFG_INDEX] = 0x9000, [EXT_CFG_DATA] = 0x9004, + [PCIE_HARD_DEBUG] = 0x4204, + [INTR2_CPU] = 0x4300, }; static const int pcie_offsets_bmips_7425[] = { [RGR1_SW_INIT_1] = 0x8010, [EXT_CFG_INDEX] = 0x8300, [EXT_CFG_DATA] = 0x8304, + [PCIE_HARD_DEBUG] = 0x4204, + [INTR2_CPU] = 0x4300, }; static const struct pcie_cfg_data generic_cfg = { @@ -1538,6 +1752,8 @@ static const int pcie_offset_bcm7278[] = { [RGR1_SW_INIT_1] = 0xc010, [EXT_CFG_INDEX] = 0x9000, [EXT_CFG_DATA] = 0x9004, + [PCIE_HARD_DEBUG] = 0x4204, + [INTR2_CPU] = 0x4300, }; static const struct pcie_cfg_data bcm7278_cfg = { @@ -1556,8 +1772,23 @@ static const struct pcie_cfg_data bcm2711_cfg = { .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; +static const int pcie_offsets_bcm2712[] = { + [EXT_CFG_INDEX] = 0x9000, + [EXT_CFG_DATA] = 0x9004, + [PCIE_HARD_DEBUG] = 0x4304, + [INTR2_CPU] = 0x4400, +}; + +static const struct pcie_cfg_data bcm2712_cfg = { + .offsets = pcie_offsets_bcm2712, + .type = BCM2712, + .perst_set = brcm_pcie_perst_set_2712, + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712, +}; + static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, + { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg }, { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, @@ -1635,6 +1866,12 @@ static int brcm_pcie_probe(struct platform_device *pdev) clk_disable_unprepare(pcie->clk); return PTR_ERR(pcie->perst_reset); } + pcie->bridge_reset = + devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); + if (IS_ERR(pcie->bridge_reset)) { + clk_disable_unprepare(pcie->clk); + return PTR_ERR(pcie->bridge_reset); + } ret = reset_control_reset(pcie->rescal); if (ret) @@ -1666,6 +1903,12 @@ static int brcm_pcie_probe(struct platform_device *pdev) dev_err(pcie->dev, "probe of internal MSI failed"); goto fail; } + } else if (pci_msi_enabled() && msi_np != pcie->np) { + ret = brcm_pcie_enable_external_msix(pcie, msi_np); + if (ret) { + dev_err(pcie->dev, "probe of external MSI-X failed\n"); + goto fail; + } } bridge->ops = pcie->cfg->type == BCM7425 ? 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Signed-off-by: Stanimir Varbanov --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 218 ++++++++++++++++++++-- 1 file changed, 202 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index bccb7318ce7e..358b129a0f65 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -186,17 +186,30 @@ cma: linux,cma { }; }; - soc: soc@107c000000 { + soc: soc@0 { compatible = "simple-bus"; - ranges = <0x00000000 0x10 0x00000000 0x80000000>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + + ranges = + <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges = + <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; sdio1: mmc@fff000 { compatible = "brcm,bcm2712-sdhci", "brcm,sdhci-brcmstb"; - reg = <0x00fff000 0x260>, - <0x00fff400 0x200>; + reg = <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>; reg-names = "host", "cfg"; interrupts = ; clocks = <&clk_emmc2>; @@ -206,7 +219,7 @@ sdio1: mmc@fff000 { system_timer: timer@7c003000 { compatible = "brcm,bcm2835-system-timer"; - reg = <0x7c003000 0x1000>; + reg = <0x10 0x7c003000 0x0 0x1000>; interrupts = , , , @@ -216,19 +229,19 @@ system_timer: timer@7c003000 { mailbox: mailbox@7c013880 { compatible = "brcm,bcm2835-mbox"; - reg = <0x7c013880 0x40>; + reg = <0x10 0x7c013880 0x0 0x40>; interrupts = ; #mbox-cells = <0>; }; local_intc: local-intc@7cd00000 { compatible = "brcm,bcm2836-l1-intc"; - reg = <0x7cd00000 0x100>; + reg = <0x10 0x7cd00000 0x0 0x100>; }; uart10: serial@7d001000 { compatible = "arm,pl011", "arm,primecell"; - reg = <0x7d001000 0x200>; + reg = <0x10 0x7d001000 0x0 0x200>; interrupts = ; clocks = <&clk_uart>, <&clk_vpu>; clock-names = "uartclk", "apb_pclk"; @@ -238,7 +251,7 @@ uart10: serial@7d001000 { interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; - reg = <0x7d517000 0x10>; + reg = <0x10 0x7d517000 0x0 0x10>; interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -246,7 +259,7 @@ interrupt-controller@7d517000 { gio_aon: gpio@7d517c00 { compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; - reg = <0x7d517c00 0x40>; + reg = <0x10 0x7d517c00 0x0 0x40>; gpio-controller; #gpio-cells = <2>; brcm,gpio-bank-widths = <17 6>; @@ -258,13 +271,186 @@ gio_aon: gpio@7d517c00 { gicv2: interrupt-controller@7fff9000 { compatible = "arm,gic-400"; - reg = <0x7fff9000 0x1000>, - <0x7fffa000 0x2000>, - <0x7fffc000 0x2000>, - <0x7fffe000 0x2000>; + reg = <0x10 0x7fff9000 0x0 0x1000>, + <0x10 0x7fffa000 0x0 0x2000>, + <0x10 0x7fffc000 0x0 0x2000>, + <0x10 0x7fffe000 0x0 0x2000>; interrupt-controller; #interrupt-cells = <3>; }; + + mip0: msi-controller@130000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00130000 0x00 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <128>; + brcm,msi-num-spis = <64>; + brcm,msi-offset = <0>; + brcm,msi-pci-addr = <0xff 0xfffff000>; + }; + + mip1: msi-controller@131000 { + compatible = "brcm,bcm2712-mip-intc"; + reg = <0x10 0x00131000 0x00 0xc0>; + msi-controller; + interrupt-controller; + #interrupt-cells = <2>; + brcm,msi-base-spi = <247>; + /* Actually 20 total, but the others are + * both sparse and non-consecutive + */ + brcm,msi-num-spis = <8>; + brcm,msi-offset = <8>; + brcm,msi-pci-addr = <0xff 0xffffe000>; + }; + + pcie_rescal: reset-controller@119500 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x10 0x00119500 0x00 0x10>; + #reset-cells = <0>; + }; + + bcm_reset: reset-controller@1504318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x10 0x01504318 0x00 0x30>; + #reset-cells = <1>; + }; + + /* Single-lane Gen3 PCIe + * Outbound window at 14_0000_0000-17_ffff_ffff + */ + pcie0: pcie@100000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00100000 0x0 0x9310>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 208: AER, 215: NMI, 216: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 42>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&pcie0>; + + ranges = <0x02000000 0x00 0x00000000 + 0x17 0x00000000 + 0x0 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x14 0x00000000 + 0x3 0x00000000>; + + dma-ranges = <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; + + /* Single-lane Gen3 PCIe + * Outbound window at 18_0000_0000-1b_ffff_ffff + */ + pcie1: pcie@110000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00110000 0x0 0x9310>; + device_type = "pci"; + linux,pci-domain = <1>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 218: AER, 225: NMI, 226: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 43>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&mip1>; + + ranges = <0x02000000 0x00 0x00000000 + 0x1b 0x00000000 + 0x00 0xfffffffc>, + <0x43000000 0x04 0x00000000 + 0x18 0x00000000 + 0x03 0x00000000>; + + dma-ranges = <0x03000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; + + /* Quad-lane Gen3 PCIe + * Outbound window at 1c_0000_0000-1f_ffff_ffff + */ + pcie2: pcie@120000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x10 0x00120000 0x00 0x9310>; + device_type = "pci"; + linux,pci-domain = <2>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + /* Unused interrupts: 228: AER, 235: NMI, 236: PME */ + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 44>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-parent = <&mip0>; + + // ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 + ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x0 0xfffffffc>, + // 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 + <0x43000000 0x04 0x00000000 + 0x1c 0x00000000 + 0x03 0x00000000>; + + // 64GB system RAM space at PCIe 10_0000_0000 + dma-ranges = <0x02000000 0x00 0x00000000 + 0x1f 0x00000000 + 0x00 0x00400000>, + <0x43000000 0x10 0x00000000 + 0x00 0x00000000 + 0x10 0x00000000>; + + status = "disabled"; + }; }; timer {