From patchwork Wed Jun 26 12:37:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13712832 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 354611474D4; Wed, 26 Jun 2024 12:38:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719405494; cv=none; b=W52jtL7YSZ2CW5YGHDNr38bYoj3jwy3Q/C2ySSBNRecWs98hMNi3Uv6XjgmJMcGBQVhTb3icN9HCXrnE2qIv7WlQ0mkQhga+Z/RIzJlkp9DLk/fcDZKW5g8iW8U5c7t0ntVvJLWA5llHRc/TN1GAB72YyG3Wp9/O9ZOzzC+76Ww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719405494; c=relaxed/simple; bh=/aw0WtwPmVZySBFz2H9clszTt8P3jzZkMlqbGcwPdoI=; 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Wed, 26 Jun 2024 12:38:01 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:37:56 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:49 +0530 Subject: [PATCH RFC 1/7] dt: bindings: add qcom,qps615.yaml Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-1-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719405471; l=2476; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=/aw0WtwPmVZySBFz2H9clszTt8P3jzZkMlqbGcwPdoI=; b=DXkeP/a4jyMBskUt3dtXDg5vn4ouKucKv75saOW7IjhogYzEQO+CWEfTIyiqg97Hw4sxPAJQY J0Bluq4gh5wC6v1PLa1X0tod4887sWejSjKVfX35v6RthJkGumkn1Ne X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: luvrWw1hPqj0IRKmVmZaB13A5VcNCPqI X-Proofpoint-GUID: luvrWw1hPqj0IRKmVmZaB13A5VcNCPqI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 bulkscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260094 qps615 is a driver for Qualcomm PCIe switch driver which controls power & configuration of the hardware. Add a bindings document for the driver. Signed-off-by: Krishna chaitanya chundru --- .../devicetree/bindings/pci/qcom,qps615.yaml | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,qps615.yaml b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml new file mode 100644 index 000000000000..f090683f9e2f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-qps615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPS615 PCIe switch + +maintainers: + - Krishna chaitanya chundru + +description: | + Qualcomm QPS615 PCIe switch has one upstream and three downstream + ports. One of the downstream ports is used as endpoint device of + Ethernet MAC. Other two downstream ports are supposed to connect + to external device. + + The power controlled by the GPIO's, if we enable the GPIO's the + power to the switch will be on. + + The QPS615 PCIe switch is configured through I2C interface before + PCIe link is established. + +properties: + compatible: + enum: + - pci1179,0623 + + reg: + maxItems: 1 + + vdd-supply: + description: | + Phandle to the vdd input voltage which are fixed regulators which + in are mapped to the GPIO's. + + switch-i2c-cntrl: + description: | + phandle to i2c controller which is used to configure the PCIe + switch. + +required: + - compatible + - reg + - vdd-supply + - switch-i2c-cntrl + +additionalProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bus-range = <0x01 0xff>; + + qps615@0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vdd-supply = <&vdd>; + switch-i2c-cntrl = <&foo>; + }; + }; + }; From patchwork Wed Jun 26 12:37:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13712833 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55BF41822CB; Wed, 26 Jun 2024 12:38:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719405497; cv=none; b=jDOKhPPmcfyeHgcE2AoPIiDXhSgsAL4TxtK8ceENmlOc+4RHninVmxnwae7cRuQFy9K5GJo77i3Yuj/w3TbViJcgI1iKpYWQQIbiZh57L8J2TmhJI3TDcBuD69Py+EZ3cjmGOVJahMCj166SrSzHMyqwEMRDi346I/66dtA9jeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 26 Jun 2024 12:38:07 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:01 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:50 +0530 Subject: [PATCH RFC 2/7] arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-2-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Once the GPIO's are enabled, switch power will be on. Make all GPIO's as fixed regulators and inter link them so that enabling the regulator will enable power to the switch by enabling GPIO's. Enable i2c0 which is required to configure the switch. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a085ff5b5fb2..5b453896a6c9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -511,6 +511,61 @@ vreg_bob_3p296: bob { regulator-max-microvolt = <3960000>; }; }; + + qps615_0p9_vreg: qps615-0p9-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_0p9_vreg"; + gpio = <&pm8350c_gpios 2 0>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <4300>; + }; + + qps615_1p8_vreg: qps615-1p8-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_1p8_vreg"; + gpio = <&pm8350c_gpios 3 0>; + vin-supply = <&qps615_0p9_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; + + qps615_rsex_vreg: qps615-rsex-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_rsex_vreg"; + gpio = <&pm8350c_gpios 1 0>; + vin-supply = <&qps615_1p8_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pcie1 { + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x01 0xff>; + + qps615@0 { + compatible = "pci1179,0623"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + vdda-supply = <&qps615_rsex_vreg>; + switch-i2c-cntrl = <&i2c0>; + }; + }; }; &gcc { From patchwork Wed Jun 26 12:37:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13712834 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C42818410C; 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Wed, 26 Jun 2024 12:38:13 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QCcCsi002760 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 12:38:12 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:07 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:51 +0530 Subject: [PATCH RFC 3/7] pci: Change the parent of the platform devices for child OF nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-3-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719405471; l=2484; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=o73P9a6+O7XFPmCnQ9h8UKwsslsAIZP78jJFcmgXucE=; b=FtCKxhvs5D+vmvL9iESiZMmFM1UCNW4pokyCdk6crWHFlFMqJSXoi/yfn2mxR6Ly9uYASbxiG LDj2eg6kYTqAAwKSapdXHD3ab6o6sGeOofiLVshcOCCYfRV6nqZknjZ X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: n9BSs_OYnN20c9tUZGj_hPGqWWS-uRxM X-Proofpoint-GUID: n9BSs_OYnN20c9tUZGj_hPGqWWS-uRxM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 mlxlogscore=809 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260094 Currently the power control driver is child of pci-pci bridge driver, this will cause issue when suspend resume is introduced in the pwr control driver. If the supply is removed to the endpoint in the power control driver then the config space access initaited by the pci-pci bridge driver can cause issues like Timeouts. For this reason change the parent to controller from pci-pci bridge. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/bus.c | 5 +++-- drivers/pci/pwrctl/core.c | 7 ++++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 3e3517567721..eedab4aabd81 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -335,6 +335,7 @@ void __weak pcibios_bus_add_device(struct pci_dev *pdev) { } void pci_bus_add_device(struct pci_dev *dev) { struct device_node *dn = dev->dev.of_node; + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); int retval; /* @@ -356,9 +357,9 @@ void pci_bus_add_device(struct pci_dev *dev) pci_dev_assign_added(dev, true); - if (pci_is_bridge(dev)) { + if (pci_is_bridge(dev) && host) { retval = of_platform_populate(dev->dev.of_node, NULL, NULL, - &dev->dev); + host->dev.parent); if (retval) pci_err(dev, "failed to populate child OF nodes (%d)\n", retval); diff --git a/drivers/pci/pwrctl/core.c b/drivers/pci/pwrctl/core.c index feca26ad2f6a..4c0d0f3b15f8 100644 --- a/drivers/pci/pwrctl/core.c +++ b/drivers/pci/pwrctl/core.c @@ -10,6 +10,7 @@ #include #include #include +#include "../pci.h" static int pci_pwrctl_notify(struct notifier_block *nb, unsigned long action, void *data) @@ -64,18 +65,22 @@ static int pci_pwrctl_notify(struct notifier_block *nb, unsigned long action, */ int pci_pwrctl_device_set_ready(struct pci_pwrctl *pwrctl) { + struct pci_bus *bus = pci_find_bus(of_get_pci_domain_nr(pwrctl->dev->parent->of_node), 0); int ret; if (!pwrctl->dev) return -ENODEV; + if (!bus) + return -ENODEV; + pwrctl->nb.notifier_call = pci_pwrctl_notify; ret = bus_register_notifier(&pci_bus_type, &pwrctl->nb); if (ret) return ret; pci_lock_rescan_remove(); - pci_rescan_bus(to_pci_dev(pwrctl->dev->parent)->bus); + pci_rescan_bus(bus); pci_unlock_rescan_remove(); return 0; From patchwork Wed Jun 26 12:37:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13712835 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A76181CF1; Wed, 26 Jun 2024 12:38:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 26 Jun 2024 12:38:18 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QCcH35012411 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 12:38:17 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:12 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:52 +0530 Subject: [PATCH RFC 4/7] pci: Add new start_link() & stop_link function ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-4-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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As controller driver already enables link training, we need to stop the link training by using stop_link and enable them back after device is configured by using start_link. The stop_link() & start_link() be used to keep the link in D3cold & D0 before turning off the power of the device. Signed-off-by: Krishna chaitanya chundru --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index fb004fd4e889..3892ff7fd536 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -803,6 +803,8 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + int (*start_link)(struct pci_bus *bus); + int (*stop_link)(struct pci_bus *bus); }; /* From patchwork Wed Jun 26 12:37:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13712836 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDF8B181D1B; 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d15a5c2d5b48..edf624768145 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -646,10 +646,29 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_host_start_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + return dw_pcie_start_link(pci); +} + +static int dw_pcie_host_stop_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + dw_pcie_stop_link(pci); + return 0; +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .start_link = dw_pcie_host_start_link, + .stop_link = dw_pcie_host_stop_link, }; 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Wed, 26 Jun 2024 12:38:28 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:23 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:54 +0530 Subject: [PATCH RFC 6/7] pci: qcom: Add support for start_link() & stop_link() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-6-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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And in the start_link() the enable LTSSM bit if the resources are turned on other wise do the all the initialization and then start the link. Introduce ltssm_disable function op to stop the link training. Use a flag 'pci_pwrctl_turned_off" to indicate the resources are turned off by the pci pwrctl framework. If the link is stopped using the stop_link() then just return with doing anything in suspend and resume. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 108 +++++++++++++++++++++++++++++---- 1 file changed, 97 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 14772edcf0d3..1ab3ffdb3914 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -37,6 +37,7 @@ /* PARF registers */ #define PARF_SYS_CTRL 0x00 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 @@ -83,6 +84,9 @@ /* PARF_PM_CTRL register fields */ #define REQ_NOT_ENTR_L1 BIT(5) +/* PARF_PM_STTS register fields */ +#define PM_ENTER_L23 BIT(5) + /* PARF_PCS_DEEMPH register fields */ #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) @@ -126,6 +130,7 @@ /* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL_PME_TURNOFF_MSG BIT(4) /* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 @@ -228,6 +233,7 @@ struct qcom_pcie_ops { void (*host_post_init)(struct qcom_pcie *pcie); void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); + void (*ltssm_disable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); }; @@ -248,10 +254,13 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + bool pci_pwrctl_turned_off; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static void qcom_pcie_icc_update(struct qcom_pcie *pcie); + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -266,17 +275,6 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } -static int qcom_pcie_start_link(struct dw_pcie *pci) -{ - struct qcom_pcie *pcie = to_qcom_pcie(pci); - - /* Enable Link Training state machine */ - if (pcie->cfg->ops->ltssm_enable) - pcie->cfg->ops->ltssm_enable(pcie); - - return 0; -} - static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); @@ -556,6 +554,15 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) return 0; } +static void qcom_pcie_2_3_2_ltssm_disable(struct qcom_pcie *pcie) +{ + u32 val; + + val = readl(pcie->parf + PARF_LTSSM); + val &= ~LTSSM_EN; + writel(val, pcie->parf + PARF_LTSSM); +} + static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -1336,6 +1343,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .post_init = qcom_pcie_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .ltssm_disable = qcom_pcie_2_3_2_ltssm_disable, }; /* Qcom IP rev.: 1.9.0 */ @@ -1346,6 +1354,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .host_post_init = qcom_pcie_host_post_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .ltssm_disable = qcom_pcie_2_3_2_ltssm_disable, .config_sid = qcom_pcie_config_sid_1_9_0, }; @@ -1395,9 +1404,81 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { .no_l0s = true, }; +static int qcom_pcie_turnoff_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u32 ret_l23, val, ret; + + if (!dw_pcie_link_up(pcie->pci)) { + if (pcie->cfg->ops->ltssm_disable) + pcie->cfg->ops->ltssm_disable(pcie); + } else { + writel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pcie->elbi + ELBI_SYS_CTRL); + + ret_l23 = readl_poll_timeout(pcie->parf + PARF_PM_STTS, val, + val & PM_ENTER_L23, 10000, 100000); + if (ret_l23) { + dev_err(pci->dev, "Failed to enter L2/L3\n"); + return -ETIMEDOUT; + } + + qcom_pcie_host_deinit(&pcie->pci->pp); + + ret = icc_disable(pcie->icc_mem); + if (ret) + dev_err(pci->dev, "Failed to disable PCIe-MEM interconnect path: %d\n", + ret); + + pcie->pci_pwrctl_turned_off = true; + } + + return 0; +} + +static int qcom_pcie_turnon_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + if (pcie->pci_pwrctl_turned_off) { + qcom_pcie_host_init(&pcie->pci->pp); + + dw_pcie_setup_rc(&pcie->pci->pp); + } + + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); + + /* Ignore the retval, the devices may come up later. */ + dw_pcie_wait_for_link(pcie->pci); + + qcom_pcie_icc_update(pcie); + + pcie->pci_pwrctl_turned_off = false; + + return 0; +} + +static int qcom_pcie_start_link(struct dw_pcie *pci) +{ + return qcom_pcie_turnon_link(pci); +} + +static void qcom_pcie_stop_link(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + + if (!dw_pcie_link_up(pcie->pci)) { + if (pcie->cfg->ops->ltssm_disable) + pcie->cfg->ops->ltssm_disable(pcie); + } else { + qcom_pcie_turnoff_link(pci); + } +} + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, + .stop_link = qcom_pcie_stop_link, }; static int qcom_pcie_icc_init(struct qcom_pcie *pcie) @@ -1604,6 +1685,8 @@ static int qcom_pcie_suspend_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + if (pcie->pci_pwrctl_turned_off) + return 0; /* * Set minimum bandwidth required to keep data path functional during * suspend. @@ -1642,6 +1725,9 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); 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Wed, 26 Jun 2024 12:38:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:28 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:55 +0530 Subject: [PATCH RFC 7/7] pci: pwrctl: Add power control driver for qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-7-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719405471; l=9545; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=GH1ZIcjQdgYwfp8z77xEv6s9RCk4oE8cin2OQE9YM+g=; b=igys+2Y9iLjg6uLmopQAM0IqONOCRY5LiHavrftNwD8fH69dFlEerEAREcFPVbhA32B3A4Rwv 4khExXq9KcxDKjZLwqLfE7f+deIm6Ras3XZQC3UN8iUFfWL/aIKeH5O X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JktbPvjJgskeN9Fb6quZ90PaFemNAWKB X-Proofpoint-GUID: JktbPvjJgskeN9Fb6quZ90PaFemNAWKB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260094 QPS615 switch needs to configured after powering on and before PCIe link was up. As the PCIe controller driver already enables the PCIe link training at the host side, stop the link training. Otherwise the moment we turn on the switch it will participate in the link training and link may come before switch is configured through i2c. The switch can be configured different ways like changing de-emphasis settings of the switch, disabling unused ports etc and these settings can vary from board to board, for that reason the sequence is taken from the firmware file which contains the address of the slave, to address and data to be written to the switch. The driver reads the firmware file and parses them to apply those configurations to the switch. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) diff --git a/drivers/pci/pwrctl/Kconfig b/drivers/pci/pwrctl/Kconfig index f1b824955d4b..a419b250006d 100644 --- a/drivers/pci/pwrctl/Kconfig +++ b/drivers/pci/pwrctl/Kconfig @@ -14,4 +14,11 @@ config PCI_PWRCTL_PWRSEQ Enable support for the PCI power control driver for device drivers using the Power Sequencing subsystem. +config PCI_PWRCTL_QPS615 + tristate "PCI Power Control driver for QPS615" + select PCI_PWRCTL + help + Enable support for the PCI power control driver for QPS615 and + configures it. + endmenu diff --git a/drivers/pci/pwrctl/Makefile b/drivers/pci/pwrctl/Makefile index d308aae4800c..ac563a70c023 100644 --- a/drivers/pci/pwrctl/Makefile +++ b/drivers/pci/pwrctl/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_PWRCTL) += pci-pwrctl-core.o pci-pwrctl-core-y := core.o obj-$(CONFIG_PCI_PWRCTL_PWRSEQ) += pci-pwrctl-pwrseq.o +obj-$(CONFIG_PCI_PWRCTL_QPS615) += pci-pwrctl-qps615.o diff --git a/drivers/pci/pwrctl/pci-pwrctl-qps615.c b/drivers/pci/pwrctl/pci-pwrctl-qps615.c new file mode 100644 index 000000000000..1f2caf5d7da2 --- /dev/null +++ b/drivers/pci/pwrctl/pci-pwrctl-qps615.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +struct qcom_qps615_pwrctl_i2c_setting { + u32 slv_addr; + u32 reg_addr; + u32 val; +}; + +struct qcom_qps615_pwrctl_ctx { + struct i2c_adapter *adapter; + struct pci_pwrctl pwrctl; + struct device_link *link; + struct regulator *vdd; +}; + +/* write 32-bit value to 24 bit register */ +static int qps615_switch_i2c_write(struct qcom_qps615_pwrctl_ctx *ctx, u32 slv_addr, u32 reg_addr, + u32 reg_val) +{ + struct i2c_msg msg; + u8 msg_buf[7]; + int ret; + + msg.addr = slv_addr; + msg.len = 7; + msg.flags = 0; + + /* Big Endian for reg addr */ + msg_buf[0] = (u8)(reg_addr >> 16); + msg_buf[1] = (u8)(reg_addr >> 8); + msg_buf[2] = (u8)reg_addr; + + /* Little Endian for reg val */ + msg_buf[3] = (u8)(reg_val); + msg_buf[4] = (u8)(reg_val >> 8); + msg_buf[5] = (u8)(reg_val >> 16); + msg_buf[6] = (u8)(reg_val >> 24); + + msg.buf = msg_buf; + ret = i2c_transfer(ctx->adapter, &msg, 1); + return ret == 1 ? 0 : ret; +} + +/* read 32 bit value from 24 bit reg addr */ +static int qps615_switch_i2c_read(struct qcom_qps615_pwrctl_ctx *ctx, u32 slv_addr, u32 reg_addr, + u32 *reg_val) +{ + u8 wr_data[3], rd_data[4] = {0}; + struct i2c_msg msg[2]; + int ret; + + msg[0].addr = slv_addr; + msg[0].len = 3; + msg[0].flags = 0; + + /* Big Endian for reg addr */ + wr_data[0] = (u8)(reg_addr >> 16); + wr_data[1] = (u8)(reg_addr >> 8); + wr_data[2] = (u8)reg_addr; + + msg[0].buf = wr_data; + + msg[1].addr = slv_addr; + msg[1].len = 4; + msg[1].flags = I2C_M_RD; + + msg[1].buf = rd_data; + + ret = i2c_transfer(ctx->adapter, &msg[0], 2); + if (ret != 2) + return ret; + + *reg_val = (rd_data[3] << 24) | (rd_data[2] << 16) | (rd_data[1] << 8) | rd_data[0]; + + return 0; +} + +static int qcom_qps615_pwrctl_init(struct qcom_qps615_pwrctl_ctx *ctx) +{ + struct device *dev = ctx->pwrctl.dev; + struct qcom_qps615_pwrctl_i2c_setting *set; + const struct firmware *fw; + const u8 *pos, *eof; + int ret; + u32 val; + + ret = request_firmware(&fw, "qcom/qps615.bin", dev); + if (ret < 0) { + dev_err(dev, "firmware loading failed with ret %d\n", ret); + return ret; + } + + if (!fw) { + ret = -EINVAL; + goto err; + } + + pos = fw->data; + eof = fw->data + fw->size; + + while (pos < (fw->data + fw->size)) { + set = (struct qcom_qps615_pwrctl_i2c_setting *)pos; + + ret = qps615_switch_i2c_write(ctx, set->slv_addr, set->reg_addr, set->val); + if (ret) { + dev_err(dev, + "I2c write failed for slv addr:%x at addr%x with val %x ret %d\n", + set->slv_addr, set->reg_addr, set->val, ret); + goto err; + } + + ret = qps615_switch_i2c_read(ctx, set->slv_addr, set->reg_addr, &val); + if (ret) { + dev_err(dev, "I2c read failed for slv addr:%x at addr%x ret %d\n", + set->slv_addr, set->reg_addr, ret); + goto err; + } + + if (set->val != val) { + dev_err(dev, + "I2c read's mismatch for slv:%x at addr%x exp%d got%d\n", + set->slv_addr, set->reg_addr, set->val, val); + goto err; + } + pos += sizeof(struct qcom_qps615_pwrctl_i2c_setting); + } + +err: + release_firmware(fw); + + return ret; +} + +static int qcom_qps615_power_on(struct qcom_qps615_pwrctl_ctx *ctx) +{ + int ret; + + ret = regulator_enable(ctx->vdd); + if (ret) { + dev_err(ctx->pwrctl.dev, "cannot enable vdda regulator\n"); + return ret; + } + + ret = qcom_qps615_pwrctl_init(ctx); + if (ret) + regulator_disable(ctx->vdd); + + return ret; +} + +static int qcom_qps615_power_off(struct qcom_qps615_pwrctl_ctx *ctx) +{ + return regulator_disable(ctx->vdd); +} + +static int qcom_qps615_pwrctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct qcom_qps615_pwrctl_ctx *ctx; + struct device_node *adapter_node; + struct pci_host_bridge *bridge; + struct i2c_adapter *adapter; + struct pci_bus *bus; + + bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + if (!bus) + return -ENODEV; + + bridge = pci_find_host_bridge(bus); + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + adapter_node = of_parse_phandle(node, "switch-i2c-cntrl", 0); + if (adapter_node) { + adapter = of_get_i2c_adapter_by_node(adapter_node); + __free(adapter_node); + if (!adapter) + return dev_err_probe(dev, -EPROBE_DEFER, + "failed to parse switch-i2c-cntrl\n"); + } + + ctx->pwrctl.dev = dev; + ctx->adapter = adapter; + ctx->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(ctx->vdd)) + return dev_err_probe(dev, PTR_ERR(ctx->vdd), + "failed to get vdd regulator\n"); + + ctx->link = device_link_add(&bridge->dev, dev, DL_FLAG_AUTOREMOVE_CONSUMER); + + platform_set_drvdata(pdev, ctx); + + bridge->ops->stop_link(bus); + qcom_qps615_power_on(ctx); + bridge->ops->start_link(bus); + + return devm_pci_pwrctl_device_set_ready(dev, &ctx->pwrctl); +} + +static const struct of_device_id qcom_qps615_pwrctl_of_match[] = { + { + .compatible = "pci1179,0623", + }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_qps615_pwrctl_of_match); + +static int pci_pwrctl_suspend_noirq(struct device *dev) +{ + struct pci_bus *bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + bridge->ops->stop_link(bus); + qcom_qps615_power_off(ctx); + + return 0; +} + +static int pci_pwrctl_resume_noirq(struct device *dev) +{ + struct pci_bus *bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + qcom_qps615_power_on(ctx); + bridge->ops->start_link(bus); + + return 0; +} + +static void qcom_qps615_pwrctl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + device_link_del(ctx->link); + pci_pwrctl_suspend_noirq(dev); +} + +static const struct dev_pm_ops pci_pwrctl_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(pci_pwrctl_suspend_noirq, pci_pwrctl_resume_noirq) +}; + +static struct platform_driver qcom_qps615_pwrctl_driver = { + .driver = { + .name = "pwrctl-qps615", + .of_match_table = qcom_qps615_pwrctl_of_match, + .pm = &pci_pwrctl_pm_ops, + }, + .probe = qcom_qps615_pwrctl_probe, + .remove_new = qcom_qps615_pwrctl_remove, +}; +module_platform_driver(qcom_qps615_pwrctl_driver); + +MODULE_AUTHOR("Krishna chaitanya chundru "); +MODULE_DESCRIPTION("Qualcomm QPS615 power control driver"); +MODULE_LICENSE("GPL");