From patchwork Wed Jun 26 14:30:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13713037 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14DEF186E26; Wed, 26 Jun 2024 14:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719412267; cv=none; b=o9W+eKohx6IeTCRCbR4F4kBGVNZkRAZ0+tOIFgFfFjqWzQPafmi5KhL0ZHGf/qkKE2Y/b8jd98GKZvwrZRRk6PkgbhBQWVFdB0EUuCiywY3T+QvyI7gSBgmj1RU1umnlXkVwOkrOszreKseiFC4JzYdSWF7Y5t+l8npIuDztVNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719412267; c=relaxed/simple; bh=G/xQhtJfSJVECUMN+T0d9iXwDkBME4Om+sO3P5KPeSA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uQzzCu6Q/VO6Xq7qK2Pgop/tTTSTBleMZ7MtcSt1JEljYOddfyps0KTEscPFRf3Zm7crVHPXEk7TmMQTtGnsNh46kCn6a6R73yLCMb9arGLdXE5t42+Ck8P9GfCmlQD/gCUMEsLwlfIgdNSQKZcUBZsQkxg6YO6H8U65ynaXTfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=E8+sCEvD; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="E8+sCEvD" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45QAfL2s018766; Wed, 26 Jun 2024 14:30:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gBNF1d6gH6Rd1O/2/9XvTuf3ps3jKwjpwvy2Zcx8tZ4=; b=E8+sCEvD45dXAdN9 DOdk5zu7Ixw078k9g+enL4cfdg5Ir+mc/9UDStnrgLfN+x/3vQ666nXRRBgunffC OIz3w1U8MjM0Kkaf9/2beKETv11Nf0DnmiBIVBfEr2gQwn6N3UTzDR/DG93avLFN 9NsNgHb2MQ3zNf3XOS2Y8foA9o7UB/+z4EUlyLw4BDDfAi4ZDp2aAvNtcyIthnrG aeJtjbxg2vk6KfBYubHXRrc797+2d82A6g/4aVvwMhbVrLVmw2Hb7Aa8wy1n6ddS DtA2cx63bhXENdwhXtAqmoi5A+0jqxQoXmdLuGFUMRHHfezeuhoIICZf4q+ccy/c 4A3JSw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 400f90gyr8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 14:30:47 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QEUkrb008085 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 14:30:46 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:30:41 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 1/6] iommu/arm-smmu: re-enable context caching in smmu reset operation Date: Wed, 26 Jun 2024 20:00:15 +0530 Message-ID: <20240626143020.3682243-2-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: So9CL627crvhNC1OWsoifEiSfCIIh8aQ X-Proofpoint-GUID: So9CL627crvhNC1OWsoifEiSfCIIh8aQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 Default MMU-500 reset operation disables context caching in prefetch buffer. It is however expected for context banks using the ACTLR register to retain their prefetch value during reset and runtime suspend. Replace default MMU-500 reset operation with Qualcomm specific reset operation which envelope the default reset operation and re-enables context caching in prefetch buffer for Qualcomm SoCs. Reviewed-by: Konrad Dybcio Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 25f034677f56..76db4c8d1a9b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -14,6 +14,16 @@ #define QCOM_DUMMY_VAL -1 +/* + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch + * buffer). The remaining bits are implementation defined and vary across + * SoCs. + */ + +#define CPRE (1 << 1) +#define CMTLB (1 << 0) + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -379,11 +389,31 @@ static int qcom_smmu_def_domain_type(struct device *dev) return match ? IOMMU_DOMAIN_IDENTITY : 0; } +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) +{ + int ret; + u32 val; + int i; + + ret = arm_mmu500_reset(smmu); + if (ret) + return ret; + + /* arm_mmu500_reset() disables CPRE which is re-enabled here */ + for (i = 0; i < smmu->num_context_banks; ++i) { + val = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); + val |= CPRE; + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val); + } + + return 0; +} + static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; - arm_mmu500_reset(smmu); + qcom_smmu500_reset(smmu); /* * To address performance degradation in non-real time clients, @@ -410,7 +440,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, - .reset = arm_mmu500_reset, + .reset = qcom_smmu500_reset, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG @@ -443,7 +473,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, - .reset = arm_mmu500_reset, + .reset = qcom_smmu500_reset, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, From patchwork Wed Jun 26 14:30:16 2024 Content-Type: text/plain; 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Wed, 26 Jun 2024 14:30:51 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:30:46 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 2/6] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer Date: Wed, 26 Jun 2024 20:00:16 +0530 Message-ID: <20240626143020.3682243-3-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jxq4AW70pxU9QXzDkdHxsgIqAJxaSjZE X-Proofpoint-GUID: jxq4AW70pxU9QXzDkdHxsgIqAJxaSjZE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 qcom_smmu_match_data is static and constant so refactor qcom_smmu to store single pointer to qcom_smmu_match_data instead of replicating multiple child members of the same and handle the further dereferences in the places that want them. Suggested-by: Robin Murphy Reviewed-by: Dmitry Baryshkov Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c index 552199cbd9e2..885af324916b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -73,7 +73,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) if (__ratelimit(&rs)) { dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); - cfg = qsmmu->cfg; + cfg = qsmmu->data->cfg; if (!cfg) return; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 76db4c8d1a9b..573c4c9886f1 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -506,7 +506,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, return ERR_PTR(-ENOMEM); qsmmu->smmu.impl = impl; - qsmmu->cfg = data->cfg; + qsmmu->data = data; return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 9bb3ae7d62da..addc07623c0b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -8,7 +8,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; - const struct qcom_smmu_config *cfg; + const struct qcom_smmu_match_data *data; bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; From patchwork Wed Jun 26 14:30:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13713039 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83ACB186E2E; Wed, 26 Jun 2024 14:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 26 Jun 2024 14:30:57 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QEUucp009791 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 14:30:56 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:30:51 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 3/6] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Date: Wed, 26 Jun 2024 20:00:17 +0530 Message-ID: <20240626143020.3682243-4-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uAVeYgvDHPrIXWLO0U1ZbG1j4ZusG4K_ X-Proofpoint-ORIG-GUID: uAVeYgvDHPrIXWLO0U1ZbG1j4ZusG4K_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 phishscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 Currently in Qualcomm SoCs the default prefetch is set to 1 which allows the TLB to fetch just the next page table. MMU-500 features ACTLR register which is implementation defined and is used for Qualcomm SoCs to have a custom prefetch setting enabling TLB to prefetch the next set of page tables accordingly allowing for faster translations. ACTLR value is unique for each SMR (Stream matching register) and stored in a pre-populated table. This value is set to the register during context bank initialisation. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 61 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 16 +++++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 +- drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 ++ 4 files changed, 84 insertions(+), 3 deletions(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 573c4c9886f1..77c9abffe07d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -215,10 +215,42 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) return true; } +static void qcom_smmu_set_actlr(struct device *dev, struct arm_smmu_device *smmu, int cbndx, + const struct actlr_config *actlrcfg, const size_t num_actlrcfg) +{ + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_smr *smr; + u16 mask; + int idx; + u16 id; + int i; + int j; + + for (i = 0; i < num_actlrcfg; i++) { + id = actlrcfg[i].sid; + mask = actlrcfg[i].mask; + + for_each_cfg_sme(cfg, fwspec, j, idx) { + smr = &smmu->smrs[idx]; + if (smr_is_subset(smr, id, mask)) { + arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR, + actlrcfg[i].actlr); + break; + } + } + } +} + static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + const struct actlr_variant *actlrvar; + int cbndx = smmu_domain->cfg.cbndx; struct adreno_smmu_priv *priv; + int i; smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; @@ -248,6 +280,18 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + actlrvar = qsmmu->data->actlrvar; + if (!actlrvar) + return 0; + + for (i = 0; i < qsmmu->data->num_smmu ; i++) { + if (actlrvar[i].io_start == smmu->ioaddr) { + qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar[i].actlrcfg, + actlrvar[i].num_actlrcfg); + break; + } + } + return 0; } @@ -277,7 +321,24 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + const struct actlr_variant *actlrvar; + int cbndx = smmu_domain->cfg.cbndx; + int i; + smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; + actlrvar = qsmmu->data->actlrvar; + if (!actlrvar) + return 0; + + for (i = 0; i < qsmmu->data->num_smmu ; i++) { + if (actlrvar[i].io_start == smmu->ioaddr) { + qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar[i].actlrcfg, + actlrvar[i].num_actlrcfg); + break; + } + } return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index addc07623c0b..c51817ff4674 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARM_SMMU_QCOM_H @@ -24,8 +24,22 @@ struct qcom_smmu_config { const u32 *reg_offset; }; +struct actlr_config { + u16 sid; + u16 mask; + u32 actlr; +}; + +struct actlr_variant { + const resource_size_t io_start; + const struct actlr_config * const actlrcfg; + const size_t num_actlrcfg; +}; + struct qcom_smmu_match_data { + const struct actlr_variant * const actlrvar; const struct qcom_smmu_config *cfg; + const size_t num_smmu; const struct arm_smmu_impl *impl; const struct arm_smmu_impl *adreno_impl; }; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 87c81f75cf84..f43d417bf7f6 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1003,9 +1003,10 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) * expect simply identical entries for this case, but there's * no harm in accommodating the generalisation. */ - if ((mask & smrs[i].mask) == mask && - !((id ^ smrs[i].id) & ~smrs[i].mask)) + + if (smr_is_subset(&smrs[i], id, mask)) return i; + /* * If the new entry has any other overlap with an existing one, * though, then there always exists at least one stream ID diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 4765c6945c34..d9c2ef8c1653 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -503,6 +503,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, writeq_relaxed(val, arm_smmu_page(smmu, page) + offset); } +static inline bool smr_is_subset(struct arm_smmu_smr *smrs, u16 id, u16 mask) +{ + return (mask & smrs->mask) == mask && !((id ^ smrs->id) & ~smrs->mask); +} + #define ARM_SMMU_GR0 0 #define ARM_SMMU_GR1 1 #define ARM_SMMU_CB(s, n) ((s)->numpage + (n)) From patchwork Wed Jun 26 14:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13713040 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 132441891A9; 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Wed, 26 Jun 2024 14:31:02 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QEV2ox009876 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 14:31:02 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:30:57 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 4/6] iommu/arm-smmu: add ACTLR data and support for SM8550 Date: Wed, 26 Jun 2024 20:00:18 +0530 Message-ID: <20240626143020.3682243-5-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FyIJyffm-lkjhyky2JsEPyMpDglSWBQ0 X-Proofpoint-ORIG-GUID: FyIJyffm-lkjhyky2JsEPyMpDglSWBQ0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 phishscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 Add ACTLR data table for SM8550 along with support for same including SM8550 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 89 ++++++++++++++++++++++ 1 file changed, 89 insertions(+) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 77c9abffe07d..b4521471ffe9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -23,6 +23,85 @@ #define CPRE (1 << 1) #define CMTLB (1 << 0) +#define PREFETCH_SHIFT 8 +#define PREFETCH_DEFAULT 0 +#define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) +#define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) +#define PREFETCH_DEEP (3 << PREFETCH_SHIFT) + +static const struct actlr_config sm8550_apps_actlr_cfg[] = { + { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB }, + { 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, +}; + +static const struct actlr_config sm8550_gfx_actlr_cfg[] = { + { 0x0000, 0x03ff, PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_variant sm8550_actlr[] = { + { + .io_start = 0x15000000, + .actlrcfg = sm8550_apps_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sm8550_apps_actlr_cfg) + }, { + .io_start = 0x03da0000, + .actlrcfg = sm8550_gfx_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sm8550_gfx_actlr_cfg) + }, +}; static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { @@ -606,6 +685,15 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; + +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { + .impl = &qcom_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrvar = sm8550_actlr, + .num_smmu = ARRAY_SIZE(sm8550_actlr), +}; + static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, .adreno_impl = &qcom_adreno_smmu_500_impl, @@ -640,6 +728,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, + { .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data }, { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, { } }; 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Wed, 26 Jun 2024 14:31:07 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:31:02 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 5/6] iommu/arm-smmu: add ACTLR data and support for SC7280 Date: Wed, 26 Jun 2024 20:00:19 +0530 Message-ID: <20240626143020.3682243-6-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: stVHse33-NhFiiEb_0S4KNK-WTAP6sqN X-Proofpoint-ORIG-GUID: stVHse33-NhFiiEb_0S4KNK-WTAP6sqN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 Add ACTLR data table for SC7280 along with support for same including SC7280 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b4521471ffe9..bd101a161d04 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -29,6 +29,55 @@ #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +static const struct actlr_config sc7280_apps_actlr_cfg[] = { + { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB }, + { 0x2040, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x2000, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2062, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x2080, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x20c0, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2100, 0x0020, PREFETCH_DEFAULT | CMTLB }, + { 0x2140, 0x0000, PREFETCH_DEFAULT | CMTLB }, + { 0x0900, 0x0402, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0901, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x0d01, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1181, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1182, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1183, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1184, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1185, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1186, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1187, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1188, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x1189, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118b, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118c, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118d, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118e, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x118f, 0x0420, PREFETCH_DEEP | CPRE | CMTLB }, + { 0x2180, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2181, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2183, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2184, 0x0020, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2187, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, +}; + +static const struct actlr_config sc7280_gfx_actlr_cfg[] = { + { 0x0000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_variant sc7280_actlr[] = { + { + .io_start = 0x15000000, + .actlrcfg = sc7280_apps_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_apps_actlr_cfg) + }, { + .io_start = 0x03da0000, + .actlrcfg = sc7280_gfx_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_gfx_actlr_cfg) + }, +}; + static const struct actlr_config sm8550_apps_actlr_cfg[] = { { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, @@ -685,6 +734,13 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; +static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = { + .impl = &qcom_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrvar = sc7280_actlr, + .num_smmu = ARRAY_SIZE(sc7280_actlr), +}; static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, @@ -711,7 +767,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, - { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, + { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_500_impl0_data }, { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data }, From patchwork Wed Jun 26 14:30:20 2024 Content-Type: text/plain; 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Wed, 26 Jun 2024 14:31:12 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 07:31:07 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v12 6/6] iommu/arm-smmu: add support for PRR bit setup Date: Wed, 26 Jun 2024 20:00:20 +0530 Message-ID: <20240626143020.3682243-7-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> References: <20240626143020.3682243-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: g9GunnCogbgEISY9TRC3vTybAVZ22hg8 X-Proofpoint-GUID: g9GunnCogbgEISY9TRC3vTybAVZ22hg8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260107 Add an adreno-smmu-priv interface for drm/msm to call into arm-smmu-qcom and initiate the PRR bit setup or reset sequence as per request. This will be used by GPU to setup the PRR bit and related configuration registers through adreno-smmu private interface instead of directly poking the smmu hardware. Suggested-by: Rob Clark Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 23 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 6 +++++- 3 files changed, 30 insertions(+), 1 deletion(-) -- 2.34.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index bd101a161d04..752f909d26b6 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -28,6 +28,7 @@ #define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +#define GFX_ACTLR_PRR (1 << 5) static const struct actlr_config sc7280_apps_actlr_cfg[] = { { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB }, @@ -235,6 +236,27 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); } +static void qcom_adreno_smmu_set_prr(const void *cookie, phys_addr_t page_addr, bool set) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_device *smmu = smmu_domain->smmu; + u32 reg = 0; + + writel_relaxed(lower_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); + + writel_relaxed(upper_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); + + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR); + reg &= ~GFX_ACTLR_PRR; + if (set) + reg |= FIELD_PREP(GFX_ACTLR_PRR, 1); + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg); + +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -407,6 +429,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_fault_info = qcom_adreno_smmu_get_fault_info; priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + priv->set_prr = qcom_adreno_smmu_set_prr; actlrvar = qsmmu->data->actlrvar; if (!actlrvar) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index d9c2ef8c1653..3076bef49e20 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_SCTLR_M BIT(0) #define ARM_SMMU_CB_ACTLR 0x4 +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008 +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_RESUME_TERMINATE BIT(0) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index c637e0997f6d..d6e2ca9f8d8c 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -49,7 +49,10 @@ struct adreno_smmu_fault_info { * before set_ttbr0_cfg(). If stalling on fault is enabled, * the GPU driver must call resume_translation() * @resume_translation: Resume translation after a fault - * + * @set_prr: Extendible interface to be used by GPU to modify the + * ACTLR register bits, currently used to configure + * Partially-Resident-Region (PRR) feature's + * setup and reset sequence as requested. * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -67,6 +70,7 @@ struct adreno_smmu_priv { void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); + void (*set_prr)(const void *cookie, phys_addr_t page_addr, bool set); }; #endif /* __ADRENO_SMMU_PRIV_H */