From patchwork Thu Jun 27 07:58:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leith Bade X-Patchwork-Id: 13713917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E60A6C2BD09 for ; Thu, 27 Jun 2024 08:00:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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In the public schematic for the BPI-R3 (titled "BPI-R3-MT7986A", revision "V1.1", sheet 4), the SPI1_CS (GPIO32) pin of the MT7986 (U1E) is connected to the GbE_RESET net. Frank Wunderlich has told me, via the Banana Pi forum, that this GbE_RESET net connects to the MT7531 reset line in the private part of the shematic he has a copy of. Signed-off-by: Leith Bade Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ed79ad1ae871..951612ea1e66 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -206,7 +206,7 @@ switch: switch@31 { interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 32 GPIO_ACTIVE_HIGH>; }; }; From patchwork Thu Jun 27 07:58:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leith Bade X-Patchwork-Id: 13713919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D8D7C2BD09 for ; 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Thu, 27 Jun 2024 00:59:46 -0700 (PDT) Received: from localhost.localdomain ([2403:5816:cd6c:0:6d45:ae2f:1ead:bd58]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1faac9c4cf4sm7181895ad.290.2024.06.27.00.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 00:59:46 -0700 (PDT) From: Leith Bade To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, frank-w@public-files.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, didi.debian@cknow.org, Leith Bade Subject: [PATCH 2/4] arm64: dts: mediatek: mt7986: add gpio-hog for boot mode switch on BPI-R3 Date: Thu, 27 Jun 2024 17:58:54 +1000 Message-Id: <20240627075856.2314804-3-leith@bade.nz> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240627075856.2314804-1-leith@bade.nz> References: <20240627075856.2314804-1-leith@bade.nz> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_005952_046603_5D983D28 X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To avoid future pin conflicts with the boot mode dip switch (SW1), add a gpio-hog to document the two GPIOs it is connected to. If another device attempts to then claim the pins a log message will get printed. The BPI-R3 has a four position DIP switch (labelled SW1), that is used to configure the boot mode. The first two positions (labelled A & B) configure two bootstrap pins on the MT7986 that select which flash chip the boot ROM will load the second stage bootloader from. The third position toggles chip select lines to select between the NOR or NAND chip on the SPI0 bus. The fourth position toggles chip select lines to select between the eMMC chip or SD card on the MMC0 bus. Only the first two positions are connected to GPIO pins on the MT7986. In the public schematic for the BPI-R3 (titled "BPI-R3-MT7986A", revision "V1.1", sheet 4), these are the MT7986 (U1E) pins GPIO_0 (GPIO5) and GPIO_1 (GPIO6). This gpio-hog configures the two boot mode pins as inputs. Signed-off-by: Leith Bade --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 951612ea1e66..2cccbec39d34 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -235,6 +235,13 @@ &pcie_phy { }; &pio { + boot_mode_hog: boot-mode-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>, + <6 GPIO_ACTIVE_HIGH>; + input; + }; + i2c_pins: i2c-pins { mux { function = "i2c"; From patchwork Thu Jun 27 07:58:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leith Bade X-Patchwork-Id: 13713918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87238C2BD09 for ; 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Thu, 27 Jun 2024 00:59:55 -0700 (PDT) Received: from localhost.localdomain ([2403:5816:cd6c:0:6d45:ae2f:1ead:bd58]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1faac9c4cf4sm7181895ad.290.2024.06.27.00.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 00:59:55 -0700 (PDT) From: Leith Bade To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, frank-w@public-files.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, didi.debian@cknow.org, Leith Bade Subject: [PATCH 3/4] arm64: dts: mediatek: mt7986: add missing pin groups to BPI-R3 Date: Thu, 27 Jun 2024 17:58:55 +1000 Message-Id: <20240627075856.2314804-4-leith@bade.nz> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240627075856.2314804-1-leith@bade.nz> References: <20240627075856.2314804-1-leith@bade.nz> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_005956_085329_B4345AC5 X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The uart0, mdio and switch nodes are not connected to pin groups unlike most of the other nodes. Signed-off-by: Leith Bade --- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 2cccbec39d34..54087001cc8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -194,6 +194,8 @@ gmac1: mac@1 { }; mdio: mdio-bus { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; #address-cells = <1>; #size-cells = <0>; }; @@ -206,6 +208,8 @@ switch: switch@31 { interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&switch_pins>; reset-gpios = <&pio 32 GPIO_ACTIVE_HIGH>; }; }; @@ -335,6 +339,13 @@ mux { }; }; + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart"; @@ -349,6 +360,20 @@ mux { }; }; + mdio_pins: mdio-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + }; + + switch_pins: switch-pins { + mux { + function = "eth"; + groups = "switch_int"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function = "wifi"; @@ -471,6 +496,8 @@ &trng { }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; status = "okay"; }; From patchwork Thu Jun 27 07:58:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leith Bade X-Patchwork-Id: 13713920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77836C3064D for ; Thu, 27 Jun 2024 08:00:53 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 27 Jun 2024 01:00:00 -0700 (PDT) From: Leith Bade To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, frank-w@public-files.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, didi.debian@cknow.org, Leith Bade Subject: [PATCH 4/4] arm64: dts: mediatek: mt7986: add missing UART1 CTS/RTS pins in BPI-R3 Date: Thu, 27 Jun 2024 17:58:56 +1000 Message-Id: <20240627075856.2314804-5-leith@bade.nz> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240627075856.2314804-1-leith@bade.nz> References: <20240627075856.2314804-1-leith@bade.nz> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240627_010003_207638_9F99DE64 X-CRM114-Status: GOOD ( 14.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current definition of the uart1_pins pin group does not include the CTS and RTS pins that are available on header CON1. In the public schematic for the BPI-R3 (titled "BPI-R3-MT7986A", revision "V1.1", sheet 4), the UART1_RTS and UART1_CTS pins are connected via nets to the connector CON1 (sheet 14) UART0-RTS and UART0-CTS pins. The datasheet does not show these nets as connected to anything else. These pins can be configured for either UART1 or as a GPIO, with no other alternate usage listed in the pinctrl driver. By changing the pin group definition from uart1_rx_tx to uart1 the additional RTS and CTS pins are included. Signed-off-by: Leith Bade Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 54087001cc8c..48bd1e04963c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -349,7 +349,7 @@ mux { uart1_pins: uart1-pins { mux { function = "uart"; - groups = "uart1_rx_tx"; + groups = "uart1"; }; };