From patchwork Thu Jun 27 11:04:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13714190 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA55513E8B9; Thu, 27 Jun 2024 11:05:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486302; cv=none; b=bOc5cKfpaEs6I1aUSr1Mwp+bQYF7/R7Iv/lh27bVkTFcfbuyigFslMHTQ1OlsE+uukrMy85Xuzn/QQs8YII3H44lc+aCm2AWZFVGP8hyxQAIxfmEt0niOBPUHVaKP/ATjmjWyoiFRmnuBDDFhNcsCoKYtZKh9Bf1lxpQ31HMXLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486302; c=relaxed/simple; bh=W149TVbhn1TxRc4WkqnwWJldebG7cEb6TOniVY0sl9c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C+pHuOm6pN59aU4/Imd8TScNtz887gKavpaEavDTmlYXSN7T642k+LiA3ehX0NM//ylqxrMYrnTKf18wTvR2/EISVQab42G5Y/abnd24TCEXvac3iwK6zeOpPJN/pk6MQWL7U8Bd9HGH1HCvrQGFe5H4MYbM6H1wXPyYz/asOf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=I1ny2F6p; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I1ny2F6p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1209BC4AF0B; Thu, 27 Jun 2024 11:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719486302; bh=W149TVbhn1TxRc4WkqnwWJldebG7cEb6TOniVY0sl9c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I1ny2F6pz/4AjpJgRVqQqxfOUE/1ClTXYF+VYWvWEiewS0PHyetC2wpY0XxY1sbS/ MgPlpBQ8xi6o6sQUhAbKFbUpErQf6PfIhd+Kr6j9w4WgcDY5Rdit3q+99k1M4LAcVL ZnrN7G+0alPgWOzTQTylQOt/X1aMH08/H4VxzKe13PQtOm2r5xEEM3NugQJej7yqbv ce6Y9AeBqsTbalbsxI8MSkqrpKvKHnPFqRcEe7uDNmvBGSZ0kzshm/2UtgCuhFRyEV hNV4uvGmj3U8DXS3k3nvmgwC8oOUJmha0e4IXpNhf2ah5OiE2rWOb8eoD75QHKKOWL wQ5lzVVFNb09w== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v4 1/4] dt-bindings: clock: airoha: Add reset support to EN7581 clock binding Date: Thu, 27 Jun 2024 13:04:22 +0200 Message-ID: <28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce reset capability to EN7581 device-tree clock binding documentation. Add reset register mapping between misc scu and pb scu ones in order to follow the memory order. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Fixes: 0a382be005cf ("dt-bindings: clock: airoha: add EN7581 binding") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Lorenzo Bianconi --- .../bindings/clock/airoha,en7523-scu.yaml | 25 ++++++- .../dt-bindings/reset/airoha,en7581-reset.h | 66 +++++++++++++++++++ 2 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 3f4266637733..84353fd09428 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -35,7 +35,7 @@ properties: reg: minItems: 2 - maxItems: 3 + maxItems: 4 "#clock-cells": description: @@ -43,6 +43,10 @@ properties: clocks. const: 1 + '#reset-cells': + description: ID of the controller reset line + const: 1 + required: - compatible - reg @@ -60,6 +64,8 @@ allOf: - description: scu base address - description: misc scu base address + '#reset-cells': false + - if: properties: compatible: @@ -70,6 +76,7 @@ allOf: items: - description: scu base address - description: misc scu base address + - description: reset base address - description: pb scu base address additionalProperties: false @@ -83,3 +90,19 @@ examples: <0x1fb00000 0x1000>; #clock-cells = <1>; }; + + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + scuclk: clock-controller@1fa20000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fa20000 0x0 0x400>, + <0x0 0x1fb00000 0x0 0x90>, + <0x0 0x1fb00830 0x0 0x8>, + <0x0 0x1fbe3400 0x0 0xfc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h new file mode 100644 index 000000000000..6544a1790b83 --- /dev/null +++ b/include/dt-bindings/reset/airoha,en7581-reset.h @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 AIROHA Inc + * Author: Lorenzo Bianconi + */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ + +/* RST_CTRL2 */ +#define EN7581_XPON_PHY_RST 0 +#define EN7581_CPU_TIMER2_RST 1 +#define EN7581_HSUART_RST 2 +#define EN7581_UART4_RST 3 +#define EN7581_UART5_RST 4 +#define EN7581_I2C2_RST 5 +#define EN7581_XSI_MAC_RST 6 +#define EN7581_XSI_PHY_RST 7 +#define EN7581_NPU_RST 8 +#define EN7581_I2S_RST 9 +#define EN7581_TRNG_RST 10 +#define EN7581_TRNG_MSTART_RST 11 +#define EN7581_DUAL_HSI0_RST 12 +#define EN7581_DUAL_HSI1_RST 13 +#define EN7581_HSI_RST 14 +#define EN7581_DUAL_HSI0_MAC_RST 15 +#define EN7581_DUAL_HSI1_MAC_RST 16 +#define EN7581_HSI_MAC_RST 17 +#define EN7581_WDMA_RST 18 +#define EN7581_WOE0_RST 19 +#define EN7581_WOE1_RST 20 +#define EN7581_HSDMA_RST 21 +#define EN7581_TDMA_RST 22 +#define EN7581_EMMC_RST 23 +#define EN7581_SOE_RST 24 +#define EN7581_PCIE2_RST 25 +#define EN7581_XFP_MAC_RST 26 +#define EN7581_USB_HOST_P1_RST 27 +#define EN7581_USB_HOST_P1_U3_PHY_RST 28 +/* RST_CTRL1 */ +#define EN7581_PCM1_ZSI_ISI_RST 29 +#define EN7581_FE_PDMA_RST 30 +#define EN7581_FE_QDMA_RST 31 +#define EN7581_PCM_SPIWP_RST 32 +#define EN7581_CRYPTO_RST 33 +#define EN7581_TIMER_RST 34 +#define EN7581_PCM1_RST 35 +#define EN7581_UART_RST 36 +#define EN7581_GPIO_RST 37 +#define EN7581_GDMA_RST 38 +#define EN7581_I2C_MASTER_RST 39 +#define EN7581_PCM2_ZSI_ISI_RST 40 +#define EN7581_SFC_RST 41 +#define EN7581_UART2_RST 42 +#define EN7581_GDMP_RST 43 +#define EN7581_FE_RST 44 +#define EN7581_USB_HOST_P0_RST 45 +#define EN7581_GSW_RST 46 +#define EN7581_SFC2_PCM_RST 47 +#define EN7581_PCIE0_RST 48 +#define EN7581_PCIE1_RST 49 +#define EN7581_CPU_TIMER_RST 50 +#define EN7581_PCIE_HB_RST 51 +#define EN7581_XPON_MAC_RST 52 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ From patchwork Thu Jun 27 11:04:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13714191 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 443ED13E8B9; Thu, 27 Jun 2024 11:05:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486306; cv=none; b=kW0fSyaBCqQu69MUWqcgSmD4Oh50jEUKOMPH+f3pM4iRP2hRsYlIjiV/5yNcPL86dKlfFpg4LrJ+FKJ4u5RnDClaWcLxGHIheFkH326vzL97ekPl1j8A+OkByEpj8qdvJLv7zBRiLxhSFBrUA3IlWxqNEp1eOdOWyN+L5fHZ6no= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486306; c=relaxed/simple; bh=rJLnqNECMxwgylubhCINuV4UU6Ut3xQwA21m5Yr0idU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tozkW/4GOJi8AagU5rYN3xptvSRkhjoTlAAYF2ThBKkogNLhfbFbkC9Z/qg1/h2VRSAJm1TCN6GKr/FWw19b7ZStlgY7FG+B7zNws8hnpFXvkdNnJkBR1yTECm27qXbNDPeRUEd8km82Zv2xEbGHSBJWEL2nhE5XYy4InxK0IJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XhJJ2LYS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XhJJ2LYS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C3935C2BBFC; Thu, 27 Jun 2024 11:05:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719486306; bh=rJLnqNECMxwgylubhCINuV4UU6Ut3xQwA21m5Yr0idU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XhJJ2LYSjal5rlgCzHpO/YmxXBFA1DGMqNS62tY2svbhHXqWAVJ1+fQ9k0up+itQM BJYcFB9Cdnf/4f/pGzc9Y7YQOQaS0Z9Uxoa0SOh9w4ySBGnznEmWBR1Wt6KU9uW5vR ZZWpFEk+OYoB0+jVKYWSuWDDWKWcR+7BgdFL+cgvMzmYYk8owkqM5IGoP3/fnKEZKd XaIzhz5onEF/o1czt6su4NAfczjRiDY1+rDOZUP4mg0+TUJT9stGaCQ5+yglMVqsCx LJ6GxvsTMhEa5fQilzLxjuTdNe3XhZHGeN6Z9dudaSgUsV+HCeXwEbMW51HWihA/l7 U9vU0oZJvYbIw== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v4 2/4] clk: en7523: Add reset-controller support for EN7581 SoC Date: Thu, 27 Jun 2024 13:04:23 +0200 Message-ID: <4f735d17e549ea53769bf5a3f50406debb879a44.1719485847.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce reset API support to EN7581 clock driver. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 192 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 187 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index ccc394692671..5cd501b86557 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -5,7 +5,11 @@ #include #include #include +#include #include +#include + +#define RST_NR_PER_BANK 32 #define REG_PCI_CONTROL 0x88 #define REG_PCI_CONTROL_PERSTOUT BIT(29) @@ -40,6 +44,9 @@ #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) +#define REG_RST_CTRL2 0x00 +#define REG_RST_CTRL1 0x04 + struct en_clk_desc { int id; const char *name; @@ -64,8 +71,20 @@ struct en_clk_gate { struct clk_hw hw; }; +struct en_rst_data { + const u16 *bank_ofs; + const u16 *idx_map; + void __iomem *base; + struct reset_controller_dev rcdev; +}; + struct en_clk_soc_data { const struct clk_ops pcie_ops; + struct { + const u16 *bank_ofs; + const u16 *idx_map; + u16 idx_map_nr; + } reset; int (*hw_init)(struct platform_device *pdev, void __iomem *base, void __iomem *np_base); }; @@ -168,6 +187,69 @@ static const struct en_clk_desc en7523_base_clks[] = { } }; +static const u16 en7581_rst_ofs[] = { + REG_RST_CTRL2, + REG_RST_CTRL1, +}; + +static const u16 en7581_rst_map[] = { + /* RST_CTRL2 */ + [EN7581_XPON_PHY_RST] = 0, + [EN7581_CPU_TIMER2_RST] = 2, + [EN7581_HSUART_RST] = 3, + [EN7581_UART4_RST] = 4, + [EN7581_UART5_RST] = 5, + [EN7581_I2C2_RST] = 6, + [EN7581_XSI_MAC_RST] = 7, + [EN7581_XSI_PHY_RST] = 8, + [EN7581_NPU_RST] = 9, + [EN7581_I2S_RST] = 10, + [EN7581_TRNG_RST] = 11, + [EN7581_TRNG_MSTART_RST] = 12, + [EN7581_DUAL_HSI0_RST] = 13, + [EN7581_DUAL_HSI1_RST] = 14, + [EN7581_HSI_RST] = 15, + [EN7581_DUAL_HSI0_MAC_RST] = 16, + [EN7581_DUAL_HSI1_MAC_RST] = 17, + [EN7581_HSI_MAC_RST] = 18, + [EN7581_WDMA_RST] = 19, + [EN7581_WOE0_RST] = 20, + [EN7581_WOE1_RST] = 21, + [EN7581_HSDMA_RST] = 22, + [EN7581_TDMA_RST] = 24, + [EN7581_EMMC_RST] = 25, + [EN7581_SOE_RST] = 26, + [EN7581_PCIE2_RST] = 27, + [EN7581_XFP_MAC_RST] = 28, + [EN7581_USB_HOST_P1_RST] = 29, + [EN7581_USB_HOST_P1_U3_PHY_RST] = 30, + /* RST_CTRL1 */ + [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, + [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, + [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, + [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, + [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, + [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, + [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, + [EN7581_UART_RST] = RST_NR_PER_BANK + 12, + [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, + [EN7581_GDMA_RST] = RST_NR_PER_BANK + 14, + [EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16, + [EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17, + [EN7581_SFC_RST] = RST_NR_PER_BANK + 18, + [EN7581_UART2_RST] = RST_NR_PER_BANK + 19, + [EN7581_GDMP_RST] = RST_NR_PER_BANK + 20, + [EN7581_FE_RST] = RST_NR_PER_BANK + 21, + [EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22, + [EN7581_GSW_RST] = RST_NR_PER_BANK + 23, + [EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25, + [EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26, + [EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27, + [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, + [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, + [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, +}; + static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) { const struct en_clk_desc *desc = &en7523_base_clks[i]; @@ -370,7 +452,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev, void __iomem *pb_base; u32 val; - pb_base = devm_platform_ioremap_resource(pdev, 2); + pb_base = devm_platform_ioremap_resource(pdev, 3); if (IS_ERR(pb_base)) return PTR_ERR(pb_base); @@ -423,6 +505,95 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } +static int en7523_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + u32 val; + + val = readl(addr); + if (assert) + val |= BIT(id % RST_NR_PER_BANK); + else + val &= ~BIT(id % RST_NR_PER_BANK); + writel(val, addr); + + return 0; +} + +static int en7523_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, true); +} + +static int en7523_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return en7523_reset_update(rcdev, id, false); +} + +static int en7523_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; + + return !!(readl(addr) & BIT(id % RST_NR_PER_BANK)); +} + +static int en7523_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); + + if (reset_spec->args[0] >= rcdev->nr_resets) + return -EINVAL; + + return rst_data->idx_map[reset_spec->args[0]]; +} + +static const struct reset_control_ops en7523_reset_ops = { + .assert = en7523_reset_assert, + .deassert = en7523_reset_deassert, + .status = en7523_reset_status, +}; + +static int en7523_reset_register(struct platform_device *pdev, + const struct en_clk_soc_data *soc_data) +{ + struct device *dev = &pdev->dev; + struct en_rst_data *rst_data; + void __iomem *base; + + /* no reset lines available */ + if (!soc_data->reset.idx_map_nr) + return 0; + + base = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(base)) + return PTR_ERR(base); + + rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); + if (!rst_data) + return -ENOMEM; + + rst_data->bank_ofs = soc_data->reset.bank_ofs; + rst_data->idx_map = soc_data->reset.idx_map; + rst_data->base = base; + + rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr; + rst_data->rcdev.of_xlate = en7523_reset_xlate; + rst_data->rcdev.ops = &en7523_reset_ops; + rst_data->rcdev.of_node = dev->of_node; + rst_data->rcdev.of_reset_n_cells = 1; + rst_data->rcdev.owner = THIS_MODULE; + rst_data->rcdev.dev = dev; + + return devm_reset_controller_register(dev, &rst_data->rcdev); +} + static int en7523_clk_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -456,11 +627,17 @@ static int en7523_clk_probe(struct platform_device *pdev) r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); + return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n", + pdev->name); + + r = en7523_reset_register(pdev, soc_data); + if (r) { + of_clk_del_provider(node); + return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n", + pdev->name); + } - return r; + return 0; } static const struct en_clk_soc_data en7523_data = { @@ -479,6 +656,11 @@ static const struct en_clk_soc_data en7581_data = { .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, + .reset = { + .bank_ofs = en7581_rst_ofs, + .idx_map = en7581_rst_map, + .idx_map_nr = ARRAY_SIZE(en7581_rst_map), + }, .hw_init = en7581_clk_hw_init, }; From patchwork Thu Jun 27 11:04:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13714192 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03A5B13E8B9; Thu, 27 Jun 2024 11:05:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486310; cv=none; b=FyKVp6T3ro+YH8F31OUBED+eL2BRBrX2qyiqRFknq+i6QMRGEQ8w/3ZW1XY+oOBT87VCn2/t32GOZOEZCzfTHBGi1nFgQHCCPs21v5zMW6wF0+4l/BMfai0JdV84PyUVdyqhVLjCPyS58nF5jciOhr1awg216GITfxjF2IRS1hY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486310; c=relaxed/simple; bh=ek4+PAY8/cvLVH71a4c19ArzDNAgRpGILNbEZyd11sY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V9dBzBsVMhT1uNikPu4ZadrDnjHWjVCTkP2Qx96IcvLquFaSVYAmmwx4desKinvK41Bs0L58VZyJb628ycVM9xnzMXqB/d2bWyJjjTyJUrb1x0SAlutUIMHCkP2W8M+eNSgF8qtujmpC8X63CyBUrpo4roVt5z8OQUWJjmDMdBI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aJGm5V25; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aJGm5V25" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D79AC2BBFC; Thu, 27 Jun 2024 11:05:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719486309; bh=ek4+PAY8/cvLVH71a4c19ArzDNAgRpGILNbEZyd11sY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aJGm5V25tVsLgQelED4y4Z6pYyluil36uImoHRkDs2A3cgHLAuOxxkzwF3Zm6Ys9h sRwULjUNEyrXpmbM3XwxE+ebFzlHnPaL5b+7+3mPe4Vs/qY33vsHq/QiL9/C5D/ahG 7pBthLmBj5IOpeW1xJTt8mjbn4KIkeIvHpGlQe/y6XwOVtSCHZvbEMzOx4iDnMjQbF yfKhBNcGUK4FQhSX+SINCdyc5hBuyOy/9/dPxJNAAoZ4+t2oy3qPK2ztNC+qSZ/mYL 2Lbqp8JN+AdB2ibQ4EkoLTjrgEAgFR5YgxvgIT+sZ3f6dSXhL+jRSZr3YQ+hziOUtB DMOJz+WZGlY7w== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v4 3/4] clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC Date: Thu, 27 Jun 2024 13:04:24 +0200 Message-ID: <16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Get rid of prepare and unpreare callbacks for PCIe clock since they can be modeled as a reset line cosumed by the PCIe driver (pcie-mediatek-gen3) Reviewed-by: AngeloGioacchino Del Regno Tested-by: Zhengping Zhang Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 41 ++-------------------------------------- 1 file changed, 2 insertions(+), 39 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 5cd501b86557..b134821b23c1 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -361,9 +361,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev, cg->base = np_base; cg->hw.init = &init; - if (init.ops->disable) - init.ops->disable(&cg->hw); - init.ops->unprepare(&cg->hw); + if (init.ops->unprepare) + init.ops->unprepare(&cg->hw); if (clk_hw_register(dev, &cg->hw)) return NULL; @@ -381,23 +380,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw) return (val & mask) == mask; } -static int en7581_pci_prepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val & ~mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - usleep_range(5000, 10000); - - return 0; -} - static int en7581_pci_enable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -414,23 +396,6 @@ static int en7581_pci_enable(struct clk_hw *hw) return 0; } -static void en7581_pci_unprepare(struct clk_hw *hw) -{ - struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); - void __iomem *np_base = cg->base; - u32 val, mask; - - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 | - REG_RESET_CONTROL_PCIEHB; - val = readl(np_base + REG_RESET_CONTROL1); - writel(val | mask, np_base + REG_RESET_CONTROL1); - mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2; - writel(val | mask, np_base + REG_RESET_CONTROL1); - val = readl(np_base + REG_RESET_CONTROL2); - writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2); - msleep(100); -} - static void en7581_pci_disable(struct clk_hw *hw) { struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw); @@ -651,9 +616,7 @@ static const struct en_clk_soc_data en7523_data = { static const struct en_clk_soc_data en7581_data = { .pcie_ops = { .is_enabled = en7581_pci_is_enabled, - .prepare = en7581_pci_prepare, .enable = en7581_pci_enable, - .unprepare = en7581_pci_unprepare, .disable = en7581_pci_disable, }, .reset = { From patchwork Thu Jun 27 11:04:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13714193 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50805143C7D; Thu, 27 Jun 2024 11:05:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486313; cv=none; b=dyPTeVgRllvsJQQT9GnJiNrKUG4+FtK7jqGpXhKOr2HDEhLZkIZoYyHltPxC8mGqSzJxc4gc11TgSaFzcbok8l3vhqTMFLMAcGbwyjS8+vdlXbKjGIEX2vvcbGdNDErVqliS34cH5fyQmDoxAl5fQM/EiSHKY2W/x49mLb0yUaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719486313; c=relaxed/simple; bh=CHPj1ScjgYdVyznC3pgzpXrR/68/AlaRg0dR6cJ7qLc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J9JyBH5Wvi6cigocd9I8pjIlhEneF8XUu7+eUhKDBQ8fnpx44yJopLZ8iPZPtwlksy5XRk/0GJZ0zJpE/Mt4scaobnzL2EswWNzS91Elk9sQ3WxK+W7dvSw/RSdS6rOaqeuQKDnh+6DX9dZt6TTE8M3fFQevVIq0He05vPPUN84= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T8XMc63r; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T8XMc63r" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D26D4C2BBFC; Thu, 27 Jun 2024 11:05:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719486313; bh=CHPj1ScjgYdVyznC3pgzpXrR/68/AlaRg0dR6cJ7qLc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T8XMc63rUSyUjf3w5SjrCw9rLNMNNrHG2wu4Ani4jr+NFkzmU9opOMAJd6YXCGKOY UvksEtyOvS1wJLAQcfgHBim+uBvp7DCHS6036/foKPAO/2s3htlsSNV42V8G1NCuSz 00nZ9axcC2P6SAOQj0qaUl5R+tWd9ovzz3eyJ0R66mRdK3+zAZMyPEBxluF+UNR/ke o2YH4vdA7+f2Uxe6zFyPTj0kd/eiR7i5N9QKJxHrVcp5aGS4wG9ORZewWd050RCtK/ qVTIuXIW8AN3Od9Nwb9X1miOZCgoIjjxEh0vsVrwjAm7xzJ1la5QIuTPWOtp0Bh9OJ TwaVRgqFCPDkg== From: Lorenzo Bianconi To: linux-clk@vger.kernel.org Cc: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.bianconi83@gmail.com, conor@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name, john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com, will@kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v4 4/4] clk: en7523: Remove PCIe reset open drain configuration for EN7581 Date: Thu, 27 Jun 2024 13:04:25 +0200 Message-ID: <43276af5f08a554b4ab2e52e8d437fff5c06a732.1719485847.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCIe reset open drain configuration will be managed by pinctrl driver. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index b134821b23c1..e10c73c29ee2 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -37,8 +37,6 @@ #define REG_PCIE1_MEM_MASK 0x0c #define REG_PCIE2_MEM 0x10 #define REG_PCIE2_MEM_MASK 0x14 -#define REG_PCIE_RESET_OPEN_DRAIN 0x018c -#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0) #define REG_NP_SCU_PCIC 0x88 #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) @@ -85,8 +83,7 @@ struct en_clk_soc_data { const u16 *idx_map; u16 idx_map_nr; } reset; - int (*hw_init)(struct platform_device *pdev, void __iomem *base, - void __iomem *np_base); + int (*hw_init)(struct platform_device *pdev, void __iomem *np_base); }; static const u32 gsw_base[] = { 400000000, 500000000 }; @@ -411,7 +408,6 @@ static void en7581_pci_disable(struct clk_hw *hw) } static int en7581_clk_hw_init(struct platform_device *pdev, - void __iomem *base, void __iomem *np_base) { void __iomem *pb_base; @@ -434,10 +430,6 @@ static int en7581_clk_hw_init(struct platform_device *pdev, writel(0x28000000, pb_base + REG_PCIE2_MEM); writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK); - val = readl(base + REG_PCIE_RESET_OPEN_DRAIN); - writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK, - base + REG_PCIE_RESET_OPEN_DRAIN); - return 0; } @@ -577,7 +569,7 @@ static int en7523_clk_probe(struct platform_device *pdev) soc_data = device_get_match_data(&pdev->dev); if (soc_data->hw_init) { - r = soc_data->hw_init(pdev, base, np_base); + r = soc_data->hw_init(pdev, np_base); if (r) return r; }