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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , William Tu , Tariq Toukan Subject: [PATCH net V2 1/7] net/mlx5: IFC updates for changing max EQs Date: Thu, 27 Jun 2024 21:02:34 +0300 Message-ID: <20240627180240.1224975-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|IA1PR12MB8189:EE_ X-MS-Office365-Filtering-Correlation-Id: d07541f7-002c-404c-e9f7-08dc96d392ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: bnC9G+31DmeZrYKl4cJoYB/edVPAC8XL/7oJCyA9aZVYHDPptrvC3r+vHTu7SZriDKq5Gxym6ye16t2WtAVMtZyvLdz7H9Iqd0UCbsI9/SMTU6TSXQgOXTsKZntlUjF81XFkxCQ4sVwDmAXtCNC2kOFV0gyP/f83MlYFYnuvX0H5LsvC37Kx6cOtshkPq2HrCchgMPPM8X4Qil9EMGe4RQDHknwUt4Empu40HNQh0erfT/ShD5BDjTQBJZQRuLIRgisdBzyMA7HxneNsO+rpmi64F964kCxr3xhx02L5Bcw8oo2SXb1sgXMO01kbc74MiuVwC+fv6EIhvLguZODLt+pWZJzbLuuLjUWs6tvAKKUZGWzeLTBCM9L0sDXnMmkbjZNf0Ph/5uC4OjuXSjb3Ye586B3rlShcFT4aylmmYPP1pSBytUkPz/f1wATbuWPLPiat4cc4ZLud7oxdqL3ggqkhORT1C78+QzOqdL0pdch6TGnIKQahSKNbCSXgZpDkGi2uop204VNHxVNIjMuQOOhJCviD099X5UjuTW9VuHJWg5UbdXeUCkGz5/NH8UBv+uXyb9kSk7FZJLWVc870WLPIma4I8dmsLfiV/0JdjkpPnkhn44Lm9xpSY8H8tdzr3mA21vbG6LZyQWq5t9E8MMYydE7ral18auPw0FW7SzayjR0/XPTSxjeIWvOuX8UqUz8dnKBUruze4GmnoC5mlryTFdgTc4hUgCHSReMX79D2LREsxdZTiVBA120iTApkfWva2driOy/2SJXevMDryZfpLMg1OmD6F0W+zma1wRb8g7zRFA9e8NBlP1ka2BpgOkz4V33ctVZxk+kaamgGxSunRj3hdHiL20he2FIRe/JoD3guHGSFps2rwG1A8HiJpgBhOu076wd9zMNGKrBbSllpxOckpnpTNA5tgSdDKyOJ1kzsDBsG78YS1FRHdQXu7ndESsvs3YHw4kqobshD6vcnIjG2jKMpBDbGRChqhjuAZ8BDl1uNF34EygnxFX7YqSXoMPr/etfoA0GShz1gYSdEfuVKYNjpZeq3rom3g8PwRCci/t5pv7W7FOwsnvJNt4V62a7oVg3fl13Pibis95OVgaxi53ZHW2gPo76maJoc+b04D4QopmXhAN/jVG3kFXuIHg8rYbyaaR00B9ah7dhmw8KaXHnr6/Jk4NZVxINDnLJ6HVgAaN7gDUQMt+SEixk/aEpAofJOcJS69KzeZJR5vEFgL2ozhPdfGo8a0uf6IiZW4uOcqGL2XMUGx8ZJuMiUBS2Sqt4xJ/nwVhdQH73xhh+yfhQUWe/zor40vPM= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:22.6070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d07541f7-002c-404c-e9f7-08dc96d392ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8189 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens Expose new capability to support changing the number of EQs available to other functions. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 5df52e15f7d6..d45bfb7cf81d 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -2029,7 +2029,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 pcc_ifa2[0x1]; u8 reserved_at_3f1[0xf]; - u8 reserved_at_400[0x400]; + u8 reserved_at_400[0x40]; + + u8 reserved_at_440[0x8]; + u8 max_num_eqs_24b[0x18]; + u8 reserved_at_460[0x3a0]; }; enum mlx5_ifc_flow_destination_type { From patchwork Thu Jun 27 18:02:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13714964 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2089.outbound.protection.outlook.com [40.107.94.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADB6419AA57 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , William Tu , Tariq Toukan Subject: [PATCH net V2 2/7] net/mlx5: Use max_num_eqs_24b capability if set Date: Thu, 27 Jun 2024 21:02:35 +0300 Message-ID: <20240627180240.1224975-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|DM4PR12MB6301:EE_ X-MS-Office365-Filtering-Correlation-Id: 76a0ad8e-ab59-47e6-6bd2-08dc96d3907b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: NLrSiHe7Wp1DEYY+7S50lDfISn++MGYKHg2udVHwSIjxCi4re/umUFyZwHBvB0929wYpjcQsNoe1kk8llRfbFi2CQlgO/TnyxJxfdvRk5ubqCML/cg4X6BkxmIpIL6bp7QaOdjsws6ncjcXLZgqwQxX6VPGGPOuiJjD2KdOf/krAbcQUNAJ+6Mq6tqVwNrrcGLVUOh+QjiBB5j2oHp8qTB+3C5B5I8IlB64JmK2FjJhDzhwSxzZeBRIP5GEot5CXeePNTuY6OnqCe5U+yM7kAA8LrVoO926n8a47SxfNwE+W5TgvEyV1h96Z44Hq5Q2cLAIA27q8aNcOnB1eePi5o3cx1g2qWcsLU41/D+ZgbT2RxEcT+ZelOde6tYpZ/co+gYRrq6vPrw5aDUKEHNn5GFhODE9CmFJzTgTJaaeV2pBFLphbfjTrEaAcAjiAcsOmZv8puXBw/Ps0qJ93JMT5NiaQNvAC069bUpjBUdQD1LLm+ivQp7eSLx9rdxu70g2vsY6yOC/qhLMnOJH+hjIx6CPrCt5nQA2sImmCn6MOsgTqsy5H68KfsEln6B/RC5E8/1pToDWeG7vhMrqt7Oyra1mtV4xynsdEsxtgquAQ/+kK5PzB+of4AxVqPyfUbA1Zc4yrnbo969s5egkVtByuVr968PB05RiZYpjnxhLBSMEDqqP+bI6gZ4ixLWAfgZXYB6q/b8mz82zyPs7eWuGvxgAx0E6H7LvN+iPuOW1v1kdKPvMPanRBcLrsnzHN5J3In/4+VbTWVYIsHKyLVaoQuftNXqOGnafdbHeMl9Eqp0VIFgo9f6vPqza/VUcnx8d+JrpgHir5L4ygH6+fJelN/knpQcYT32glIIjw8yPqSuD2VwqpcyHrpppXu1Z/QeC1JI8lIUnLeDbm3cswdR92t4b6Y0MjVdr2aI/zKyplTr2+7CX/1PRrvsmxr4VY1aMJKJj1KH3i94BUUpmQqg88CFuIkPSraAXSSxIkjwXU44p5L/yH06LUq8LrqDvtWcFYpKvYqcBfY0yieihLl8m+F8cRQYQ2yFjWb8HN8mxwGa34u2qt0zmrX/y56IccRmWYkT/9PUemkOJ6es3YssXzg71/woJm14FTaXuQ4yb18iDg9IMEkPJxxVAevPGQAg7CHMYPpa/pjBKf89CxWJ1INvcO+sGTP/soLZh+9PLFEMB3qiXwGQS2W6FNbGUwpobl6BPGTdcZodz0CkFsjuQB7MfxdguRfR/kXc2em4kBUh53E5ffxxid8fuArZY3g+3xZTsqHemhrPFxuCewFu9cSy64l92+1umsZyeH20rsJK2o0T82/7etl6wHUDXbmL6qvJIes1hDl0yDUrIeAVqKjOXnamOyNt1NyIVzV32bNBSRphlvtMbbLDWb1lub/eLKOn1KoLdohbCeST0Q/d7CTEGhmErXq81cGF+Qquu0PflvYeiZFXez9I+aEjLqKt8G X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:18.4166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76a0ad8e-ab59-47e6-6bd2-08dc96d3907b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6301 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens A new capability with more bits is added. If it's set use that value as the maximum number of EQs available. This cap is also writable by the vhca_resource_manager to allow limiting the number of EQs available to SFs and VFs. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 4 +--- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 +--- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 5693986ae656..ac1565c0c8af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -1197,9 +1197,7 @@ static int get_num_eqs(struct mlx5_core_dev *dev) if (!mlx5_core_is_eth_enabled(dev) && mlx5_eth_supported(dev)) return 1; - max_dev_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); + max_dev_eqs = mlx5_max_eq_cap_get(dev); num_eqs = min_t(int, mlx5_irq_table_get_num_comp(eq_table->irq_table), max_dev_eqs - MLX5_MAX_ASYNC_EQS); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index c38342b9f320..a7fd18888b6e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -383,4 +383,14 @@ static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vpo : vport; } +static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev) +{ + if (MLX5_CAP_GEN_2(dev, max_num_eqs_24b)) + return MLX5_CAP_GEN_2(dev, max_num_eqs_24b); + + if (MLX5_CAP_GEN(dev, max_num_eqs)) + return MLX5_CAP_GEN(dev, max_num_eqs); + + return 1 << MLX5_CAP_GEN(dev, log_max_eq); +} #endif /* __MLX5_CORE_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index fb8787e30d3f..401d39069680 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -711,9 +711,7 @@ int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table) int mlx5_irq_table_create(struct mlx5_core_dev *dev) { - int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , Tariq Toukan Subject: [PATCH net V2 3/7] net/mlx5: Use max_num_eqs_24b when setting max_io_eqs Date: Thu, 27 Jun 2024 21:02:36 +0300 Message-ID: <20240627180240.1224975-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|DS7PR12MB5909:EE_ X-MS-Office365-Filtering-Correlation-Id: fa7355ea-124a-46ea-518c-08dc96d397a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: kV+kGYnn3YwHYU8jxquxdHUEyLMU0szGZQNLLf46f76FdRUv+WdEKLNQZ0rBkLxulcTlNR/r2x99tHli4LrmXdLH6vfLecjAu53G00Z1AN+qnPzxQwfgWh1p/k01x9yu8RB7xXui+vrTx8WNh4nsSKGWGfLFra1aHhdUdjfQuAClVcfRyMagtidTpDInpJT2+b3V5zy1R6szTaAx+LhncE0tP7pWr0jcDSQB06IiKICGhdIMcSO2lZ3qhMKRKlucIgZeKR72p16PTlcJxcFLYD/C9bHWdBjs6M1MU4bBpGQI2CyzPr8djPI7gSHLcuDSXA7OvaXl1nsk0E2N2RTBn0XeTXm92E6HgKTuiGnzviBTr7CNwYHUaceQQ4LuLpoGcy8aUXk36oaUb8SGKDKBHPUfbyMuL8lqvPwgr+4/tXmMT+CvXoGATUltMl3kZ+g9J495+1Rat5ei2U9ZL+1cNr5DY7Oqc6d105im62BqbWS9RgbNaJ8wnRR8SMxj/kYGsKB9bbu/7BucnvnOQU7AwGC+yRcoHN8glU408OsBBYUalNke/zS1D8qCIM9fQaCYCEPqhDyiE/av4qGfToQvZdjQh4Fhk7bEx3OoyR0rsMV3IC8v4MfqGTzl+Doek81nGaPI2SkbQ5DNzf3faqs2hf9veLcssiueQXD2P76IQmKPBofAu9z5CHjVlxUEVxk3rtTkUkZMcjKlZWRS9i9NjeXdFkFUfApskgxsZgQWJdEI+FgjHI/iKhV4MUoWGqe6iORHx4zlh9fHaWz6shHaHTrGNsGVv6DU5Oqp2bWlvnKAR3qfrsWoiP2++tJwGI1nXxUpPipgYNoGu7eShgWwlC6APQ1q247meGEgRk5mqhYdkaFae3zn2WBncUy3xNwFVD66HqUHhUwB06fZnI8ok0TeQooRPAoERVHrkpdFOj5Lww54Hhc361iXtX9F5+N7c7SfiPd+b8yhNI0+QABHGyP5yjW2zlkBYDPet+J8u14fwddmWGBRb55gfzGTQRejERu4k20MOEheh3dlIKI/Iz38EFxdRHhvX8xNQjvQ9RyXVxElI2hZjcX5T0V9PUt7/BN9vbkDuu0/za4nmwpTkiKNpxZqmPTGc5Mb1r5AQalbz+2bZMOq4MSZefBbQ4uCpZPHqejbMjW2gIWjfuCAprKacFSc6s/PsNQj4delUN4lvNTvbzQJWgH8wAp145kh1C6lpo9OUFKqvw7sY2YZin1Fi20TcmPg2UY2TcUYv+8M7KpNg+3PIYdhHtfYhhvnKEhqLxorrh+4HCUaJSpCbC7ttu/1GVrPnvNqRwkKCIYCmM2UO5tyZjAvyXAA5j3gpZh2cECPFUDY48KN69/xJW9QmyOU8DjgSpbcV/q/GkZFV+L5FDZ+K+xzvbVGlGQijdFLdMYjvItw8l5xlSoorVvbhc07554JMzwxVBqcbBoduwyBs+YFMknE2sHSWKBg X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:30.5133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa7355ea-124a-46ea-518c-08dc96d397a5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5909 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens Due a bug in the device max_num_eqs doesn't always reflect a written value. As a result, setting max_io_eqs may not work but appear successful. Instead write max_num_eqs_24b, which reflects correct value. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/eswitch_offloads.c | 22 ++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 592143d5e1da..72949cb85244 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4600,20 +4600,26 @@ mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, u32 *max_io_eqs, return -EOPNOTSUPP; } + if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) { + NL_SET_ERR_MSG_MOD(extack, + "Device doesn't support getting the max number of EQs"); + return -EOPNOTSUPP; + } + query_ctx = kzalloc(query_out_sz, GFP_KERNEL); if (!query_ctx) return -ENOMEM; mutex_lock(&esw->state_lock); err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx, - MLX5_CAP_GENERAL); + MLX5_CAP_GENERAL_2); if (err) { NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps"); goto out; } hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); - max_eqs = MLX5_GET(cmd_hca_cap, hca_caps, max_num_eqs); + max_eqs = MLX5_GET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b); if (max_eqs < MLX5_ESW_MAX_CTRL_EQS) *max_io_eqs = 0; else @@ -4644,6 +4650,12 @@ mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs, return -EOPNOTSUPP; } + if (!MLX5_CAP_GEN_2(esw->dev, max_num_eqs_24b)) { + NL_SET_ERR_MSG_MOD(extack, + "Device doesn't support changing the max number of EQs"); + return -EOPNOTSUPP; + } + if (check_add_overflow(max_io_eqs, MLX5_ESW_MAX_CTRL_EQS, &max_eqs)) { NL_SET_ERR_MSG_MOD(extack, "Supplied value out of range"); return -EINVAL; @@ -4655,17 +4667,17 @@ mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs, mutex_lock(&esw->state_lock); err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx, - MLX5_CAP_GENERAL); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Chris Mi , Tariq Toukan Subject: [PATCH net V2 4/7] net/mlx5: E-switch, Create ingress ACL when needed Date: Thu, 27 Jun 2024 21:02:37 +0300 Message-ID: <20240627180240.1224975-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6731:EE_|PH0PR12MB8799:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e7438be-1a6a-4961-5fe5-08dc96d39aba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: 1AbVOMFPaQ7ZG8qCFTkpjbpqZAPuI//b8tlydgGQPXs1BWZXa1WQCdVqsiBGfqsM4YueirHWhbnsuc5okcu2v9Wvhs7Cq5uRoKRFYqXZ3GBeu1iLfLUJckbXaAIPCV/F4l4ZGgc1+anrGYETryb8WYqZmNjksNnH3qEpqptgPoJOT0sFhljJZNpTyvKLjSTuM7D+WMaenOZWYAMU9ZBChReLqCUwHloTHoi9cuYtg5XtTgriqq2wI0cwmC7ZBQHmj5GMTX6x2XR09vQc1X8J2VxQsEJl2fyrNvcc4HUET75/tVezSSRrGYpaJ/3gAxgWJLG2gzD4tghCkCUhzGbF1GlPgufHrX7Vqu3JOzHQGJNr6zrS1+3NwVsABEmaeMB397gyWT1PyU4ZPfUoaU5ni/h6cfVlAEkCRKFwgzmM6r+nt8mYKQ8Z+2nVJFOD+8DXDRACmFzm1EYAgr+2X9yP312yK0vGIJnedlj0CjYhv9r4MFaGr+7qOU/FVA7F1VpbnP20H5W+yTUSul4MkDOe+j3ltOwlzyDAtzus1yxEP26eXHGCJ5rOcxTfxjvmFTGroROFazWN8HnXhKrL7/tg9+35BKUBR/FgDqtHpdAwSDfs5E3A808PrgrrSrow0ILB4JKn3hRzaLnuF578fd3RvsQD8TP6tcn4i4C9GZ5wa1wWgk8lpNFhSgiyg3QOTMS4UxSK53gpCdGQe1jv9upjB+SErjIEYInbYbktICvAB3p4JrkjW4JKfFDMVZJJ0c5G2T+1P8OKUC2AmzApYT0G1Ss4ndm2NAslF46CzO33xqFVDfJA/Rt79MuZdlS2Qec6/kpdaQv2u6ieKq2FLGohTAnDT7/BBPdbqEqmbI09UsqaQGi+ZcXghGNSj5OcwLtUw88aG0uGBvolbCX5guSegbRybv6XTm4p/QIDEc3jmYGDGfIuhQ5vLn9dj6eLFcGokckm/Sy5uvVz9Wwi/m6WYWJ906fOLMc2N8hZcEpE5QJPGEq3J4WpSiHG+BqKll2evIYygCFLBoqaAqklq8zYPMqTrdlNyxfdzsiVfTI6LiwnmQGnCPHEAxXVf8yvZlCBdodqQAji7K7S8Tn0OybtdZ1QwrJM9QQYbr5QSfXHHCh7qQiPd/ZdNvg20fsJNu6Fe8WMJnjL1sUjW3hF0PIYkgYerVs3JcZWpnoX97OcabLm/EJTZAbPTUaYu9oMPmneZxCZN2qwPerN8Mf4gj6SmHWy1/51+zjp7V9IGZXbMmIwnRNL62Iyn8KSW7uVXpuG4CRvgBCd1bCEuzNjQKqDdKtWUZyMcuNTuuNy0H9i0Y4KeoOuJVLKEdbtk5d7TFem26hWFPnFvWd8f9Uaiuwd0YMcluFX0k6GatXg2j9PIspQMdvkM2/7xH+WWA/ZGDnGghKX+RvbNVYXC3cTimI2jJW/Wr3+OEpguW2rk5FoSLw= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:35.6220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e7438be-1a6a-4961-5fe5-08dc96d39aba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6731.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8799 X-Patchwork-Delegate: kuba@kernel.org From: Chris Mi Currently, ingress acl is used for three features. It is created only when vport metadata match and prio tag are enabled. But active-backup lag mode also uses it. It is independent of vport metadata match and prio tag. And vport metadata match can be disabled using the following devlink command: # devlink dev param set pci/0000:08:00.0 name esw_port_metadata \ value false cmode runtime If ingress acl is not created, will hit panic when creating drop rule for active-backup lag mode. If always create it, there will be about 5% performance degradation. Fix it by creating ingress acl when needed. If esw_port_metadata is true, ingress acl exists, then create drop rule using existing ingress acl. If esw_port_metadata is false, create ingress acl and then create drop rule. Fixes: 1749c4c51c16 ("net/mlx5: E-switch, add drop rule support to ingress ACL") Signed-off-by: Chris Mi Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/esw/acl/ingress_ofld.c | 37 +++++++++++++++---- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_ofld.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_ofld.c index 50d2ea323979..a436ce895e45 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_ofld.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/ingress_ofld.c @@ -6,6 +6,9 @@ #include "helper.h" #include "ofld.h" +static int +acl_ingress_ofld_setup(struct mlx5_eswitch *esw, struct mlx5_vport *vport); + static bool esw_acl_ingress_prio_tag_enabled(struct mlx5_eswitch *esw, const struct mlx5_vport *vport) @@ -123,18 +126,31 @@ static int esw_acl_ingress_src_port_drop_create(struct mlx5_eswitch *esw, { struct mlx5_flow_act flow_act = {}; struct mlx5_flow_handle *flow_rule; + bool created = false; int err = 0; + if (!vport->ingress.acl) { + err = acl_ingress_ofld_setup(esw, vport); + if (err) + return err; + created = true; + } + flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP; flow_act.fg = vport->ingress.offloads.drop_grp; flow_rule = mlx5_add_flow_rules(vport->ingress.acl, NULL, &flow_act, NULL, 0); if (IS_ERR(flow_rule)) { err = PTR_ERR(flow_rule); - goto out; + goto err_out; } vport->ingress.offloads.drop_rule = flow_rule; -out: + + return 0; +err_out: + /* Only destroy ingress acl created in this function. */ + if (created) + esw_acl_ingress_ofld_cleanup(esw, vport); return err; } @@ -299,16 +315,12 @@ static void esw_acl_ingress_ofld_groups_destroy(struct mlx5_vport *vport) } } -int esw_acl_ingress_ofld_setup(struct mlx5_eswitch *esw, - struct mlx5_vport *vport) +static int +acl_ingress_ofld_setup(struct mlx5_eswitch *esw, struct mlx5_vport *vport) { int num_ftes = 0; int err; - if (!mlx5_eswitch_vport_match_metadata_enabled(esw) && - !esw_acl_ingress_prio_tag_enabled(esw, vport)) - return 0; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jianbo Liu , Dragos Tatulea , Tariq Toukan Subject: [PATCH net V2 5/7] net/mlx5e: Add mqprio_rl cleanup and free in mlx5e_priv_cleanup() Date: Thu, 27 Jun 2024 21:02:38 +0300 Message-ID: <20240627180240.1224975-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|MW4PR12MB6921:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cbf0e28-aee6-4621-006e-08dc96d39a26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: XdIpamsl3bS5cdsdYK75pc+0PnnH4pGVi2HbmzPA/vYRp+RDABXRfqvcvbxsD2Y1rITHE1YdzFFZPn3/aDHvSVmxNuOg/FZExOILc62+PG+UVFhDC1o9fU2O5SPmSbGOHkCk09PH23ed7Q8n9iAW5J4BZT4ITHHjVekGTWZrQIc4Ebr15HxXCBDUAYhe91PqAOrtmU/KRaBJlTXWpqYkgGKoU7b65P4wgSvjVlLgIc5i1TdJyh1PKj5RfLzNDxjeAn8NJn0bBLTr+LhIJzs21owxO7ck98YUOO+8IPCsZqSzGAW2IRF4/y2zq3izV37TTdGuq83Q6q992dQwLdflqftJsXbZ/CEhZ6Iga7EB5hEfyPjDYv4UxDGOX6mST3Mbs8fQUFC/UZKfMUZNjx8EK7SbIJdRvAIIncdTKWLENixu/nFpqMCNmcRGP6NBFgXSBz6y3JBm00pD87bcmuI4MTO7iOJqXvuMSI91KK9PpRgTaTyInz6hRt6N6v0R71WnHLv0AdbHD0vtSHT/3clXuhMrdL+Tx3yD5ooe9MbvZJXWPpwvuj/8S7QClb4xSUrRKDbnAZL7GZpc4hXS1ambJPHRcR8Fd5lk4d1SBWYyx6tzO8IeE/Gzlz42uRcubYdpdlPbJEHk2DJYFyV3N29K7MjthHjxS7nuuzca52lAZAAOveDSUCI8xrtzEdE4aY/bvcVp9t7SXEVn3izZGtq1/5rbbpDW0Y+CsiRR5AJ/5faiNkB0CvSTM425WdrJAlAYPE8aPvGiEu8WnaAF54Sp4OOVz/Z932hyPgE6ROHxiXCQ4mC9gRh+uXo5fhKQuabbRJZBzoJsxEC43MEGzPfI6OAuwZnXsNDI+uTypvCTVez2+Em6E3ZnbrOvnBi1YxR9YJdQ0yTwrSEtqegX+8NFOWIXpoxOZidXMTSPHge8QuHL1BqGJWqLUtSwuvDD2rtGsxHSYeeT5fgPIBxugGCm8OkQgz0hWFxE44xwtuKXGvCxmqcDWQWzCR36xWAu4x0TPT7jsEs+YTxf9hcuR5etngEn2J058Y1EEWaSPsh4ofQTu4GeMcJ6ob7CKuqJX5xlvu6TG6G91EDA/kCtXKQmBXbgrKO4l9G8iXf2CS7ZERXqhCNDn1l0aPE5xU3COpQwdK4V+jgmKtXBhRZ6Z5TMONst+OSPW2ifItk0923IY6RSyE1pKwut662onrWbkKNzV/bFq5IjAltdBXUYuScYILgMBlmplKg/yuX7410573BEl23c3pVbHGSiezuofkF8Z6nOrG2Zu70RjNYykRpTfVnBkdk7so7ms+eO0wwJqqUzQQyfdwNPLutGfz7ttD/C1D7rOU+XhvEup8BsauBL3NnLr/SLW915w9ow3MxtRmNlNa1RrZqKKx6CAmB9wgvIFK8HK09+ET4WOq/fGVaJf8DtlgCB4GjEfzO4LbyPslTXf9BDGjbtAbEor4Uuh8f/ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:34.6340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cbf0e28-aee6-4621-006e-08dc96d39a26 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6921 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu In the cited commit, mqprio_rl cleanup and free are mistakenly removed in mlx5e_priv_cleanup(), and it causes the leakage of host memory and firmware SCHEDULING_ELEMENT objects while changing eswitch mode. So, add them back. Fixes: 0bb7228f7096 ("net/mlx5e: Fix mqprio_rl handling on devlink reload") Signed-off-by: Jianbo Liu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index a605eae56685..eedbcba22689 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5868,6 +5868,11 @@ void mlx5e_priv_cleanup(struct mlx5e_priv *priv) kfree(priv->htb_qos_sq_stats[i]); kvfree(priv->htb_qos_sq_stats); + if (priv->mqprio_rl) { + mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); + mlx5e_mqprio_rl_free(priv->mqprio_rl); + } + memset(priv, 0, sizeof(*priv)); } From patchwork Thu Jun 27 18:02:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13714969 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2089.outbound.protection.outlook.com [40.107.236.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32A2E17C7F for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net V2 6/7] net/mlx5e: Present succeeded IPsec SA bytes and packet Date: Thu, 27 Jun 2024 21:02:39 +0300 Message-ID: <20240627180240.1224975-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|SJ2PR12MB9114:EE_ X-MS-Office365-Filtering-Correlation-Id: 6bb151fc-eb90-4043-ad4a-08dc96d39e31 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: 4EnkhU2xdWqdX4dP5fCEu0Hh5p8sYcibioK0Bv3O/mfbw5dqAk1vhAFNzyc/oi8osiy+DM5+KAqhPsrwAdMqljzG0p718z35KMmrerhR+q4dFY8AP2yKI4D9Xat9NmtFKmYeoaaX6KBIi3YOYrYO/FvphFEyq5FwV+MBqYhVrlG4Nk8Yt4Jim7mMzE2scLrm2jLIFtwg1zVYyG5jpIdWbpn2DQLiQNaixf2OT4NcTFR3wx791Usqcux0qEaB/ntbuvPW6RE8iOhKZby/hBOZys56VNYfregDUGpyWWSWp1ls0htweBS8Bm7+vYhPT8Hsi1vlxqirMQQXj4JLU9s6ACj2Lra1PoT+mESfzxim9jXjjgklXqs7j4kt/nziAxBk5+pzoL8o5c65/iPbkBCnyGxEhESDWTQRwupUdGT1DvNUwpHr06HigVko2OKmjNM5kBKzJEQFlMbw49J6OBRnaa6rZCFrRTon8WcU71Q9SNJI4KfiHvUfDPkpeYfXQ+vBha18qYeDPj6sNl4g7zjl4dAsCQbnFIElEz4MPXXuhlKVUBmtNZ4yhsxMX10qukVbcYNBCKyG+zFGtd7qlZvnD/FXDXN6z6LBwST3Ju4qsglhi1nydu8BSxKYBbCG/kcDG/GGh6CF7C1/g+RwxdHMA+FSVVgOJ1nkxwox+p5RY3w41yTR4j2bSQjZoOKPqD2wL/mRackYBYSZbWpo9ezcj+PiazVL34DgHNMpCEwqiwhZ+tGlPBqdWB8abbEOstnM7VuzcJUa/qiARRRWJW3pVV/OuZxyBGUF+HH6mXLEs+9t493NCpE/R2xLwKcbQH7dJRcFSj5t3TTghsxnGq6cNvasJwa/FTIchnT+ppQtc1QfjCEyLbs6rUXNuejAcnz7dW+2Kz8Fq8dcUh1vTtAJeD48C7HqqOay6kkB0K+I3zqeFbez6F0BfmhY+iUk6SbsbMsHJ2CRncSU9b7njSRegKvuQzyF2Iad/YHykSBeclsSfweoDlEQYtxItB81i8KSZhB9R1j9+URwBKrLO9DHYZbxZV3PBAweFWZKjn57xgV5EijOZKiJm4fQBRHGE1ULzue2AGxYVfnf5zn3GpcMKNHJCIpfNwu53BocTUun7Qap+1VhVRmofYohR7MlkDoi6pUQGbd9UMPW+8JbIyhkRaLr5azoqc/Hqq0q8DYmvsR9nJpUxqkjHTct1M+ICaTLdRAw/9jUXx0zvo410EaA34iFI/1eiQ7fkmU67zyPfv6gPngHpUDLS2iODCqtNqpLBMScv+usiYAjFnux7mBKEKjCe3bPCxnjBmKC41Dgb/BYe3qGFgKbj53q7Ilpj6Xfv3MUlEMdygwQ8RgyvSEv2tm2iU8s2HVTqIIU8ELG/uVrcFmJqj2rQdN7qQBxpugd6zV3zAXdoPP2ojDmC0ai/I+Zega3Q37EpvkWfyz9Bsn8G46+oActfX+gbTiK+Dpr X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:41.5151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6bb151fc-eb90-4043-ad4a-08dc96d39e31 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9114 X-Patchwork-Delegate: kuba@kernel.org From: Leon Romanovsky IPsec SA statistics presents successfully decrypted and encrypted packet and bytes, and not total handled by this SA. So update the calculation logic to take into account failures. Fixes: 6fb7f9408779 ("net/mlx5e: Connect mlx5 IPsec statistics with XFRM core") Signed-off-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 36 ++++++++++++------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index c54fd01ea635..2a10428d820a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -989,6 +989,10 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) struct mlx5e_ipsec_sa_entry *sa_entry = to_ipsec_sa_entry(x); struct mlx5e_ipsec_rule *ipsec_rule = &sa_entry->ipsec_rule; struct net *net = dev_net(x->xso.dev); + u64 trailer_packets = 0, trailer_bytes = 0; + u64 replay_packets = 0, replay_bytes = 0; + u64 auth_packets = 0, auth_bytes = 0; + u64 success_packets, success_bytes; u64 packets, bytes, lastuse; lockdep_assert(lockdep_is_held(&x->lock) || @@ -999,26 +1003,32 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) return; if (sa_entry->attrs.dir == XFRM_DEV_OFFLOAD_IN) { - mlx5_fc_query_cached(ipsec_rule->auth.fc, &bytes, &packets, &lastuse); - x->stats.integrity_failed += packets; - XFRM_ADD_STATS(net, LINUX_MIB_XFRMINSTATEPROTOERROR, packets); - - mlx5_fc_query_cached(ipsec_rule->trailer.fc, &bytes, &packets, &lastuse); - XFRM_ADD_STATS(net, LINUX_MIB_XFRMINHDRERROR, packets); + mlx5_fc_query_cached(ipsec_rule->auth.fc, &auth_bytes, + &auth_packets, &lastuse); + x->stats.integrity_failed += auth_packets; + XFRM_ADD_STATS(net, LINUX_MIB_XFRMINSTATEPROTOERROR, auth_packets); + + mlx5_fc_query_cached(ipsec_rule->trailer.fc, &trailer_bytes, + &trailer_packets, &lastuse); + XFRM_ADD_STATS(net, LINUX_MIB_XFRMINHDRERROR, trailer_packets); } if (x->xso.type != XFRM_DEV_OFFLOAD_PACKET) return; - mlx5_fc_query_cached(ipsec_rule->fc, &bytes, &packets, &lastuse); - x->curlft.packets += packets; - x->curlft.bytes += bytes; - if (sa_entry->attrs.dir == XFRM_DEV_OFFLOAD_IN) { - mlx5_fc_query_cached(ipsec_rule->replay.fc, &bytes, &packets, &lastuse); - x->stats.replay += packets; - XFRM_ADD_STATS(net, LINUX_MIB_XFRMINSTATESEQERROR, packets); + mlx5_fc_query_cached(ipsec_rule->replay.fc, &replay_bytes, + &replay_packets, &lastuse); + x->stats.replay += replay_packets; + XFRM_ADD_STATS(net, LINUX_MIB_XFRMINSTATESEQERROR, replay_packets); } + + mlx5_fc_query_cached(ipsec_rule->fc, &bytes, &packets, &lastuse); + success_packets = packets - auth_packets - trailer_packets - replay_packets; + x->curlft.packets += success_packets; + + success_bytes = bytes - auth_bytes - trailer_bytes - replay_bytes; + x->curlft.bytes += success_bytes; } static int mlx5e_xfrm_validate_policy(struct mlx5_core_dev *mdev, From patchwork Thu Jun 27 18:02:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13714968 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2086.outbound.protection.outlook.com [40.107.237.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D1D419AD85 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net V2 7/7] net/mlx5e: Approximate IPsec per-SA payload data bytes count Date: Thu, 27 Jun 2024 21:02:40 +0300 Message-ID: <20240627180240.1224975-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|PH7PR12MB8038:EE_ X-MS-Office365-Filtering-Correlation-Id: 38d1558f-9b4d-40fb-7fe9-08dc96d39ccd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: 8smZ7IqNLCm8S513y8lGnfMA7QKPFgimMljvlFKh0gakyKusOF3d+LhFjTLBUIwXKS7GOXgN9IPczWiBZqMU4qC7PEikWvFQQoCPhs7X78/tU0vfBNzGInVHK9Uybgqpwh8OrAESuOlXfq743a5HttQIkpkCIoV2Y0O6wnblAcfG/iOnQVatsppaCWCP4UF7lBisx8US8b0dDLWyZrLH4WabRvUJGMSbM73956PUK/CVobzVTaMLqp1IQEMyd5OLjYpDb2A39ONZnQDLWh4ZgBD2MrMqmvIHS1m/ee2hhMeu0d7LtbY32VdJwpxxF3kPd8DDNX1XlGcH3e3LCf5cjFR2R/iCa70agZvAK5a1ibTkRlqPby8n2KU/6GTzIaCLHyZETvbr1EIb6OVlEseoU0uImyhdZoJi9mX+VywDpM4R3b6tO+ghZxbCSzJ+QhUKNXD0n6kssSQf5fqZB8iq7edhLYa9CNk1okZMSp1zpMdM9hUZLS5tZH4sryXeaVQHDBrTXcwGwm+AmJY+iLuFHMb3oG86VrB11EX+Fuznqm1XUQztDPZ6W0DNa8msGtW9cNiz3p7W8R63EYnm/E5c22akWWp6lA5SVsRQ4tmHVmbB4Zp0fcB+yl8FWZobuZzQXPX0MBcCgV5d71n9JtG/8U6qYGaa6a6JzBxvWv0he2JVDnJXygcooh/1dag8e6MWKOZJ2n8FSSoEXU4whJOroTBv6tweRnEhLQqVJPmGhz9ScKmBnMrnVNhOex+75NGO52TJVn6zwytTyUkLN/VvQ79+Q+HBdKdEA+6Y0Vc9bdQI+xh/bPqCp5NOizmoxSd9q4RNtaJoYwIWHBpGePUvC00X2pNBgIokNXeCunh+xjcHp7W7FMn1rOi79iczY56+r/nTymQ7BxU2+9oj1pzw+tiCtm+7HZ9oTA9jIo1Yb/FPPm9SxlGJAwvKqhJKM3cbBlDvYLL+I9UdD6Ih8/F/+jw3PstIQ8eGS4IZixJpfAK9s65cSJU6snEwifafuShqR3W8A2STnIRqU8eD67obDDrGQ0BkUAIPyJzCX3phxBz0yw1m+9NXL6GoFE5VO6U0Iy8mOFWbwDPpvkx5MnBS38x7oc+75JwsR9za/BWD+sry28HYnfk+kYcWdlLFa06d/S4a9hKbgi2KttlYvlEFDCcQLp7aQfIGAFGjJXBQkcSh3+xtpctb63I8/SpT5szqNFcO1S0X06JGRHb0BdJ9MvjplBSkze0TDPxLL2yyD4hhZCBcZfAgL/RAH7L2VXsDzBffANcq5GTqbRCictbYz8OvUJVnpkENZS4aQU3JuUhzqMuMfoBspKa5E+MVQeqIu8xWQ+ffyGNK5TF+yqanfcYUm/X+mZA0A7+AXuNnppifEgodUBqwkOJLEntBo2AO8TCmtkUxXsJv4nJUNyek7J8nSYkFcz8dNMp+0s5qarXiGMFuXLH/z/JL0jnJiDQk X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:39.0871 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38d1558f-9b4d-40fb-7fe9-08dc96d39ccd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8038 X-Patchwork-Delegate: kuba@kernel.org From: Leon Romanovsky ConnectX devices lack ability to count payload data byte size which is needed for SA to return to libreswan for rekeying. As a solution let's approximate that by decreasing headers size from total size counted by flow steering. The calculation doesn't take into account any other headers which can be in the packet (e.g. IP extensions). Fixes: 5a6cddb89b51 ("net/mlx5e: Update IPsec per SA packets/bytes count") Signed-off-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 2a10428d820a..3d274599015b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -994,6 +994,7 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) u64 auth_packets = 0, auth_bytes = 0; u64 success_packets, success_bytes; u64 packets, bytes, lastuse; + size_t headers; lockdep_assert(lockdep_is_held(&x->lock) || lockdep_is_held(&dev_net(x->xso.real_dev)->xfrm.xfrm_cfg_mutex) || @@ -1026,9 +1027,20 @@ static void mlx5e_xfrm_update_stats(struct xfrm_state *x) mlx5_fc_query_cached(ipsec_rule->fc, &bytes, &packets, &lastuse); success_packets = packets - auth_packets - trailer_packets - replay_packets; x->curlft.packets += success_packets; + /* NIC counts all bytes passed through flow steering and doesn't have + * an ability to count payload data size which is needed for SA. + * + * To overcome HW limitestion, let's approximate the payload size + * by removing always available headers. + */ + headers = sizeof(struct ethhdr); + if (sa_entry->attrs.family == AF_INET) + headers += sizeof(struct iphdr); + else + headers += sizeof(struct ipv6hdr); success_bytes = bytes - auth_bytes - trailer_bytes - replay_bytes; - x->curlft.bytes += success_bytes; + x->curlft.bytes += success_bytes - headers * success_packets; } static int mlx5e_xfrm_validate_policy(struct mlx5_core_dev *mdev,