From patchwork Thu Jun 27 20:44:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715015 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 742C61A2562; Thu, 27 Jun 2024 20:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521049; cv=none; b=RR/BQpfSkH9hjjzU6yZqVrwPD6YyAsVsRF7Xhr0WR0wgx6YKv2mSturM2R0ZTHpvkiMkTpxhi9yYqcAXMe17oUfFJVc9BlOE2eotpHPkGHrkCoSh7rSk4TB408SPhY8C7r/FSjBfNHcAS/Bu8kchg0FjyIkpAEewvQryqgZTtkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521049; c=relaxed/simple; bh=GSnYrv2tIngbGP7UO6mPjG1VZqxU7RfQH2ltGkwIMPI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RhPShrzNG4hR3dDJUVJiZl5MLBYL6CQKO6OR8HNTh1lKve35S3Vun7J8kRid4SKxOb7Upn0su1g8p9C0JOYX1LeF3mJfDA4qkISCa0+Jvjy6KFRYaUDp7Eu2xxV1Nz9Tbp+fjShPhkwiyd/oRcAOBgGvnSvZzpz7uuZWljJ6ET0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YGMxtzd1; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YGMxtzd1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521047; x=1751057047; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=GSnYrv2tIngbGP7UO6mPjG1VZqxU7RfQH2ltGkwIMPI=; b=YGMxtzd1evtldTeTHbZmUua3j3Xp0iM2GuRGSRnuM53v5lkeeBgae/Aw FYJ3kSQw8oOKzbooLtjB4SZo2jp8ynp1yFc4EnFLn1JtFrC/aMk7NEOGh hhcYIFQ+MsDAt0f59eituyZoY6AUaloijMMH08fe3HuoL7KIMXwTAxqAY IfKKDocbAB47tVf5GhBF3fWPZF7K5/0sC5jBvfJiIGn+hJ/+cK9nHTzXS KecWMMxXGF+OKc/UvAZLajyD+q7BXSlvZvDsPcIFiA1JwDMGVWZliI2PY qKNGOuW7WZzMJ5u1A2rkwxxS7QbqK/pJkbQC5Qw7GHZgwh0n2sFd3emMR g==; X-CSE-ConnectionGUID: tJBV7g8hT2OMXy9q6/ptaQ== X-CSE-MsgGUID: g2sdqLsZSNGKuuEGnUsCqQ== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="27816191" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="27816191" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:07 -0700 X-CSE-ConnectionGUID: thV0zFdERkyaHSqWflpazw== X-CSE-MsgGUID: 0hUuORO4THG75FcnuN/UhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="44913242" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:07 -0700 Date: Thu, 27 Jun 2024 13:44:06 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 1/9] x86/cpu/topology: Add CPU type to struct cpuinfo_topology Message-ID: <20240627-add-cpu-type-v2-1-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Sometimes it is required to identify the type of a core for taking specific actions e.g. intel_pstate driver uses the core type to determine CPU scaling. Also, some CPU vulnerabilities only affect a specific CPU type e.g. RFDS only affects Intel Atom. For hybrid systems that have variants P+E, P-only(Core) and E-only(Atom), it gets challenging to identify which variant is vulnerable to a specific vulnerability, as these variants share the same family, model and stepping. Such processors do have CPUID fields that uniquely identify them. Like, P+E, P-only and E-only enumerates CPUID.1A.CORE_TYPE, while P+E additionally enumerates CPUID.7.HYBRID. Linux does not currently use this field. Add a new field hw_cpu_type to struct cpuinfo_topology which can be used to match a CPU based on its type. The hw_cpu_type is populated in the below debugfs file: # cat /sys/kernel/debug/x86/topo/cpus/# Signed-off-by: Pawan Gupta --- arch/x86/include/asm/processor.h | 3 +++ arch/x86/include/asm/topology.h | 9 +++++++++ arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 9 +++++++++ 4 files changed, 22 insertions(+) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index cb4f6c513c48..d8d715fcc25c 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -105,6 +105,9 @@ struct cpuinfo_topology { // Cache level topology IDs u32 llc_id; u32 l2c_id; + + // Hardware defined CPU-type + u8 hw_cpu_type; }; struct cpuinfo_x86 { diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h index abe3a8f22cbd..717fdb928dc3 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -33,6 +33,14 @@ #include #include +#define X86_CPU_TYPE_INTEL_SHIFT 24 + +enum x86_hw_topo_cpu_type { + X86_HW_CPU_TYPE_UNKNOWN = 0, + X86_HW_CPU_TYPE_INTEL_ATOM = 0x20, + X86_HW_CPU_TYPE_INTEL_CORE = 0x40, +}; + #ifdef CONFIG_NUMA #include @@ -139,6 +147,7 @@ extern const struct cpumask *cpu_clustergroup_mask(int cpu); #define topology_logical_die_id(cpu) (cpu_data(cpu).topo.logical_die_id) #define topology_die_id(cpu) (cpu_data(cpu).topo.die_id) #define topology_core_id(cpu) (cpu_data(cpu).topo.core_id) +#define topology_hw_cpu_type(cpu) (cpu_data(cpu).topo.hw_cpu_type) #define topology_ppin(cpu) (cpu_data(cpu).ppin) #define topology_amd_node_id(cpu) (cpu_data(cpu).topo.amd_node_id) diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 3baf3e435834..8082e03a5976 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -22,6 +22,7 @@ static int cpu_debug_show(struct seq_file *m, void *p) seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); seq_printf(m, "core_id: %u\n", c->topo.core_id); + seq_printf(m, "hw_cpu_type: %x\n", c->topo.hw_cpu_type); seq_printf(m, "logical_pkg_id: %u\n", c->topo.logical_pkg_id); seq_printf(m, "logical_die_id: %u\n", c->topo.logical_die_id); seq_printf(m, "llc_id: %u\n", c->topo.llc_id); diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c index 9a6069e7133c..8b47bd6b0623 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -140,6 +140,14 @@ static void parse_topology(struct topo_scan *tscan, bool early) } } +static void topo_set_hw_cpu_type(struct cpuinfo_x86 *c) +{ + c->topo.hw_cpu_type = X86_HW_CPU_TYPE_UNKNOWN; + + if (c->x86_vendor == X86_VENDOR_INTEL && c->cpuid_level >= 0x1a) + c->topo.hw_cpu_type = cpuid_eax(0x1a) >> X86_CPU_TYPE_INTEL_SHIFT; +} + static void topo_set_ids(struct topo_scan *tscan, bool early) { struct cpuinfo_x86 *c = tscan->c; @@ -190,6 +198,7 @@ void cpu_parse_topology(struct cpuinfo_x86 *c) } topo_set_ids(&tscan, false); + topo_set_hw_cpu_type(c); } void __init cpu_init_topology(struct cpuinfo_x86 *c) From patchwork Thu Jun 27 20:44:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715016 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60E1419F46D; Thu, 27 Jun 2024 20:44:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521055; cv=none; b=ZxNqvcIgtnNOgOYdklSbez67SgR02+ZQOla1XMEwA8AQ+Fqo3WPA904NG592wsiQ74JyqWBeQKIKdbEfRG8fo8W5yM6t8NOQ5QVlYv6R+rYPj2u4gp9cpL0TI124eLt+ipIN9OvifRucLFc2kocErOnEasPmuNVAyNUZf+HlXvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521055; c=relaxed/simple; bh=WWEGL8llrzPO9U6cEMHLUdGN09d4ZNQFv7tRiYccFcY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RRo6Xlv1uj/JpGC+diilZ4dGAl1pJOmEpyLbPzdHRf9XcM2bcq79TJ7ynhjB4ksFlxpgstFfhBPJoUgbsjpv1WvDCl0dQZbt/E2qW6ZL4KpW/Nlxyu4G/CgVnvBVUUl5VYq8eOBFtGf4UpNzgYjoQhCRaGphnsj8zfwF89BORSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Dnhd4s0+; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Dnhd4s0+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521054; x=1751057054; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=WWEGL8llrzPO9U6cEMHLUdGN09d4ZNQFv7tRiYccFcY=; b=Dnhd4s0+TtI9QnbdzgfxE/q06E9NRryTSDTY7KG6NJSHN+S+KZ8r+VE0 mNTuFwmNUdFcDLAqnHxFXq7+P77kEoP31atZnATKiulZr44AUK6ob0xad BLaVhzrtlY9NSUiOyde6HnkOFuOPaaNw6H6neuoFJCrmwNd55MuBqxJbN 0cw2N1KH0ke6C+xMyKT0gdJVb5st3ZIYbTKx/ACIZWjN/tPWqBgsPii/8 jlxiiTEi3pb/gQmVaVKIE+oIU3W5fhsBdIjR7Gf4fRW8tTrKx2Eba4CUY nRh9LH5Ek5QfS/PW2WILjBEEWycJFZoYYyiiQ8UObqZUq0RA5bO0Bnr0e Q==; X-CSE-ConnectionGUID: ECmBtKa3S2KnbH9TO4WUlw== X-CSE-MsgGUID: QjyGIfCrSvC0tzgezuSKpw== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="34132505" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="34132505" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:13 -0700 X-CSE-ConnectionGUID: Mg/mQqb7ScmVeA4Bu0gsBQ== X-CSE-MsgGUID: zgddO2GCQyS+WVb1tTFg1A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="75708598" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:13 -0700 Date: Thu, 27 Jun 2024 13:44:12 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 2/9] cpufreq: intel_pstate: Use topology_cpu_type() Message-ID: <20240627-add-cpu-type-v2-2-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Intel pstate driver uses hybrid_get_type() to get the cpu-type of a given CPU. It uses smp_call_function_single() which is sub-optimal. Avoid it by using topology_hw_cpu_type(cpu) that returns the cached cpu-type. Suggested-by: Dave Hansen Signed-off-by: Pawan Gupta Acked-by: Srinivas Pandruvada Acked-by: Rafael J. Wysocki --- drivers/cpufreq/intel_pstate.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 15de5e3d96fd..0a1e832c7536 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -1956,24 +1956,16 @@ static int knl_get_turbo_pstate(int cpu) return ret; } -static void hybrid_get_type(void *data) -{ - u8 *cpu_type = data; - - *cpu_type = get_this_hybrid_cpu_type(); -} - static int hwp_get_cpu_scaling(int cpu) { - u8 cpu_type = 0; + u8 cpu_type = topology_hw_cpu_type(cpu); - smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); /* P-cores have a smaller perf level-to-freqency scaling factor. */ - if (cpu_type == 0x40) + if (cpu_type == X86_HW_CPU_TYPE_INTEL_CORE) return hybrid_scaling_factor; /* Use default core scaling for E-cores */ - if (cpu_type == 0x20) + if (cpu_type == X86_HW_CPU_TYPE_INTEL_ATOM) return core_get_scaling(); /* From patchwork Thu Jun 27 20:44:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715017 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C5E319F46C; Thu, 27 Jun 2024 20:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521061; cv=none; b=RdiMC0A38cMYcFiXW6i+I5BuMsyrUdgCvGpuAR/5SyMzf7zalj2CkYqSJZHtRT6mMYuFcqiUPzPH2rSE3lEIzRTxE/d6jLa4ndQQy3l1JlWxoU6Uuw9G/ChgLko0rwx7OtiH0l/CmovVdWtA5DNI8umFrJLcH7Vmt6WW2uy0UUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521061; c=relaxed/simple; bh=DVzDv4uACxxSDrFRLriFQUI7g0cXPdhDN1i3ovSARok=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=JtLEq2sZVAznvAvF73sPSMA86xsc7k2pVZ6+q5xldLy7dDn9QZbjmoe0cP2+gzAxLQe+EmNZiuavRj/Zz12TClM+fsPVR2BfvSW0Fcpf6kg7zsiZtGR9XWQ8vWoWno2Df5E8SLXJN8KqrPYfsQdIaFiLVxhdiaGq0vUzuBsIFKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CHVIyyVa; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CHVIyyVa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521060; x=1751057060; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=DVzDv4uACxxSDrFRLriFQUI7g0cXPdhDN1i3ovSARok=; b=CHVIyyVagqPt5zVoPOeT9a09XMjryzsSinXSSB/a0wngZH9/BVPn8gK4 RrtJokgFzKG3+re6gh2V/Bvm5XWwcKJPqJIXeKTE4/PJkF+kSCyozkSdi jiXkWHuGhSo7c5YzshKIw9Id0kp6T04YDPVMDwS8fnqk4oZzec1xqELaa w3rrjZOr/RaVMxJWnyZ24uiRrPz0kThTzQReCgvKBkZ2l3bPINsYtQL1f dUvULImX8zjqJpaNdOIuP8jxv/WsfIozBY9Pj9Fp6Dvymui2N8p9b/Em6 uJkz3dqN66E/Faxqxna10Os2f+T3zCa+qCzegkwjpPDFEKJqIJOF1B2b9 A==; X-CSE-ConnectionGUID: FBo8+E47RDW/Y3F6IooyFQ== X-CSE-MsgGUID: oQBx7lM/T1SrPnakPv0Jgg== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="34132520" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="34132520" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:20 -0700 X-CSE-ConnectionGUID: w5mtiqysTy2FweArSpdLMg== X-CSE-MsgGUID: tg+JUzvBTnOX6U1LGBxvSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="75708643" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:19 -0700 Date: Thu, 27 Jun 2024 13:44:18 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 3/9] perf/x86/intel: Use topology_hw_cpu_type() Message-ID: <20240627-add-cpu-type-v2-3-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> get_this_hybrid_cpu_type() misses a case when cpu-type is populated regardless of X86_FEATURE_HYBRID_CPU. This is particularly true for hybrid variants that have P or E cores fused off. Instead use topology_hw_cpu_type() as it does not rely on hybrid feature to enumerate cpu-type. This can also help avoid the model-specific fixup get_hybrid_cpu_type(). Suggested-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/events/intel/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 38c1b1f1deaa..0da1fd14b0ea 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4753,7 +4753,7 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) { - u8 cpu_type = get_this_hybrid_cpu_type(); + u8 cpu_type = topology_hw_cpu_type(smp_processor_id()); int i; /* From patchwork Thu Jun 27 20:44:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715018 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F2C1A01CE; Thu, 27 Jun 2024 20:44:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521068; cv=none; b=b39De0OlF3uqJ7VNwCgLNhN1zNF/yiMA0mgMGnwF8gidgi+PuJJ062dma3dpXIK3Erp6KsW27u5oQX+zw/hghjQQ8PnuTYT5Y5fUac2Wnv1paa55HxVSe5TgWUGtVFW34Pde4K+ENpEO12QIQzkALI1i1fJpeR+SBT0TDxqPuls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521068; c=relaxed/simple; bh=L2IcI1EjQZtbklruJIn6Yv5Q4rHmaf70lTCCFIPHBrc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ZyeZ6tUeJGL+6ceA9RhEpdUiGc7PzH1RY3Px5zsrzlWaG0fgUNzcnU0lbIBP9+sNA/6T1/Z+nKloZf89hCBrZ2W+lsLEirfmUA+aYF4RIXu6QtQ3NXR3yoeom2gAyg3LEJmRewj3HhAJk6QyQJilQRfG0UIUSA0KmGV46BuJXDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I+PqMDbz; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I+PqMDbz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521067; x=1751057067; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=L2IcI1EjQZtbklruJIn6Yv5Q4rHmaf70lTCCFIPHBrc=; b=I+PqMDbzEawNTZtVTpbjdX3ZD2rmOhY+l7Oow4M4EU6dFfQsf1f9v0Ck yfiPgzfs6mso74YNzMU+RHlDvhGCafR4qXxyxSRPt4gvYRFxGR3YTEyQC b+AX42qmIKUFqeVD1Wj7Ztg2vlASp3IwrMLzCJrV7eQmuc/ajfiZB7cqM TPgMGCT8QMqAAtKLMeLC5DV4HyNigge2nrciAd8vKnybnxTTOMBUAK1p6 zUoPJVSmn0mzkBdqi8Im049FPAOPMJWHI1B4URIHMBDoNeRlW6c95esoz SZZ8BFHsFPgk7TH5zhgfymk/+XrsyIKTiC9WGLn+QmDmVhTke5oxXv7IB A==; X-CSE-ConnectionGUID: JdQOqN8tTgGAazTcBX7J/g== X-CSE-MsgGUID: UvCGxU1XSZaS8amOi1Cp1Q== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="27816240" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="27816240" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:25 -0700 X-CSE-ConnectionGUID: F/n3hlJAQISAj+eHodAlgQ== X-CSE-MsgGUID: LhH9NVjVQSu21ZtcFuHqRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="44913369" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:26 -0700 Date: Thu, 27 Jun 2024 13:44:24 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 4/9] x86/cpu: Remove get_this_hybrid_cpu_type() Message-ID: <20240627-add-cpu-type-v2-4-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> get_this_hybrid_cpu_type() is replaced by topology_hw_cpu_type(). There are no more callers, remove it. Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu.h | 6 ------ arch/x86/kernel/cpu/intel.c | 16 ---------------- 2 files changed, 22 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index aa30fd8cad7f..20e491c22b98 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -31,7 +31,6 @@ extern void __init sld_setup(struct cpuinfo_x86 *c); extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); extern bool handle_guest_split_lock(unsigned long ip); extern void handle_bus_lock(struct pt_regs *regs); -u8 get_this_hybrid_cpu_type(void); #else static inline void __init sld_setup(struct cpuinfo_x86 *c) {} static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code) @@ -45,11 +44,6 @@ static inline bool handle_guest_split_lock(unsigned long ip) } static inline void handle_bus_lock(struct pt_regs *regs) {} - -static inline u8 get_this_hybrid_cpu_type(void) -{ - return 0; -} #endif #ifdef CONFIG_IA32_FEAT_CTL void init_ia32_feat_ctl(struct cpuinfo_x86 *c); diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index fdf3489d92a4..ac6c68a39051 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1335,19 +1335,3 @@ void __init sld_setup(struct cpuinfo_x86 *c) sld_state_setup(); sld_state_show(); } - -#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 - -/** - * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU - * - * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in - * a hybrid processor. If the processor is not hybrid, returns 0. - */ -u8 get_this_hybrid_cpu_type(void) -{ - if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return 0; - - return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; -} From patchwork Thu Jun 27 20:44:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715019 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A337B19EED2; Thu, 27 Jun 2024 20:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521074; cv=none; b=VyWxy122Q/eOiZrvbcrMafKeuD/YfXRllN/rqzttUutmTqRxjPlnK6pUhztReY5DaOdcdHRGv/9vjzPXKjdHBorHE/sHNf9+4LWeOgK/4D33WuDwdz4XDKB19Gf+yExBJAgOM8D3rBFsAvbtqB2XlwpOquFmp2KCP/imCStS6ZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521074; c=relaxed/simple; bh=fdujHrXY5TjguA4JCpRyxjYQMm4wQQhKrrWjnggGMh0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FVns7233yrlGSABWiaF+wWrrv9idrqWxWxShxfdjYC8B2gDVJMBWmAVuErVZNCHtDeLQZ0jT6BsAdjTHVf601VwWTmhnnHKSe9sJf4FhLt1xe/0ocqnFZKwUz/1EJk9InpeF+cOxPlCff+KfdtZfoaQ3jhvtlz46ZyuMCnkOzms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PcPk1Pt9; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PcPk1Pt9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521073; x=1751057073; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=fdujHrXY5TjguA4JCpRyxjYQMm4wQQhKrrWjnggGMh0=; b=PcPk1Pt9rB/IXySZeOZjmcTN1f1ratnh+dAzwpx4NNmO7X/vO+5cxZ55 glFYMgxiZNLONm6X3A+VqqgrKT5mxQpdYP3w3vcsGjNE/p9E1LKD00LNh AmJyeDtJFs1nq4uO3ihcUiv7mzW+qgIf2QQiBM7uZV1OKu4iI6ZTe8wZz D0/WZKX+sO2mJ3oLiq16rS3PoR7x4wxJi/VnOwyVpfTnkftPcqFQdR+dF VeFaJRSdihWgj8rJyQUGuStyYBvR4rF6AbOhMwOkaHfnuaRvZU0h4s8VW oKPRi8pTzKkkIotCY06r/EekfdJInlsGelvr7E89nF3UBBJB33X4fFLyw A==; X-CSE-ConnectionGUID: Q7sKH1b6QvipYQW/iJevkg== X-CSE-MsgGUID: 9ymZQcwqRMGIFc+6TfrVWQ== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16563579" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16563579" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:32 -0700 X-CSE-ConnectionGUID: pMrTV7/fRiitzDKJw6iNwA== X-CSE-MsgGUID: +e7jarY+Th6Wntg/fZc3BQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="67703766" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:31 -0700 Date: Thu, 27 Jun 2024 13:44:30 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 5/9] x86/cpu: Name CPU matching macro more generically (and shorten) Message-ID: <20240627-add-cpu-type-v2-5-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> To add cpu-type to the existing CPU matching infrastructure, the base macro X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE need to append _CPU_TYPE. This makes an already long name longer, and somewhat incomprehensible. To avoid this, rename the base macro to X86_MATCH_CPU. The macro name doesn't need to explicitly tell everything that it matches. The arguments to the macro already hints what it matches. For consistency, use this base macro to define X86_MATCH_VFM and friends. Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 104 +++++++++++------------------------ 1 file changed, 31 insertions(+), 73 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index b6325ee30871..6c8f4cf03cae 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -58,7 +58,7 @@ #define X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** - * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching + * X86_MATCH_CPU - Base macro for CPU matching * @_vendor: The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY * The name is expanded to X86_VENDOR_@_vendor * @_family: The family number or X86_FAMILY_ANY @@ -75,19 +75,7 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _model, \ - _steppings, _feature, _data) { \ - .vendor = X86_VENDOR_##_vendor, \ - .family = _family, \ - .model = _model, \ - .steppings = _steppings, \ - .feature = _feature, \ - .flags = X86_CPU_ID_FLAG_ENTRY_VALID, \ - .driver_data = (unsigned long) _data \ -} - -#define X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _model, \ - _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _data) { \ .vendor = _vendor, \ .family = _family, \ .model = _model, \ @@ -107,13 +95,10 @@ * @_data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * The steppings arguments of X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE() is - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(vendor, family, model, \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + feature, data) /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CPU feature @@ -124,13 +109,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, \ - X86_MODEL_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -140,12 +122,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ - X86_MATCH_VENDOR_FAM_FEATURE(vendor, X86_FAMILY_ANY, feature, data) +#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -153,12 +133,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_FEATURE(feature, data) \ - X86_MATCH_VENDOR_FEATURE(ANY, feature, data) +#define X86_MATCH_FEATURE(feature, data) \ + X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -169,13 +147,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, \ - X86_FEATURE_ANY, data) +#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + X86_FEATURE_ANY, data) /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -185,12 +160,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments to X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set of wildcards. */ -#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ - X86_MATCH_VENDOR_FAM_MODEL(vendor, family, X86_MODEL_ANY, data) +#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) /** * X86_MATCH_INTEL_FAM6_MODEL - Match vendor INTEL, family 6 and model @@ -209,8 +182,8 @@ X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, INTEL_FAM6_##model, data) #define X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(model, steppings, data) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, INTEL_FAM6_##model, \ - steppings, X86_FEATURE_ANY, data) + X86_MATCH_CPU(X86_VENDOR_INTEL, 6, INTEL_FAM6_##model, \ + steppings, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -218,15 +191,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Stepping and feature are set to wildcards */ -#define X86_MATCH_VFM(vfm, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM(vfm, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping @@ -235,15 +203,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * feature is set to wildcard */ -#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + steppings, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -252,15 +215,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Steppings is set to wildcard */ -#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, feature, data) /* * Match specific microcode revisions. From patchwork Thu Jun 27 20:44:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715020 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26BFD1A38F9; Thu, 27 Jun 2024 20:44:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521079; cv=none; b=PU22tReIw9X2yUrHtkt75OslIkDKF9bM2ZrPxPsDp6WCe8V3wKsG7Lbn7hPuymFp8fRbRwDm6Gc7PBhR1jHQW97BGJL3hTLeDXB8lVUweuMj//WtJWmpYijgFpoe+nyGsRWYJczc1ZO0rgvtX6Bn+jGV/CzQsRv9//1GwmuD+0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521079; c=relaxed/simple; bh=czVhlTW+B8D0/yDhk+UoDmaIZ12/fDo49V3e2kVcrbI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Q4Rf6Ab8c9fNqA5dI96h3u5vv/e+My7jnhsJ3GwDbu99NRUNa73pwCTUBisthLy1B7+82bkUW4s5JWA5fN1PTMwTQsqSgBu8FSVJsMHDED6pHI1AdWIgRRFCjs664HYqXMQ13ydYoIHHnuJ2/Ux50R1NneVMgKYJBtp210aHceo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ksY4Wkfy; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ksY4Wkfy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521078; x=1751057078; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=czVhlTW+B8D0/yDhk+UoDmaIZ12/fDo49V3e2kVcrbI=; b=ksY4WkfyYgCBtD2oPKCgJX9UvIg6hIqIca5EhffY0WVlRVs8hlY+AX5j xdjXfoCJzjwcKH8AJSkCOHsYDjNH1nmg0MNz6LaHNX5RMsw5g8eCuEHDv HJbC7y8qcnI4FZ/Il349hwH8b8H7sCmcqAk5s7lzCPXcUyBU+NOqrp8nm /uuePurTitg5O5OtnYxMNq7MJPH2R9xqtqpPC0pSItoNvKhujW0Aq9paU SGhcvK8PNzAYBAACjNbhdZl+EYx0PF8sn6O2wxP+Lyd5GY0EKGH5HyJB/ 8CbynLM1maFdFbSfr8DfFMksFKqPCXsf3qvsNEwXQOzIf+x8eyALn31tx w==; X-CSE-ConnectionGUID: jDeut94jRaivWGI7YGMBow== X-CSE-MsgGUID: NWSCknKuRX6OoC13RL1CnA== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16563597" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16563597" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:38 -0700 X-CSE-ConnectionGUID: oR6k/JzvSi+IqihXDBAk/g== X-CSE-MsgGUID: orlN6MJoRFCGnNoKoIOhhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="67703788" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:37 -0700 Date: Thu, 27 Jun 2024 13:44:36 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 6/9] x86/cpu: Add cpu_type to struct x86_cpu_id Message-ID: <20240627-add-cpu-type-v2-6-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> In addition to matching vendor/family/model/feature, for hybrid variants it is required to also match cpu-type also. For example some CPU vulnerabilities only affect a specific cpu-type. RFDS only affects Intel Atom parts. To be able to also match CPUs based on type add a new field cpu_type to struct x86_cpu_id which is used by the CPU-matching tables. Introduce X86_CPU_TYPE_ANY for the cases that don't care about the cpu-type. Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 35 ++++++++++++++++++++++++----------- include/linux/mod_devicetable.h | 2 ++ 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index 6c8f4cf03cae..08c2efa6dfdf 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -75,13 +75,14 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _cpu_type, _data) { \ .vendor = _vendor, \ .family = _family, \ .model = _model, \ .steppings = _steppings, \ .feature = _feature, \ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, \ + .cpu_type = _cpu_type, \ .driver_data = (unsigned long) _data \ } @@ -98,7 +99,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - feature, data) + feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CPU feature @@ -112,7 +113,7 @@ */ #define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -125,7 +126,7 @@ */ #define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -136,7 +137,7 @@ */ #define X86_MATCH_FEATURE(feature, data) \ X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -150,7 +151,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - X86_FEATURE_ANY, data) + X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -163,7 +164,7 @@ */ #define X86_MATCH_VENDOR_FAM(vendor, family, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_INTEL_FAM6_MODEL - Match vendor INTEL, family 6 and model @@ -183,7 +184,7 @@ #define X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(model, steppings, data) \ X86_MATCH_CPU(X86_VENDOR_INTEL, 6, INTEL_FAM6_##model, \ - steppings, X86_FEATURE_ANY, data) + steppings, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -194,7 +195,7 @@ */ #define X86_MATCH_VFM(vfm, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping @@ -206,7 +207,7 @@ */ #define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) + steppings, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -218,7 +219,19 @@ */ #define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) + +/** + * X86_MATCH_VFM_CPU_TYPE - Match encoded vendor/family/model/cpu-type + * @vfm: Encoded 8-bits each for vendor, family, model + * @cpu_type: CPU type e.g. P-core, E-core on Intel + * @data: Driver specific data or NULL. The internal storage + * format is unsigned long. The supplied value, pointer + * etc. is cast to unsigned long internally. + */ +#define X86_MATCH_VFM_CPU_TYPE(vfm, cpu_type, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, cpu_type, data) /* * Match specific microcode revisions. diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 4338b1b4ac44..b8a2e88f966f 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -692,6 +692,7 @@ struct x86_cpu_id { __u16 feature; /* bit index */ /* Solely for kernel-internal use: DO NOT EXPORT to userspace! */ __u16 flags; + __u8 cpu_type; kernel_ulong_t driver_data; }; @@ -701,6 +702,7 @@ struct x86_cpu_id { #define X86_MODEL_ANY 0 #define X86_STEPPING_ANY 0 #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ +#define X86_CPU_TYPE_ANY 0 /* * Generic table type for matching CPU features. From patchwork Thu Jun 27 20:44:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715021 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FD2C1A0729; Thu, 27 Jun 2024 20:44:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521085; cv=none; b=OnwGiC9SnpUdHwsT0eN0RwZNwrSaO8W4/RcZsLNZLbCY1qkVKcTXeFFIz5i7c7+s7dqig69je7sKLBw1J7nwAe+6vfxwcnxoXjewnMFHUB/DclBOo0hKvusjBUoOYa2TZ6tt57E+36IGRCVzKeGYn7KFxXGLlnEKXk0FszHm1nk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521085; c=relaxed/simple; bh=OEfQqdYgE2tBKPCJz5LhDneI5bGCQKBVyCZ/vbzQ2HI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=VabCmDDkfWDM4bAbeut4DJhoTIU05gCU8cPJXjwcE/YV26DgSRsGseC9H5e/npx9+N+qNMZ3KS2p3HuG+OFSU9wlfkaKoFYRWZ0Mz+U0ZuMebJOm3XemnfYXkAU8C9EwNsOOvYHfcLowNVh+JBnH/PmXFQtLjwhu4btkwbDRPRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a5R7rCs3; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a5R7rCs3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521084; x=1751057084; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=OEfQqdYgE2tBKPCJz5LhDneI5bGCQKBVyCZ/vbzQ2HI=; b=a5R7rCs3hk0hY/96kuvT2Mhibo4GUYCGBOb82r0rFJyJA60cPI/HI7JI ZAJvyxQYLfFNeNct3PWN1zPPjY9ai99t987r6vbloAP3v2gcWclXXPbUg X8Y7MEALFJMYkkkW/CkBNdT6HIyPK2ao8vMqZ/QwFyXyzCXhvWowTSsLR Cqq+GS1hv73eoNPyQThPc4bBoIcL67GtL+6u7xY2gfZokKUaJdxSStIbu BK5JhqJql2j7r47Zs3pyLLIuPq8Oq9keFK5gOtbybwQsDNewF8crE8X1t W0eLXoIIDqDbh7eyRkdiFKwF3XVSk2S/LdjFp3WNgrZvhU4lWcgTFbb7s g==; X-CSE-ConnectionGUID: 1hd+rOotR3KMh9GTSPB0qQ== X-CSE-MsgGUID: cng/CrTvTlyg+mb74/JiZw== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16563610" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16563610" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:44 -0700 X-CSE-ConnectionGUID: OAi7GxMSS8+IqGidXt9Jpw== X-CSE-MsgGUID: gOQGXh4ySCuRwLVThLfr/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="67703792" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:43 -0700 Date: Thu, 27 Jun 2024 13:44:42 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 7/9] x86/cpu: Update x86_match_cpu() to also use cpu-type Message-ID: <20240627-add-cpu-type-v2-7-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Non-hybrid CPU variants that share the same Family/Model could be differentiated by their cpu-type. x86_match_cpu() currently does not use cpu-type for CPU matching. Dave Hansen suggested to use below conditions to match CPU-type: 1. If CPU_TYPE_ANY (the wildcard), then matched 2. If hybrid, then matched 3. If !hybrid, look at the boot CPU and compare the cpu-type to determine if it is a match. This special case for hybrid systems allows more compact vulnerability list. Imagine that "Haswell" CPUs might or might not be hybrid and that only Atom cores are vulnerable to Meltdown. That means there are three possibilities: 1. P-core only 2. Atom only 3. Atom + P-core (aka. hybrid) One might be tempted to code up the vulnerability list like this: MATCH( HASWELL, X86_FEATURE_HYBRID, MELTDOWN) MATCH_TYPE(HASWELL, ATOM, MELTDOWN) Logically, this matches #2 and #3. But that's a little silly. You would only ask for the "ATOM" match in cases where there *WERE* hybrid cores in play. You shouldn't have to _also_ ask for hybrid cores explicitly. In short, assume that processors that enumerate Hybrid==1 have a vulnerable core type. Update x86_match_cpu() to also match cpu-type. Also treat hybrid systems as special, and match them to any cpu-type. Suggested-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/match.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c index 8e7de733320a..85ef17325c06 100644 --- a/arch/x86/kernel/cpu/match.c +++ b/arch/x86/kernel/cpu/match.c @@ -5,6 +5,26 @@ #include #include +/** + * x86_match_hw_cpu_type - helper function to match the hardware defined + * cpu-type for a single entry in the x86_cpu_id table. + * @c: Pointer to the cpuinfo_x86 structure of the CPU to match. + * @m: Pointer to the x86_cpu_id entry to match against. + * + * Return: true if the cpu-type matches, false otherwise. + */ +static bool x86_match_hw_cpu_type(struct cpuinfo_x86 *c, const struct x86_cpu_id *m) +{ + if (m->cpu_type == X86_CPU_TYPE_ANY) + return true; + + /* Hybrid CPUs are special, they are assumed to match all cpu-types */ + if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) + return true; + + return c->topo.hw_cpu_type == m->cpu_type; +} + /** * x86_match_cpu - match current CPU again an array of x86_cpu_ids * @match: Pointer to array of x86_cpu_ids. Last entry terminated with @@ -50,6 +70,8 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match) continue; if (m->feature != X86_FEATURE_ANY && !cpu_has(c, m->feature)) continue; + if (!x86_match_hw_cpu_type(c, m)) + continue; return m; } return NULL; From patchwork Thu Jun 27 20:44:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715022 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A14AA1A00E3; Thu, 27 Jun 2024 20:44:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521092; cv=none; b=PdjMwYl51e163Hiq8uUEWeDYkrxhrLLVKvqpFQ5rCbnC5Rpmes9zUWkDR+a1LBBTH43TMngIMkkoEM28NQsWODGynzzrJCmbU8Orc865sn9402FxyA1VJno8PGgycDdQdY8qToIwMBDMyd99IFKJGGw+zBEUduiIiKZhWJlBxAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521092; c=relaxed/simple; bh=CLipC/tpnvoXX06aqacY8oa3NadWRlW6zdDbfrMIo+M=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=q3ju4A14AX0cNSQL1EHkIEO3LadqssU4c91k4NWDdoUp0IFKRQz7MW3mPqbcupTZzhARqhzqAgptMI4uLQ+7sY6ekp9sMbeomesM3jVPOHffSo6c1wOKUWccA9OKNBtPp5NTaY+z17OZ7eCi+FtH2NgzirQHakspl/6AbNVuoUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ioiBCeT/; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ioiBCeT/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521091; x=1751057091; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=CLipC/tpnvoXX06aqacY8oa3NadWRlW6zdDbfrMIo+M=; b=ioiBCeT/He/UWejaXlJ4T3pm4Ro2uLKvNtSa5fRifjzM2ReMyl0lMz3H gtu0zXbiDqiZvwvdKrp+z5GaZqRIqj2UN3dnt4f9Y4aTB4UAWYB5eRzm8 24tM635BTfGycfG+00jxZqgDSiZGlpE6LEJE/5OG2FDwYXWstcWr3LjYT Fab0SXO/pUFecVhgViO7pppeOkokNNsBxEZLapgyf5eC1759fPYBKu20k 6WTy89oZMwefTn5f2xZ86I+5zY0z8US6G+qQeZFF3oeCVfDhymuyqAz5x alkYRQtdgLdrOFSbsrn2PkMHpncwsfQ5Rmzt7n7IzRCp/BGemxl+jX5+j A==; X-CSE-ConnectionGUID: oj3BbQfGQb+N/hu0vGRSEg== X-CSE-MsgGUID: Pm6/Z2vERZ2MfVR4JsYpSw== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16563641" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16563641" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:50 -0700 X-CSE-ConnectionGUID: j4C9d+tKTFWlasfS3jR8Lg== X-CSE-MsgGUID: gzXsJ6PKTYG9Dg6jhgY5ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="67703813" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:49 -0700 Date: Thu, 27 Jun 2024 13:44:48 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 8/9] x86/bugs: Declutter vulnerable CPU list Message-ID: <20240627-add-cpu-type-v2-8-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> The affected processor table has a lot of repetition and redundant information that can be omitted. For example: VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), can easily be simplified to: VULNBL_INTEL(IVYBRIDGE, SRBDS), Apply this to all the entries in the affected processor table. No functional change. Disassembly of arch/x86/kernel/cpu/common.o does not show any difference before and after the change. Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/common.c | 133 ++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 64 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index d4e539d4e158..7e5cd14e509f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1128,7 +1128,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) #define VULNWL_INTEL(vfm, whitelist) \ - X86_MATCH_VFM(vfm, whitelist) + X86_MATCH_VFM(INTEL_##vfm, whitelist) #define VULNWL_AMD(family, whitelist) \ VULNWL(AMD, family, X86_MODEL_ANY, whitelist) @@ -1145,32 +1145,32 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), /* Intel Family 6 */ - VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), + VULNWL_INTEL(TIGERLAKE, NO_MMIO), + VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), + VULNWL_INTEL(ALDERLAKE, NO_MMIO), + VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), + VULNWL_INTEL(CORE_YONAH, NO_SSB), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), /* * Technically, swapgs isn't serializing on AMD (despite it previously @@ -1180,9 +1180,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { * good enough for our purposes. */ - VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), /* AMD Family 0xf - 0x12 */ VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), @@ -1203,8 +1203,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) -#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ - X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) +#define VULNBL_INTEL(vfm, issues) \ + X86_MATCH_VFM(INTEL_##vfm, issues) + +#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ + X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues) #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1229,43 +1232,45 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define RFDS BIT(7) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { - VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), + VULNBL_INTEL(IVYBRIDGE, SRBDS), + VULNBL_INTEL(HASWELL, SRBDS), + VULNBL_INTEL(HASWELL_L, SRBDS), + VULNBL_INTEL(HASWELL_G, SRBDS), + VULNBL_INTEL(HASWELL_X, MMIO), + VULNBL_INTEL(BROADWELL_D, MMIO), + VULNBL_INTEL(BROADWELL_G, SRBDS), + VULNBL_INTEL(BROADWELL_X, MMIO), + VULNBL_INTEL(BROADWELL, SRBDS), + VULNBL_INTEL(SKYLAKE_X, MMIO | RETBLEED | GDS), + VULNBL_INTEL(SKYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL(SKYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL(KABYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL(KABYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL(CANNONLAKE_L, RETBLEED), + VULNBL_INTEL(ICELAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL(ICELAKE_D, MMIO | GDS), + VULNBL_INTEL(ICELAKE_X, MMIO | GDS), + VULNBL_INTEL(COMETLAKE, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL(TIGERLAKE_L, GDS), + VULNBL_INTEL(TIGERLAKE, GDS), + VULNBL_INTEL(LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL(ROCKETLAKE, MMIO | RETBLEED | GDS), + VULNBL_INTEL(ALDERLAKE, RFDS), + VULNBL_INTEL(ALDERLAKE_L, RFDS), + VULNBL_INTEL(RAPTORLAKE, RFDS), + VULNBL_INTEL(RAPTORLAKE_P, RFDS), + VULNBL_INTEL(RAPTORLAKE_S, RFDS), + VULNBL_INTEL(ATOM_GRACEMONT, RFDS), + VULNBL_INTEL(ATOM_TREMONT, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL(ATOM_TREMONT_D, MMIO | RFDS), + VULNBL_INTEL(ATOM_TREMONT_L, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL(ATOM_GOLDMONT, RFDS), + VULNBL_INTEL(ATOM_GOLDMONT_D, RFDS), + VULNBL_INTEL(ATOM_GOLDMONT_PLUS, RFDS), + + /* Match more than Vendor/Family/Model */ + VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), + VULNBL_INTEL (COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), VULNBL_AMD(0x15, RETBLEED), VULNBL_AMD(0x16, RETBLEED), From patchwork Thu Jun 27 20:44:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13715023 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3AB21AB526; Thu, 27 Jun 2024 20:44:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521098; cv=none; b=g1ldIADuxwmYnG/45EVX1WWMcohxVjyqn15HIuJl7/a+n1UYrZ88vkL7jg7zFWfCJufXHrw7ZMZwAxC74dLnsgznbW/ERuPJb1NMiVSKo0idYs208dXf3Hv2bs30VB+a0A+VFY0G5L656tCwN3an35eThPn/VMX7fTWFUXi2BVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719521098; c=relaxed/simple; bh=Z4q+zpMXd0kJ8jYYaQfZ8MixUXEGYXZEREi91EWfp04=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=H0+2xI8eSB+2iF0zj++BptTbehFr9hiZqXenT9NWdzsCGl/wK5ArhRdVOKTG6rZ0j0aZkT8wrGD4QBWdhkZmH5RyR0HAngaEIzrJkroIRsRbijTC3JghbAFav3Ma1xpFusd+QtoioBE0AdRjatiO5fXpENlSkrY1AxlQzm6hbbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QhzJ8g5t; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QhzJ8g5t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719521097; x=1751057097; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Z4q+zpMXd0kJ8jYYaQfZ8MixUXEGYXZEREi91EWfp04=; b=QhzJ8g5t5knuGZz5MARzXRHQwjxp4zSwyLTwUary/FCpfN1DeKbqj+ht /NOYtSuVdVNjl0Bm2ZU2jIPsYcBU+WDSOD+2MizkDplto88UGVJLqHyyw Z7xnNsj3/d9HPm6tQh/hoMeUzn6HQ1ce8FHLok4oJyQ2QBMVFjU4Lp1pg vPEnBDQecAE69H49w9O7vlcv1mzSJ2cylaSZrLsp/5YkppRR3E45Ajq8F yhVfN10n5XJx9tVU6LJacRYTXrtpn2P/7vmYa+8kcw8jka6EMuvf87pVJ zqSL3E/ctJuFM/Z024A9mHAILUfGsGkVDeNrZohz2rtkhEbmkwIotwKpe A==; X-CSE-ConnectionGUID: rDEn7FOQSBSiITeOUqZ+uA== X-CSE-MsgGUID: l2MLB1ytROix8h8TvtyvAA== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16563661" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16563661" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:56 -0700 X-CSE-ConnectionGUID: wOzLDcVMTu2OYBg+UJfd7A== X-CSE-MsgGUID: 2ffpSzJkQ8m/6HnQSujCoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="67703836" Received: from gbpfeiff-mobl.amr.corp.intel.com (HELO desk) ([10.255.229.132]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:44:56 -0700 Date: Thu, 27 Jun 2024 13:44:55 -0700 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH PATCH v2 9/9] x86/rfds: Exclude P-only parts from the RFDS affected list Message-ID: <20240627-add-cpu-type-v2-9-f927bde83ad0@linux.intel.com> X-Mailer: b4 0.12.3 References: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240627-add-cpu-type-v2-0-f927bde83ad0@linux.intel.com> RFDS only affects Atom parts. Vendor/Family/Model matching in the affected processor table makes Alderlake and Raptorlake P-only parts affected (which are not affected in reality). This is because the affected hybrid and E-only parts have the same Family/Model as the unaffected P-only parts. Match CPU-type as Atom to exclude P-only parts as RFDS affected. Note, a guest with the same Family/Model as the affected part may not have leaf 1A enumerated to know its CPU-type, but it should not be a problem as guest's Family/Model can anyways be inaccurate. Moreover, RFDS_NO or RFDS_CLEAR enumeration by the VMM decides the affected status of the guest. Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst | 8 -------- arch/x86/kernel/cpu/common.c | 9 +++++++-- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst b/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst index 0585d02b9a6c..ad15417d39f9 100644 --- a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst +++ b/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst @@ -29,14 +29,6 @@ Below is the list of affected Intel processors [#f1]_: RAPTORLAKE_S 06_BFH =================== ============ -As an exception to this table, Intel Xeon E family parts ALDERLAKE(06_97H) and -RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as -vulnerable in Linux because they share the same family/model with an affected -part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR or -CPUID.HYBRID. This information could be used to distinguish between the -affected and unaffected parts, but it is deemed not worth adding complexity as -the reporting is fixed automatically when these parts enumerate RFDS_NO. - Mitigation ========== Intel released a microcode update that enables software to clear sensitive diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7e5cd14e509f..86e0c69a60f6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1209,6 +1209,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues) +#define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ + X86_MATCH_VFM_CPU_TYPE(INTEL_##vfm, \ + X86_HW_CPU_TYPE_INTEL_##cpu_type, \ + issues) + #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1255,9 +1260,7 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL(TIGERLAKE, GDS), VULNBL_INTEL(LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), VULNBL_INTEL(ROCKETLAKE, MMIO | RETBLEED | GDS), - VULNBL_INTEL(ALDERLAKE, RFDS), VULNBL_INTEL(ALDERLAKE_L, RFDS), - VULNBL_INTEL(RAPTORLAKE, RFDS), VULNBL_INTEL(RAPTORLAKE_P, RFDS), VULNBL_INTEL(RAPTORLAKE_S, RFDS), VULNBL_INTEL(ATOM_GRACEMONT, RFDS), @@ -1271,6 +1274,8 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { /* Match more than Vendor/Family/Model */ VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), VULNBL_INTEL (COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_TYPE (ALDERLAKE, ATOM, RFDS), + VULNBL_INTEL_TYPE (RAPTORLAKE, ATOM, RFDS), VULNBL_AMD(0x15, RETBLEED), VULNBL_AMD(0x16, RETBLEED),