From patchwork Fri Jun 28 21:48:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13716688 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 972207FBA0; Fri, 28 Jun 2024 21:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; cv=none; b=LUvHCZl+ynryrU6+x1tb2V8kTOulwsuUn8JfZGOsGygwRLy2XpVnYX6nwfLoiE9TIcIpGQVEPRC7CArcpbA9Vk+y258k7aQkVEjzL2i4NtxWMDMOMmh6cWwCaj9duf71qzJil9Q8fK3ud3KlMR/UkQW7SkXHYmtmD/Kgzg3pyfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; c=relaxed/simple; bh=BFLLNRilEHBfhYwQnS8pPKKA3DqGLV81Xz7MOjtsre4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iy5POlre0J7gwxOvkuBxNK2qyf+n16lXNfEqwRDvGVa7HE1CKmGBLTmDx76rpQOqunJ1qRIX8/cWVlGXMVZTzm+Hmrf2750AJYaJ1FcuaSCez82hg1ePkc2kSF8GVThEHB3h4K2cwNSzEUlN0h4y9r8+686mSR+G6bWclZ1U+bo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CpvQxI0+; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CpvQxI0+" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SEMYOu015304; Fri, 28 Jun 2024 21:49:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Vm45qtPYuqvqe1oypVuQAO31QWMITR+NBn4ratvtn3Q=; b=CpvQxI0+iVlmViG9 UdqS+lbHIUEvGqiB810jLiTgKGp8Y497kPsRvrdM1QIwv/oWrArObhvp5PuOrv4N 4/UjqEyWRjkCXgSx0ExGvTmTbDhr3zsdDtqLM45OBY8XAzvJ7HuHsDI7Vyg2DBf/ dDFAFIis3wT1NFGkGnlldbrZb8nHM+8WczeVV0SwEuc9BMaL/UKSA9sWwhVe9Ts/ 7xchAQvjFBo2qsKWc6npd29WT6g0mmvYoBZuH6DHByQIa1mWMm727z187zyFj812 DBOppWhzPmgvy8aQqWFq/0xKQKTujIJL2t6doDK9JKIqO1ENyQqA8JwfobHleDAY 3OEVYw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 400gcmgbfp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SLn24S032485 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:02 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 14:49:01 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 1/5] drm/msm: register a fault handler for display mmu faults Date: Fri, 28 Jun 2024 14:48:43 -0700 Message-ID: <20240628214848.4075651-2-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> References: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 766gpcJrzJDNNb1KuLkBvVWmnIWE_J_w X-Proofpoint-ORIG-GUID: 766gpcJrzJDNNb1KuLkBvVWmnIWE_J_w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_16,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 phishscore=0 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280164 In preparation to register a iommu fault handler for display related modules, register a fault handler for the backing mmu object of msm_kms. Currently, the fault handler only captures the display snapshot but we can expand this later if more information needs to be added to debug display mmu faults. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_kms.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index af6a6fcb1173..2d7c5a5e22e0 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -164,12 +164,23 @@ void msm_crtc_disable_vblank(struct drm_crtc *crtc) vblank_ctrl_queue_work(priv, crtc, false); } +static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags, void *data) +{ + struct msm_kms *kms = arg; + + msm_disp_snapshot_state(kms->dev); + + return -ENOSYS; +} + struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) { struct msm_gem_address_space *aspace; struct msm_mmu *mmu; struct device *mdp_dev = dev->dev; struct device *mdss_dev = mdp_dev->parent; + struct msm_drm_private *priv = dev->dev_private; + struct msm_kms *kms = priv->kms; struct device *iommu_dev; /* @@ -197,6 +208,8 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) mmu->funcs->destroy(mmu); } + msm_mmu_set_fault_handler(aspace->mmu, kms, msm_kms_fault_handler); + return aspace; } From patchwork Fri Jun 28 21:48:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13716689 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 971137E56B; Fri, 28 Jun 2024 21:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; cv=none; b=H6E5vdS3K/QDF5hj6TcnmD+u4dc6+Iyx8WEMaPu1/Ppn05yGbFUbcLs8tAWbP4/kBXlMB6xwHAggS/w/6JZLBEjuz13495wM1HIRJAEo6OV+sNGJ30qkuqkZD23x+gRkl7UNSEvo+kaORrK/D5K/u0zuuCeeAZgHRw5lQ49QW+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; c=relaxed/simple; bh=g+ORvJ0RsstaSZcylqOz47mI7u5C3HD5piOed9fEK2E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M1sT40gXCll0WQMYnxFjBxGzG+CTlxqqhK3PjOhSOAUnuAYyKZGkSJujLjtZS65DICE14qL4tjCPLZDGoavteK/iCj8HjNxB5F2hF9+jJY/3/rmezVDNVGq0+NZCFJitTUZBnEZaxo15N71KByxExIJ5/QrWyHLt9FhAAID/tUE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=H7YO+cqY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="H7YO+cqY" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SEfj5d010388; Fri, 28 Jun 2024 21:49:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xZaprBArW1L7QsxACmo9caYiTRV4yfhCxlPzTci8mgs=; b=H7YO+cqY4juU9IUb CL9LIRAmNQn4UBiKQ+jIf7FI2CCJNtf0rsuhDp1ko/H5QPktJuLdh+uUMyOW2Xkr rBLkVDIBBD6dUwv5uJ0WFzxJltLIU2jKgbbMlnKtmfeL6H3xxIAPMUZzJ3E/02SV K//IEMcGC/08VRLE/rRMB2z7XqmkYblWyy2woBIT9rePftrH4i2HUb8VFDyFKvNZ iIRZRt09es8MZUUBlLtQRVrPv7urrq9PYIcQnGlO0At4UdGovc5aw8WZ2mhhamIg IdoZtyJEc/OCdUI5k/DibWuFNtkrxexj4dgAEJtVQMM08Nm4hV670gvm3wI15KIw ysjglQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ywpu1gwb1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SLn3o2032520 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:03 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 14:49:03 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 2/5] drm/msm/iommu: rename msm_fault_handler to msm_gpu_fault_handler Date: Fri, 28 Jun 2024 14:48:44 -0700 Message-ID: <20240628214848.4075651-3-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> References: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: OXsAMSLQIthwCztSd9Fb1rr4tXUhRusA X-Proofpoint-ORIG-GUID: OXsAMSLQIthwCztSd9Fb1rr4tXUhRusA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_16,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=935 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280164 In preparation of registering a separate fault handler for display, lets rename the existing msm_fault_handler to msm_gpu_fault_handler. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index d5512037c38b..a79cd18bc4c9 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -243,7 +243,7 @@ static const struct iommu_flush_ops tlb_ops = { .tlb_add_page = msm_iommu_tlb_add_page, }; -static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, +static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg); struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) @@ -319,7 +319,7 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) return &pagetable->base; } -static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, +static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg; @@ -445,7 +445,7 @@ struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsig return mmu; iommu = to_msm_iommu(mmu); - iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); + iommu_set_fault_handler(iommu->domain, msm_gpu_fault_handler, iommu); /* Enable stall on iommu fault: */ if (adreno_smmu->set_stall) From patchwork Fri Jun 28 21:48:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13716690 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 217907CF25; Fri, 28 Jun 2024 21:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; cv=none; b=SBANnEEuF+EeztpG9udsYbkv8Clm3EuWGgbNB0fmPIQSN7w0wSA1nZGaDlqAHRGAmcPt+QJp0pvEj3AilBgNFo9PHtECTSN5We8C/zMnLbtL5a5eKHh/d8hdlCCqRWLi5yCdH4UvM+nDtdRN88z228T1+045SBTjFIi8lPY2voE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; c=relaxed/simple; bh=WBzP2QnaXjLHyJ2MfgTPMz58EU6HOyYPMks55Sefw3U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HtMOzdaZfCTEKizaGTaXanE6Qyc4xMiNwJsPK4HF95u/XkcFMweNrAXSkD4rmKduCTC59Nxlre1GPlwPe9KiXQz6yS9QHGZXhxLXJAWkl7RvAZjjV1MiAGXJ4R5VZMuK4wvuV91aKAtp2aT+PaPGaguIc4kFx9/iiLH43Nufi2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=h8bbkNT5; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h8bbkNT5" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SL11Zo007845; Fri, 28 Jun 2024 21:49:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CtAc92ThkQIk2wHAfAQ1fuHdsMif84b8/j5OztsMf3I=; b=h8bbkNT5JXoOX+cI 50xeOb7cvXkrFjeNfRHzJT2O338zIwWi7hbILd6sfGOn013brHkbzP2XcvV1EmL/ ygH58mlt8jIm4yrCJVgIfwuFNk/MeXtCTeVGW3g0r32XWRNVd5X38J3K2ud68bLG 2dkwAtDaNLfDqoyUIfeTfhMDWVzQmWQ0YxFWvnu0l5wVYlO7os3WPhH5W8PQq9xs wydNNGKL2F9HvyRgwR+qfP7E7r/dmQOH9xnKK3ET031oMaiFxRLhWUDcgXTR4aHM 4M+Ha0CHq+zfcoj6z7lGsfbpyo7GtNhUjhG9pilJpzWNho0BTGIDORH1g/roQs/Z 6uMCDA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 401pm5avqd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SLn5LW032545 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:05 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 14:49:04 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 3/5] drm/msm/iommu: introduce msm_iommu_disp_new() for msm_kms Date: Fri, 28 Jun 2024 14:48:45 -0700 Message-ID: <20240628214848.4075651-4-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> References: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: f5uukxJRThcaGTAb2mXAKbI2C4wwFrP0 X-Proofpoint-ORIG-GUID: f5uukxJRThcaGTAb2mXAKbI2C4wwFrP0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_16,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=974 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280164 Introduce a new API msm_iommu_disp_new() for display use-cases. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_iommu.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index a79cd18bc4c9..0420bdc4a224 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -343,6 +343,17 @@ static int msm_gpu_fault_handler(struct iommu_domain *domain, struct device *dev return 0; } +static int msm_disp_fault_handler(struct iommu_domain *domain, struct device *dev, + unsigned long iova, int flags, void *arg) +{ + struct msm_iommu *iommu = arg; + + if (iommu->base.handler) + return iommu->base.handler(iommu->base.arg, iova, flags, NULL); + + return -ENOSYS; +} + static void msm_iommu_resume_translation(struct msm_mmu *mmu) { struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); @@ -434,6 +445,21 @@ struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks) return &iommu->base; } +struct msm_mmu *msm_iommu_disp_new(struct device *dev, unsigned long quirks) +{ + struct msm_iommu *iommu; + struct msm_mmu *mmu; + + mmu = msm_iommu_new(dev, quirks); + if (IS_ERR_OR_NULL(mmu)) + return mmu; + + iommu = to_msm_iommu(mmu); + iommu_set_fault_handler(iommu->domain, msm_disp_fault_handler, iommu); + + return mmu; +} + struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsigned long quirks) { struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 88af4f490881..730458d08d6b 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -42,6 +42,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks); struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsigned long quirks); +struct msm_mmu *msm_iommu_disp_new(struct device *dev, unsigned long quirks); static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, int (*handler)(void *arg, unsigned long iova, int flags, void *data)) From patchwork Fri Jun 28 21:48:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13716687 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 971CB7F7FD; Fri, 28 Jun 2024 21:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; cv=none; b=RUe+lwUk9ewvyKNE606ZFm+nN07kZH8K1RGn1wvpdZPQXPWMOYjdfOKocBn6/0yLUNlsLiEGWdI7B37CYaIw5RAx9/o7IiFUggRycW0KIGujAXzc7cGGvvFjJ3czxoQonb4c4UUH9YWlTuUTfmbMyXxFl57fZrIRWemirIimzFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611358; c=relaxed/simple; bh=Gm3uzSK01WHfzpCFwX1j3v9baN6wsVz03pWs1rR44j0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OiAXUXXJY6ed4zPyKR/eD9fTikHyDiuSYZVqAGrHWrQ5aaQr90DmrTMb6TPro0xZVUKoptBi/ocoojU+5HKDT4DiAxZm7ULPVzxu79iwruNDDMk6ZlSrXEcT0n5FlLETRekwwLNREG+WQgv0cXbCqbn2nGOTpbvG3wPnkQpCkU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=PCa9YJm0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="PCa9YJm0" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SHUJfW000516; Fri, 28 Jun 2024 21:49:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= c+eqiZZZBJlTVcEWYk6Ms1fjTZb6pA2VJtBXo4e5ldA=; b=PCa9YJm0Fh8wgnn+ hNoXXsEpXu5iHuwB5+XwK0IPO+MuPUzbOgnn2QV4kxIruGsw4NW3BU9OTtvyQB+a elScOBsUmquLKFR4+6SVOxyRu30ntro0zuGkLuVvCxHlz2Zxg2XqDqKya4FScp6R E6L6Pv1onCtKKZc+ntr48ZL3X2JHs/SHNulBNjsjvh6C+MOTQW+oG0MZ+kehzj4x IXyPPyUsWIPYuaHYhp2MXZzu8XgWI+VfXx4iYdcTNRn8qJdG9l7mlndBl29V1lyI oYTY1LPHKsVl7U9r7mVSgo1twglViSJExrV0z3bFQWGADUByMcbaoqylKrmLRQyz 5agqxA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 401ubvsxyb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SLn6ng029591 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:06 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 14:49:05 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 4/5] drm/msm: switch msm_kms to use msm_iommu_disp_new() Date: Fri, 28 Jun 2024 14:48:46 -0700 Message-ID: <20240628214848.4075651-5-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> References: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: LWQpNDELOL2zwqhZv22QO_0HS1FMfJi_ X-Proofpoint-GUID: LWQpNDELOL2zwqhZv22QO_0HS1FMfJi_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_16,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280164 Switch msm_kms to use msm_iommu_disp_new() so that the newly registered fault handler will kick-in during any mmu faults. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 2d7c5a5e22e0..d5d3117259cf 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -192,7 +192,7 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) else iommu_dev = mdss_dev; - mmu = msm_iommu_new(iommu_dev, 0); + mmu = msm_iommu_disp_new(iommu_dev, 0); if (IS_ERR(mmu)) return ERR_CAST(mmu); From patchwork Fri Jun 28 21:48:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13716691 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9717A7F7F7; Fri, 28 Jun 2024 21:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611359; cv=none; b=BSHlsUUnvCmRZ5gLbXjLoIAnI6xz9u4LJlaIgpATcO6ZN9n+K5I57gc6HA2TL0YRpxn4+YqcCtTIDEUPZX/bE+KE3MvcdyrR9vmU4n2CfnTQmjfjhtl+VtoX2dz2TIcFPVngZOY22ISp2N8dRwyZd0zy9hkKXTR/lqVc1sdC1dk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719611359; c=relaxed/simple; bh=KVv15TCBlr/3OlE7u3q1NVhY3YIWEx1DUoVIOmE+Nz0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ra3GD1MzgPoqwmY+Xe7bOqSp0Xee0bIIHAKEJHhBNjBYzyTi/6kgRPLUQEmgkXdVz4tXzqBZg9eMyhgrM0+ORMBvJKfrkD5ZuV8wUGQ20AE6GnpJ6tZbAHCmwb4CjOn0OB4iWYW9bQqtrdwx9PwMZky3htr+Xz16GJhku9+1IVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=K0+QlJgU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="K0+QlJgU" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SEwC2O015144; Fri, 28 Jun 2024 21:49:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= jm7Cf/Q39JQalwuzHNAv49M3o2JwsID+UdsKSQlM8eQ=; b=K0+QlJgUHiH4hm92 H+vHf98TGogbijDznplTolcO1IDgvf9Kv3q5OHoKTjbWa7f4MDRP7icgOWOk51tJ VNndVLAMDBnvPkWNQSFy0KyvPghkkil+BIcET/tyukfvdnuZbhiPgCFKo1wNTG1B iBztSELWOBiK0t6zp2lO35lKt8Iqw5DIiNoM5NbWpqA7CiPKMttyYfBVKWWMCjxd BJ9HnRD4G75URAbYFS7aAkhh0t3mj+DW8qQ4nzfh+sdUt82fgKKFzGYFznP+zrXN Rngt7RMvUh1/rheQBUaxNh+m8DR0JtVqX0wTIYAG6mTnlJ4ljppmVMHPg1OoSPtO xlco/A== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ywqsj1ffe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:08 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SLn7wp032577 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 21:49:07 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 14:49:07 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Subject: [PATCH 5/5] drm/msm/dpu: rate limit snapshot capture for mmu faults Date: Fri, 28 Jun 2024 14:48:47 -0700 Message-ID: <20240628214848.4075651-6-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> References: <20240628214848.4075651-1-quic_abhinavk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: D2rY39SGmFw3r9mIXf-cT9g1pF3whRcx X-Proofpoint-GUID: D2rY39SGmFw3r9mIXf-cT9g1pF3whRcx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_16,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280164 There is no recovery mechanism in place yet to recover from mmu faults for DPU. We can only prevent the faults by making sure there is no misconfiguration. Rate-limit the snapshot capture for mmu faults to once per msm_kms_init_aspace() as that should be sufficient to capture the snapshot for debugging otherwise there will be a lot of dpu snapshots getting captured for the same fault which is redundant and also might affect capturing even one snapshot accurately. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_kms.c | 6 +++++- drivers/gpu/drm/msm/msm_kms.h | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index d5d3117259cf..90a333920c01 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -168,7 +168,10 @@ static int msm_kms_fault_handler(void *arg, unsigned long iova, int flags, void { struct msm_kms *kms = arg; - msm_disp_snapshot_state(kms->dev); + if (!kms->fault_snapshot_capture) { + msm_disp_snapshot_state(kms->dev); + kms->fault_snapshot_capture++; + } return -ENOSYS; } @@ -208,6 +211,7 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) mmu->funcs->destroy(mmu); } + kms->fault_snapshot_capture = 0; msm_mmu_set_fault_handler(aspace->mmu, kms, msm_kms_fault_handler); return aspace; diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 1e0c54de3716..240b39e60828 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -134,6 +134,9 @@ struct msm_kms { int irq; bool irq_requested; + /* rate limit the snapshot capture to once per attach */ + int fault_snapshot_capture; + /* mapper-id used to request GEM buffer mapped for scanout: */ struct msm_gem_address_space *aspace;