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([2804:14c:485:4b61:3b92:aca:e1bb:86dc]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fad0677f1dsm14107765ad.83.2024.06.28.19.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 19:47:42 -0700 (PDT) From: Fabio Estevam To: shawnguo@kernel.org Cc: linux-arm-kernel@lists.infradead.org, Fabio Estevam Subject: [PATCH v2] ARM: mach-imx: imx6sx: Remove Ethernet refclock setting Date: Fri, 28 Jun 2024 23:47:35 -0300 Message-Id: <20240629024735.393050-1-festevam@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240628_194744_013987_A9959562 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Fabio Estevam The Ethernet refclock configuration is board specific and should not be harcoded in machine code. Remove it to align with the imx6ul commit e87f3be1c7f8 ("ARM: mach-imx: imx6ul: remove not optional ethernet refclock overwrite"). Clearing bits 13 and 17 of GPR1 is the POR values, so this change does not affect existing boards in mainline. Tested on imx6sx-udoo-neo and imx6sx-sdb boards. Signed-off-by: Fabio Estevam --- Changes since v1: - Fixed typo in the Subject (imx6ul-->imx6sx). arch/arm/mach-imx/mach-imx6sx.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index 9ababf4ac210..3feb31ab556e 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -7,37 +7,15 @@ #include #include #include -#include #include #include "common.h" #include "cpuidle.h" -static void __init imx6sx_enet_clk_sel(void) -{ - struct regmap *gpr; - - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr"); - if (!IS_ERR(gpr)) { - regmap_update_bits(gpr, IOMUXC_GPR1, - IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, - IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0); - } else { - pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n"); - } -} - -static inline void imx6sx_enet_init(void) -{ - imx6sx_enet_clk_sel(); -} - static void __init imx6sx_init_machine(void) { of_platform_default_populate(NULL, NULL, NULL); - imx6sx_enet_init(); imx_anatop_init(); imx6sx_pm_init(); }