From patchwork Mon Jul 1 09:07:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 13717739 X-Patchwork-Delegate: kuba@kernel.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AD323207; Mon, 1 Jul 2024 10:00:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719828025; cv=none; b=mPQXpidxcuofZipBTe5rYRSrFGdOALv2u628mur0CKldzl3yV2hmD/eG+811cGnRdl6LDfrbhUxrT81s0dr+6dzziDJdRQobo51kg2o+TmbCj8eZMTYaZXUlW7bG/4fQfCU4/EjToUhCrBDtgX2kgynFNlCnBHk8qpnbb/vz2WY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719828025; c=relaxed/simple; bh=RUf7OjjTglvTPXGaPVeizucUUQcyVBcR3ba4jC8am9c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TQO6bydQNSxclCTxlsL/mz4KHpNj09snEiKK+XPeBczrxUProdIPnjsxL4A1GJ117PBKlsgkdnut6eCZ1O2SZr5MXNZTnuwRa7ue7+McoU3XcPDK2oq828bFu2ElT0qDT6qBLF3kkX+TRe7Iv8uSh/mVbJ05iN5pLAxzf4JJw3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=XOUQQgmK; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="XOUQQgmK" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4618vWEW022313; Mon, 1 Jul 2024 02:07:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=r V/vwo6keil1TY6K9z6dN0ncA5BO0qdU5lVeOPVYXzU=; b=XOUQQgmKbmOuIPBzq /Xwi47VHHLMzo/0h16BE/dYX3cyKTcxlAtNNuaJfYv+LjZ7jDO4L9SEoPgq0JSwx BUm6TvmloehuUwZ0WgxVrRw2EA/E5n7iKp3T368STe5evXmtMIxGG4e7tmrfXo7h 7pv172C/DPNvTeJfZuOO3tkRRWsxbe/2vcDBdkiJgEGLoguEXcuq0BMhuTjs/1ui dE+l9IBKdfGBIZlhIc9zpRzozR1iVF/GZqPT9wvA3nUORx9A/Y2dHtVr92aEXU++ 2Ee02SOx6iZd3qszJ1EwzPFCkI2j6tnnCxkwlXobF6hSLuep3fAyMZlLcfk/nRLv qyAxQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 403sdcg1my-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 Jul 2024 02:07:58 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 1 Jul 2024 02:07:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 02:07:57 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 7615B3F7055; Mon, 1 Jul 2024 02:07:52 -0700 (PDT) From: Srujana Challa To: , CC: , , , , , , , , , , Nithin Dabilpuram Subject: [PATCH net,1/6] octeontx2-af: replace cpt slot with lf id on reg write Date: Mon, 1 Jul 2024 14:37:41 +0530 Message-ID: <20240701090746.2171565-2-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240701090746.2171565-1-schalla@marvell.com> References: <20240701090746.2171565-1-schalla@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: xhxDl6Nlsy0u5m-up4tXOxKgGyOdswgC X-Proofpoint-ORIG-GUID: xhxDl6Nlsy0u5m-up4tXOxKgGyOdswgC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_07,2024-06-28_01,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Nithin Dabilpuram Replace cpt slot id with lf id on reg read/write as CPTPF/VF driver would send slot number instead of lf id in the reg offset. Fixes: ae454086e3c2 ("octeontx2-af: add mailbox interface for CPT") Signed-off-by: Nithin Dabilpuram --- drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c index f047185f38e0..98440a0241a2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c @@ -663,6 +663,8 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) if (lf < 0) return false; + req->reg_offset &= 0xFF000; + req->reg_offset += lf << 3; return true; } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { /* Registers that can be accessed from PF */ @@ -707,12 +709,13 @@ int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, !is_cpt_vf(rvu, req->hdr.pcifunc)) return CPT_AF_ERR_ACCESS_DENIED; + if (!is_valid_offset(rvu, req)) + return CPT_AF_ERR_ACCESS_DENIED; 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Mon, 1 Jul 2024 02:08:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 02:08:00 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id C1EB53F7074; Mon, 1 Jul 2024 02:07:56 -0700 (PDT) From: Srujana Challa To: , CC: , , , , , , , , , Subject: [PATCH net,2/6] octeontx2-af: reduce cpt flt interrupt vectors for cn10kb Date: Mon, 1 Jul 2024 14:37:42 +0530 Message-ID: <20240701090746.2171565-3-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240701090746.2171565-1-schalla@marvell.com> References: <20240701090746.2171565-1-schalla@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: 3xqp-k5PngYfbLWB74-Bnzk2NOLgUgMk X-Proofpoint-ORIG-GUID: 3xqp-k5PngYfbLWB74-Bnzk2NOLgUgMk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_07,2024-06-28_01,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org On new silicon(cn10kb), the number of FLT interrupt vectors has been reduced. Hence, this patch modifies the code to make it work for both cn10ka and cn10kb. Signed-off-by: Srujana Challa --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 5 +- .../ethernet/marvell/octeontx2/af/rvu_cpt.c | 73 ++++++++++++++++--- .../marvell/octeontx2/af/rvu_struct.h | 5 +- 3 files changed, 65 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index 4a77f6fe2622..41b46724cb3d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1848,8 +1848,9 @@ struct cpt_flt_eng_info_req { struct cpt_flt_eng_info_rsp { struct mbox_msghdr hdr; - u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; - u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; +#define CPT_AF_MAX_FLT_INT_VECS 3 + u64 flt_eng_map[CPT_AF_MAX_FLT_INT_VECS]; + u64 rcvrd_eng_map[CPT_AF_MAX_FLT_INT_VECS]; u64 rsvd; }; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c index 98440a0241a2..38363ea56c6c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c @@ -37,6 +37,38 @@ (_rsp)->free_sts_##etype = free_sts; \ }) +#define MAX_AE GENMASK_ULL(47, 32) +#define MAX_IE GENMASK_ULL(31, 16) +#define MAX_SE GENMASK_ULL(15, 0) +static u32 cpt_max_engines_get(struct rvu *rvu) +{ + u16 max_ses, max_ies, max_aes; + u64 reg; + + reg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS1); + max_ses = FIELD_GET(MAX_SE, reg); + max_ies = FIELD_GET(MAX_IE, reg); + max_aes = FIELD_GET(MAX_AE, reg); + + return max_ses + max_ies + max_aes; +} + +/* Number of flt interrupt vectors are depends on number of engines that + * the chip has. Each flt vector represents 64 engines. + */ +static int cpt_10k_flt_nvecs_get(struct rvu *rvu) +{ + u32 max_engs; + int flt_vecs; + + max_engs = cpt_max_engines_get(rvu); + + flt_vecs = (max_engs / 64); + flt_vecs += (max_engs % 64) ? 1 : 0; + + return flt_vecs; +} + static irqreturn_t cpt_af_flt_intr_handler(int vec, void *ptr) { struct rvu_block *block = ptr; @@ -150,17 +182,25 @@ static void cpt_10k_unregister_interrupts(struct rvu_block *block, int off) { struct rvu *rvu = block->rvu; int blkaddr = block->addr; + u32 max_engs; + u8 nr; int i; + max_engs = cpt_max_engines_get(rvu); + /* Disable all CPT AF interrupts */ - rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(0), ~0ULL); - rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(1), ~0ULL); - rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(2), 0xFFFF); + for (i = CPT_10K_AF_INT_VEC_FLT0; i < cpt_10k_flt_nvecs_get(rvu); i++) { + nr = (max_engs > 64) ? 64 : max_engs; + max_engs -= nr; + rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), + INTR_MASK(nr)); + } rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1); rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1); - for (i = 0; i < CPT_10K_AF_INT_VEC_CNT; i++) + /* CPT AF interrupt vectors are flt_int, rvu_int and ras_int. */ + for (i = 0; i < cpt_10k_flt_nvecs_get(rvu) + 2; i++) if (rvu->irq_allocated[off + i]) { free_irq(pci_irq_vector(rvu->pdev, off + i), block); rvu->irq_allocated[off + i] = false; @@ -206,12 +246,17 @@ void rvu_cpt_unregister_interrupts(struct rvu *rvu) static int cpt_10k_register_interrupts(struct rvu_block *block, int off) { + int rvu_intr_vec, ras_intr_vec; struct rvu *rvu = block->rvu; int blkaddr = block->addr; irq_handler_t flt_fn; + u32 max_engs; int i, ret; + u8 nr; + + max_engs = cpt_max_engines_get(rvu); - for (i = CPT_10K_AF_INT_VEC_FLT0; i < CPT_10K_AF_INT_VEC_RVU; i++) { + for (i = CPT_10K_AF_INT_VEC_FLT0; i < cpt_10k_flt_nvecs_get(rvu); i++) { sprintf(&rvu->irq_name[(off + i) * NAME_SIZE], "CPTAF FLT%d", i); switch (i) { @@ -229,20 +274,24 @@ static int cpt_10k_register_interrupts(struct rvu_block *block, int off) flt_fn, &rvu->irq_name[(off + i) * NAME_SIZE]); if (ret) goto err; - if (i == CPT_10K_AF_INT_VEC_FLT2) - rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0xFFFF); - else - rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), ~0ULL); + + nr = (max_engs > 64) ? 64 : max_engs; + max_engs -= nr; + rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), + INTR_MASK(nr)); } - ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RVU, + rvu_intr_vec = cpt_10k_flt_nvecs_get(rvu); + ras_intr_vec = rvu_intr_vec + 1; + + ret = rvu_cpt_do_register_interrupt(block, off + rvu_intr_vec, rvu_cpt_af_rvu_intr_handler, "CPTAF RVU"); if (ret) goto err; rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1); - ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RAS, + ret = rvu_cpt_do_register_interrupt(block, off + ras_intr_vec, rvu_cpt_af_ras_intr_handler, "CPTAF RAS"); if (ret) @@ -922,7 +971,7 @@ int rvu_mbox_handler_cpt_flt_eng_info(struct rvu *rvu, struct cpt_flt_eng_info_r return blkaddr; block = &rvu->hw->block[blkaddr]; - for (vec = 0; vec < CPT_10K_AF_INT_VEC_RVU; vec++) { + for (vec = 0; vec < cpt_10k_flt_nvecs_get(block->rvu); vec++) { spin_lock_irqsave(&rvu->cpt_intr_lock, flags); rsp->flt_eng_map[vec] = block->cpt_flt_eng_map[vec]; rsp->rcvrd_eng_map[vec] = block->cpt_rcvrd_eng_map[vec]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h index 5ef406c7e8a4..120776063e86 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h @@ -71,13 +71,10 @@ enum cpt_af_int_vec_e { CPT_AF_INT_VEC_CNT = 0x4, }; -enum cpt_10k_af_int_vec_e { +enum cpt_cn10k_flt_int_vec_e { CPT_10K_AF_INT_VEC_FLT0 = 0x0, CPT_10K_AF_INT_VEC_FLT1 = 0x1, CPT_10K_AF_INT_VEC_FLT2 = 0x2, - CPT_10K_AF_INT_VEC_RVU = 0x3, - CPT_10K_AF_INT_VEC_RAS = 0x4, - CPT_10K_AF_INT_VEC_CNT = 0x5, }; /* NPA Admin function Interrupt Vector Enumeration */ From patchwork Mon Jul 1 09:07:43 2024 Content-Type: text/plain; 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Specifically, it corrects the `blkaddr` field type from `int` to `u8`. Signed-off-by: Srujana Challa --- drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index 41b46724cb3d..799aa54103a2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1745,7 +1745,7 @@ struct cpt_lf_alloc_req_msg { u16 nix_pf_func; u16 sso_pf_func; u16 eng_grpmsk; - int blkaddr; + u8 blkaddr; u8 ctx_ilen_valid : 1; u8 ctx_ilen : 7; }; From patchwork Mon Jul 1 09:07:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 13717698 X-Patchwork-Delegate: kuba@kernel.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 943DC85656; Mon, 1 Jul 2024 09:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719824899; cv=none; b=J6eIJFiTKLSY7VEX2/G2e8+HgkT2O/tpOcZw0Uj3NHUGZMsKc1sEcT3ZsPdUPZuKKBZEL6gpIcypiCZrrBLXtcnqfTgKIv+AEfJIhh5OLZ5zECN1b85+pYHnQQzGLMZKptZgvMIWwOVMJjfOOZ1LGmj3DXmINaJ1/NbcZce32so= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719824899; c=relaxed/simple; bh=of45miHqg0zIGr0XeG9+2B9Ss/L/V39dvk7XO47i/aA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gkrJdszBM2Q3HcIFErkAg3H0o/M0vg66gGpU2aRPzmYDgkwuWHnxsoDLMR8UYg1muqpIDLGQ3P5TXLuTzCUJxX2ofTaHwPYvZvk4+I5Z9/vBjYHxa6hBhqwNFRcV6IKyJbWTNOv/77wDCinQUmixV2jS23lEo2hp5rPbZ9Y3Yyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=erc6pSTO; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="erc6pSTO" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4618vXFm022323; Mon, 1 Jul 2024 02:08:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=g DL/RyI33NOmI5rhwYexOQYakJ9UWsxRPe4WpaynY+I=; b=erc6pSTOyZOb0myuA dhQt2EmjJ7wmyrxz9XnwV65V/nBab3LjEci4x3yFgEUZ2Z0Sg5Hu54XMzTNym6aU /Cw2P3TGNv3lg0deos27sjHHGvkgHBvgYpblTu9YDEUgkJcYgd64EJIu/bM+exKr WAnvad0dl5TiQLoT73T195zUyn9xurlxStdksMMhjpUY1Prz1PPPpdaJhycdj8rK gyk9qlkB1igVdAEyKej/5TZmpMuEyNY7ra6Vk3nAqjglKE7RboOXWWpU+JXq4AEd aAhCU3bl+2Nio371HNxfZ7nhm6wnaNz43solU6UqdOJawzkV43V649zDwsP1j1qk 5Y3PA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 403sdcg1nh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 01 Jul 2024 02:08:09 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 1 Jul 2024 02:08:08 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 02:08:08 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id DC7B53F7044; Mon, 1 Jul 2024 02:08:04 -0700 (PDT) From: Srujana Challa To: , CC: , , , , , , , , , , Kiran Kumar K Subject: [PATCH net,4/6] octeontx2-af: Fix issue with IPv6 ext match for RSS Date: Mon, 1 Jul 2024 14:37:44 +0530 Message-ID: <20240701090746.2171565-5-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240701090746.2171565-1-schalla@marvell.com> References: <20240701090746.2171565-1-schalla@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: OQQ7s3mCRw_n1BUg-qwo9I7BorsnOdb6 X-Proofpoint-ORIG-GUID: OQQ7s3mCRw_n1BUg-qwo9I7BorsnOdb6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_07,2024-06-28_01,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Kiran Kumar K While performing RSS based on IPv6, extension ltype is not being considered. This will be problem for fragmented packets or packets with extension header. Adding changes to match IPv6 ext header along with IPv6 ltype. Fixes: 41a7aa7b800d ("octeontx2-af: NIX Rx flowkey configuration for RSS") Signed-off-by: Kiran Kumar K --- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 00af8888e329..bf5c9cc3df87 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -3990,7 +3990,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) field->bytesm1 = 15; /* DIP,16 bytes */ } } - field->ltype_mask = 0xF; /* Match only IPv6 */ + field->ltype_mask = 0xE; /* Match IPv6 and IPv6_ext */ break; case NIX_FLOW_KEY_TYPE_TCP: case NIX_FLOW_KEY_TYPE_UDP: From patchwork Mon Jul 1 09:07:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 13717699 X-Patchwork-Delegate: kuba@kernel.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D81AF85947; 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Mon, 01 Jul 2024 02:08:14 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 1 Jul 2024 02:08:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 02:08:13 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 363B63F7044; Mon, 1 Jul 2024 02:08:08 -0700 (PDT) From: Srujana Challa To: , CC: , , , , , , , , , , Satheesh Paul Subject: [PATCH net,5/6] octeontx2-af: fix issue with IPv4 match for RSS Date: Mon, 1 Jul 2024 14:37:45 +0530 Message-ID: <20240701090746.2171565-6-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240701090746.2171565-1-schalla@marvell.com> References: <20240701090746.2171565-1-schalla@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: SiqYG2SB2TzLbhX70U1UcgXoBOhCcKyn X-Proofpoint-ORIG-GUID: SiqYG2SB2TzLbhX70U1UcgXoBOhCcKyn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_07,2024-06-28_01,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Satheesh Paul While performing RSS based on IPv4, packets with IPv4 options are not being considered. Adding changes to match both plain IPv4 and IPv4 with option header. Fixes: 41a7aa7b800d ("octeontx2-af: NIX Rx flowkey configuration for RSS") Signed-off-by: Satheesh Paul --- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index bf5c9cc3df87..da090d8b9046 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -3933,7 +3933,7 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) field->hdr_offset = 9; /* offset */ field->bytesm1 = 0; /* 1 byte */ field->ltype_match = NPC_LT_LC_IP; - field->ltype_mask = 0xF; + field->ltype_mask = 0xE; break; case NIX_FLOW_KEY_TYPE_IPV4: case NIX_FLOW_KEY_TYPE_INNR_IPV4: @@ -3961,7 +3961,10 @@ static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) } } - field->ltype_mask = 0xF; /* Match only IPv4 */ + /* Match only IPv4; both NPC_LT_LC_IP and + * NPC_LT_LC_IP_OPT + */ + field->ltype_mask = 0xE; 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Mon, 1 Jul 2024 02:08:17 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 1 Jul 2024 02:08:17 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 81AA73F705A; Mon, 1 Jul 2024 02:08:13 -0700 (PDT) From: Srujana Challa To: , CC: , , , , , , , , , , Michal Mazur Subject: [PATCH net,6/6] octeontx2-af: fix detection of IP layer Date: Mon, 1 Jul 2024 14:37:46 +0530 Message-ID: <20240701090746.2171565-7-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240701090746.2171565-1-schalla@marvell.com> References: <20240701090746.2171565-1-schalla@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 2eGvdFN0LGZ17lvV4gnLzRQ4e6X2Gm3H X-Proofpoint-GUID: 2eGvdFN0LGZ17lvV4gnLzRQ4e6X2Gm3H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_07,2024-06-28_01,2024-05-17_01 X-Patchwork-Delegate: kuba@kernel.org From: Michal Mazur Checksum and length checks are not enabled for IPv4 header with options and IPv6 with extension headers. To fix this a change in enum npc_kpu_lc_ltype is required which will allow adjustment of LTYPE_MASK to detect all types of IP headers. Fixes: 21e6699e5cd6 ("octeontx2-af: Add NPC KPU profile") Signed-off-by: Michal Mazur --- drivers/net/ethernet/marvell/octeontx2/af/npc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/npc.h index d883157393ea..6c3aca6f278d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h @@ -63,8 +63,13 @@ enum npc_kpu_lb_ltype { NPC_LT_LB_CUSTOM1 = 0xF, }; +/* Don't modify ltypes up to IP6_EXT, otherwise length and checksum of IP + * headers may not be checked correctly. IPv4 ltypes and IPv6 ltypes must + * differ only at bit 0 so mask 0xE can be used to detect extended headers. + */ enum npc_kpu_lc_ltype { - NPC_LT_LC_IP = 1, + NPC_LT_LC_PTP = 1, + NPC_LT_LC_IP, NPC_LT_LC_IP_OPT, NPC_LT_LC_IP6, NPC_LT_LC_IP6_EXT, @@ -72,7 +77,6 @@ enum npc_kpu_lc_ltype { NPC_LT_LC_RARP, NPC_LT_LC_MPLS, NPC_LT_LC_NSH, - NPC_LT_LC_PTP, NPC_LT_LC_FCOE, NPC_LT_LC_NGIO, NPC_LT_LC_CUSTOM0 = 0xE,