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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7516310768sm269306866b.218.2024.07.02.04.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 04:01:41 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 778ebf9e-3862-11ef-92e8-0d9d20120eaa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719918102; x=1720522902; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hqKpyboE7tWF7PWd9CeoA+EhM5ccJlbOY2elCP5bC/s=; b=eDKl2TfKYuNYR3VkgCIG/TlcMlGiaxVmlAffgk233KnErFKiKTAGVWfbsv+1o/Zlcc 02X7c1MTsYiAeyahRy3g1twZd9IrbQ0Fpl5xafmJ1e3o0JkKR623pP1lj/QY3/1/En0R KAK4KomBgvSwJdRA692YLGqmRxIma9WWxWs/CCAVPdXh0cMkYpY+OyxlHZpBhpj50SXx tweWqlUTJw6/XitD7ZXGMqLsPu36arUAdNSGGFdZ6VMByjGNivjzGIK1ltYfsltKaaTg I9f3njKTerrzAvFcNemmcwrtOAFa72iDJdWKFijIPyLoVa2RKCIF/WQtWLeTW4BDLoYJ OFtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719918102; x=1720522902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hqKpyboE7tWF7PWd9CeoA+EhM5ccJlbOY2elCP5bC/s=; b=uhiFKxnDJLKbDid97eH27qmB1yJemhqFbtAAhnvxzhZb6fE3zNXBSSZH6CDBh2+D1o Xn6WEJJTIa5TMGmJqBMVblxdBFObU8El7ERHsYtXxUlCksMlB66JXFq/GWDi1ehHLX93 4wCdfKhOHWzXJ3HeQi8wj6zw8QD747t9wZFzXbf5Eln6zvo532mWAovK/rTeDNj7I5U9 jBfIla75MpHG2HBJeh9s6p5icoJMzSF5vTZYuukJkBSQRwj2qJVD0E53E6voIMUOERKd G4bop1mN78fCsmyTkqvchQGKdIdfYKEX15o+iS7WDuiVDdzH6uJ0OCAPVKD1MMRB3pVO iUWQ== X-Gm-Message-State: AOJu0YydP7BLoiR9CsofGCbaj+hB2aAsieMyYuTbiWFWd7W4InxY+ZNW nvdQh7n+cFND/EgXemuG3f0NrOeKT6mL+dj9zcavlUEC4Cg9OBPd9nPQY2wu X-Google-Smtp-Source: AGHT+IG8tPIWzmPpWKtRBU14f4lxe94t3/47nhTs//yLUzC01QZ4fu+LclromPDoQq9XdS/FnnUnIA== X-Received: by 2002:a05:6512:1246:b0:52c:8024:1db with SMTP id 2adb3069b0e04-52e827364d9mr6402711e87.63.1719918101862; Tue, 02 Jul 2024 04:01:41 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Jan Beulich , Shawn Anastasio , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v14 1/9] xen: introduce generic non-atomic test_*bit() Date: Tue, 2 Jul 2024 13:01:28 +0200 Message-ID: <2f60d1fd7b3ac7d603486ce03a112d58352bf16d.1719917348.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 The following generic functions were introduced: * test_bit * generic__test_and_set_bit * generic__test_and_clear_bit * generic__test_and_change_bit These functions and macros can be useful for architectures that don't have corresponding arch-specific instructions. Also, the patch introduces the following generics which are used by the functions mentioned above: * BITOP_BITS_PER_WORD * BITOP_MASK * BITOP_WORD * BITOP_TYPE The following approach was chosen for generic*() and arch*() bit operation functions: If the bit operation function that is going to be generic starts with the prefix "__", then the corresponding generic/arch function will also contain the "__" prefix. For example: * test_bit() will be defined using arch_test_bit() and generic_test_bit(). * __test_and_set_bit() will be defined using arch__test_and_set_bit() and generic__test_and_set_bit(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich Reviewed-by: Michal Orzel --- Changes in V14: - Nothing changed. Only Rebase. --- Changes in V13: - add Reviewed-by: Jan Beulich --- Changes in V12: - revert change of moving the definition of BITS_PER_BYTE from /bitops.h to xen/bitops.h. ( a separate patch will be provided to put BITS_PER_BYTE to proper place ) - drop comments on top of generic_*() functions and update the comments above __test_*() and test_bit(). - update how static inline __test_*() are defined ( drop pointless fallback #define ) and test_bit(). - drop the footer after Signed-off-by. Changes in V11: - fix identation in generic_test_bit() function. - move definition of BITS_PER_BYTE from /bitops.h to xen/bitops.h - drop the changes in arm64/livepatch.c. - update the the comments on top of functions: generic__test_and_set_bit(), generic__test_and_clear_bit(), generic__test_and_change_bit(), generic_test_bit(). - Update footer after Signed-off section. - Rebase the patch on top of staging branch, so it can be merged when necessary approves will be given. - add Reviewed-by: Jan Beulich . --- Changes in V10: - update the commit message. ( re-order paragraphs and add explanation usage of prefix "__" in bit operation function names ) - add parentheses around the whole expression of bitop_bad_size() macros. - move macros bitop_bad_size() above asm/bitops.h as it is not arch-specific anymore and there is no need for overriding it. - drop macros check_bitop_size() and use "if ( bitop_bad_size(addr) ) __bitop_bad_size();" implictly where it is needed. - in use 'int' as a first parameter for __test_and_*(), generic__test_and_*() to be consistent with how the mentioned functions were declared in the original per-arch functions. - add 'const' to p variable in generic_test_bit(). - move definition of BITOP_BITS_PER_WORD and bitop_uint_t to xen/bitops.h as we don't allow for arch overrides these definitions anymore. --- Changes in V9: - move up xen/bitops.h in ppc/asm/page.h. - update defintion of arch_check_bitop_size. And drop correspondent macros from x86/asm/bitops.h - drop parentheses in generic__test_and_set_bit() for definition of local variable p. - fix indentation inside #ifndef BITOP_TYPE...#endif - update the commit message. --- Changes in V8: - drop __pure for function which uses volatile. - drop unnessary () in generic__test_and_change_bit() for addr casting. - update prototype of generic_test_bit() and test_bit(): now it returns bool instead of int. - update generic_test_bit() to use BITOP_MASK(). - Deal with fls{l} changes: it should be in the patch with introduced generic fls{l}. - add a footer with explanation of dependency on an uncommitted patch after Signed-off. - abstract bitop_size(). - move BITOP_TYPE define to . --- Changes in V7: - move everything to xen/bitops.h to follow the same approach for all generic bit ops. - put together BITOP_BITS_PER_WORD and bitops_uint_t. - make BITOP_MASK more generic. - drop #ifdef ... #endif around BITOP_MASK, BITOP_WORD as they are generic enough. - drop "_" for generic__{test_and_set_bit,...}(). - drop " != 0" for functions which return bool. - add volatile during the cast for generic__{...}(). - update the commit message. - update arch related code to follow the proposed generic approach. --- Changes in V6: - Nothing changed ( only rebase ) --- Changes in V5: - new patch --- xen/arch/arm/include/asm/bitops.h | 69 ----------- xen/arch/ppc/include/asm/bitops.h | 54 --------- xen/arch/ppc/include/asm/page.h | 2 +- xen/arch/ppc/mm-radix.c | 2 +- xen/arch/x86/include/asm/bitops.h | 31 ++--- xen/include/xen/bitops.h | 182 ++++++++++++++++++++++++++++++ 6 files changed, 193 insertions(+), 147 deletions(-) diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/bitops.h index 8f4bdc09d1..db23d7edc3 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -22,11 +22,6 @@ #define __set_bit(n,p) set_bit(n,p) #define __clear_bit(n,p) clear_bit(n,p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) -#define BITS_PER_BYTE 8 - #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) @@ -76,70 +71,6 @@ bool test_and_change_bit_timeout(int nr, volatile void *p, bool clear_mask16_timeout(uint16_t mask, volatile void *p, unsigned int max_try); -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = (const volatile unsigned int *)addr; - return 1UL & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); -} - #define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) #define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) #define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0) diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/bitops.h index 8119b5ace8..ee0e58e2e8 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -15,11 +15,6 @@ #define __set_bit(n, p) set_bit(n, p) #define __clear_bit(n, p) clear_bit(n, p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) -#define BITS_PER_BYTE 8 - /* PPC bit number conversion */ #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) @@ -69,17 +64,6 @@ static inline void clear_bit(int nr, volatile void *addr) clear_bits(BITOP_MASK(nr), (volatile unsigned int *)addr + BITOP_WORD(nr)); } -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = addr; - return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); -} - static inline unsigned int test_and_clear_bits( unsigned int mask, volatile unsigned int *p) @@ -133,44 +117,6 @@ static inline int test_and_set_bit(unsigned int nr, volatile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) != 0; } -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - #define arch_ffs(x) ((x) ? 1 + __builtin_ctz(x) : 0) #define arch_ffsl(x) ((x) ? 1 + __builtin_ctzl(x) : 0) #define arch_fls(x) ((x) ? 32 - __builtin_clz(x) : 0) diff --git a/xen/arch/ppc/include/asm/page.h b/xen/arch/ppc/include/asm/page.h index 890e285051..6d4cd2611c 100644 --- a/xen/arch/ppc/include/asm/page.h +++ b/xen/arch/ppc/include/asm/page.h @@ -2,9 +2,9 @@ #ifndef _ASM_PPC_PAGE_H #define _ASM_PPC_PAGE_H +#include #include -#include #include #define PDE_VALID PPC_BIT(0) diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index ab5a10695c..9055730997 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index aa71542e7b..f9aa60111f 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -19,9 +19,6 @@ #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) -extern void __bitop_bad_size(void); -#define bitop_bad_size(addr) (sizeof(*(addr)) < 4) - /** * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -175,7 +172,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) }) /** - * __test_and_set_bit - Set a bit and return its old value + * arch__test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -183,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, void *addr) +static inline int arch__test_and_set_bit(int nr, volatile void *addr) { int oldbit; @@ -194,10 +191,7 @@ static inline int __test_and_set_bit(int nr, void *addr) return oldbit; } -#define __test_and_set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_set_bit(nr, addr); \ -}) +#define arch__test_and_set_bit arch__test_and_set_bit /** * test_and_clear_bit - Clear a bit and return its old value @@ -224,7 +218,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) }) /** - * __test_and_clear_bit - Clear a bit and return its old value + * arch__test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -232,7 +226,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, void *addr) +static inline int arch__test_and_clear_bit(int nr, volatile void *addr) { int oldbit; @@ -243,13 +237,10 @@ static inline int __test_and_clear_bit(int nr, void *addr) return oldbit; } -#define __test_and_clear_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_clear_bit(nr, addr); \ -}) +#define arch__test_and_clear_bit arch__test_and_clear_bit /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, void *addr) +static inline int arch__test_and_change_bit(int nr, volatile void *addr) { int oldbit; @@ -260,10 +251,7 @@ static inline int __test_and_change_bit(int nr, void *addr) return oldbit; } -#define __test_and_change_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_change_bit(nr, addr); \ -}) +#define arch__test_and_change_bit arch__test_and_change_bit /** * test_and_change_bit - Change a bit and return its new value @@ -307,8 +295,7 @@ static inline int variable_test_bit(int nr, const volatile void *addr) return oldbit; } -#define test_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ +#define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ constant_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 6a5e28730a..cc09d273c9 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -4,6 +4,19 @@ #include #include +#define BITOP_BITS_PER_WORD 32 +typedef uint32_t bitop_uint_t; + +#define BITOP_MASK(nr) ((bitop_uint_t)1 << ((nr) % BITOP_BITS_PER_WORD)) + +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) + +#define BITS_PER_BYTE 8 + +extern void __bitop_bad_size(void); + +#define bitop_bad_size(addr) (sizeof(*(addr)) < sizeof(bitop_uint_t)) + #include /* @@ -24,6 +37,175 @@ unsigned int __pure generic_ffsl(unsigned long x); unsigned int __pure generic_flsl(unsigned long x); +/** + * generic__test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_set_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old | mask; + return (old & mask); +} + +/** + * generic__test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_clear_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old & ~mask; + return (old & mask); +} + +/** + * generic__test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_change_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old ^ mask; + return (old & mask); +} + +/** + * generic_test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool generic_test_bit(int nr, const volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + const volatile bitop_uint_t *p = + (const volatile bitop_uint_t *)addr + BITOP_WORD(nr); + + return (*p & mask); +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_set_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_set_bit +#define arch__test_and_set_bit generic__test_and_set_bit +#endif + + return arch__test_and_set_bit(nr, addr); +} +#define __test_and_set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_set_bit(nr, addr); \ +}) + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_clear_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_clear_bit +#define arch__test_and_clear_bit generic__test_and_clear_bit +#endif + + return arch__test_and_clear_bit(nr, addr); +} +#define __test_and_clear_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_clear_bit(nr, addr); \ +}) + +/** + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_change_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_change_bit +#define arch__test_and_change_bit generic__test_and_change_bit +#endif + + return arch__test_and_change_bit(nr, addr); +} +#define __test_and_change_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_change_bit(nr, addr); \ +}) + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool test_bit(int nr, const volatile void *addr) +{ +#ifndef arch_test_bit +#define arch_test_bit generic_test_bit +#endif + + return arch_test_bit(nr, addr); +} +#define test_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + test_bit(nr, addr); \ +}) + static always_inline __pure unsigned int ffs(unsigned int x) { if ( __builtin_constant_p(x) ) From patchwork Tue Jul 2 11:01:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C09A8C3065E for ; Tue, 2 Jul 2024 11:02:04 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752282.1160466 (Exim 4.92) (envelope-from ) id 1sObGd-0000kQ-2t; Tue, 02 Jul 2024 11:01:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752282.1160466; Tue, 02 Jul 2024 11:01:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGc-0000ig-VI; Tue, 02 Jul 2024 11:01:46 +0000 Received: by outflank-mailman (input) for mailman id 752282; Tue, 02 Jul 2024 11:01:46 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGc-0000Yf-80 for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:46 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 780f8084-3862-11ef-aaf1-7f3abd7486c0; Tue, 02 Jul 2024 13:01:44 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a724958f118so488316966b.0 for ; Tue, 02 Jul 2024 04:01:44 -0700 (PDT) Received: from fedora.. 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Only rebase was done. --- Changes in V10: - update the error message BITS_PER_LONG -> BITOP_BITS_PER_WORD --- Changes in V9: - add Acked-by: Jan Beulich - drop redefinition of bitop_uint_t in asm/types.h as some operation in Xen common code expects to work with 32-bit quantities. - s/BITS_PER_LONG/BITOP_BITS_PER_WORD in asm/bitops.h around __AMO() macros. --- Changes in V8: - define bitop_uint_t in after the changes in patch related to introduction of "introduce generic non-atomic test_*bit()". - drop duplicated __set_bit() and __clear_bit(). - drop duplicated comment: /* Based on linux/arch/include/asm/bitops.h */. - update type of res and mask in test_and_op_bit_ord(): unsigned long -> bitop_uint_t. - drop 1 padding blank in test_and_op_bit_ord(). - update definition of test_and_set_bit(),test_and_clear_bit(),test_and_change_bit: change return type to bool. - change addr argument type of test_and_change_bit(): unsigned long * -> void *. - move test_and_change_bit() closer to other test_and-s function. - Code style fixes: tabs -> space. - s/#undef __op_bit/#undef op_bit. - update the commit message: delete information about generic-non-atomic.h changes as now it is a separate patch. --- Changes in V7: - Update the commit message. - Drop "__" for __op_bit and __op_bit_ord as they are atomic. - add comment above __set_bit and __clear_bit about why they are defined as atomic. - align bitops_uint_t with __AMO(). - make changes after generic non-atomic test_*bit() were changed. - s/__asm__ __volatile__/asm volatile --- Changes in V6: - rebase clean ups were done: drop unused asm-generic includes --- Changes in V5: - new patch --- xen/arch/riscv/include/asm/bitops.h | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..7f7af3fda1 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#if BITOP_BITS_PER_WORD == 64 +#define __AMO(op) "amo" #op ".d" +#elif BITOP_BITS_PER_WORD == 32 +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITOP_BITS_PER_WORD" +#endif + +/* Based on linux/arch/include/asm/bitops.h */ + +/* + * Non-atomic bit manipulation. + * + * Implemented using atomics to be interrupt safe. Could alternatively + * implement with local interrupt masking. + */ +#define __set_bit(n, p) set_bit(n, p) +#define __clear_bit(n, p) clear_bit(n, p) + +#define test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + bitop_uint_t res, mask; \ + mask = BITOP_MASK(nr); \ + asm volatile ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(mask)) \ + : "memory"); \ + ((res & mask) != 0); \ +}) + +#define op_bit_ord(op, mod, nr, addr, ord) \ + asm volatile ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define test_and_op_bit(op, mod, nr, addr) \ + test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define op_bit(op, mod, nr, addr) \ + op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define NOP(x) (x) +#define NOT(x) (~(x)) + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + */ +static inline bool test_and_set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(or, NOP, nr, addr); +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + */ +static inline bool test_and_clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(and, NOT, nr, addr); +} + +/** + * test_and_change_bit - Toggle (change) a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline bool test_and_change_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(xor, NOP, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(or, NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(and, NOT, nr, addr); +} + +#undef test_and_op_bit +#undef op_bit +#undef NOP +#undef NOT +#undef __AMO + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Tue Jul 2 11:01:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 376A5C30658 for ; Tue, 2 Jul 2024 11:02:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752283.1160484 (Exim 4.92) (envelope-from ) id 1sObGf-0001Hj-D6; Tue, 02 Jul 2024 11:01:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752283.1160484; Tue, 02 Jul 2024 11:01:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGf-0001Hc-AD; Tue, 02 Jul 2024 11:01:49 +0000 Received: by outflank-mailman (input) for mailman id 752283; Tue, 02 Jul 2024 11:01:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGd-0000Yf-Mv for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:47 +0000 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [2a00:1450:4864:20::636]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7881c0cf-3862-11ef-aaf1-7f3abd7486c0; Tue, 02 Jul 2024 13:01:45 +0200 (CEST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a7523f0870cso274018666b.3 for ; Tue, 02 Jul 2024 04:01:45 -0700 (PDT) Received: from fedora.. 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Tue, 02 Jul 2024 04:01:43 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v14 3/9] xen/riscv: add minimal stuff to mm.h to build full Xen Date: Tue, 2 Jul 2024 13:01:30 +0200 Message-ID: <297d508d639a766c2c47c4d0f554d9d2597ebfb7.1719917348.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V14: - drop cast in defintion of page_to_mfn(pg). - reword first change in "Changes in V13". --- Changes in V13: - redefine page_to_mfn() and mfn_to_page(). - add inclusion of after rebasing on top of staging. --- Changes in V8-V12: - Nothing changed only rebase. --- Changes in V7: - update argument type of maddr_to_virt() function: unsigned long -> paddr_t - rename argument of PFN_ORDER(): pfn -> pg. - add Acked-by: Jan Beulich --- Changes in V6: - drop __virt_to_maddr() ( transform to macro ) and __maddr_to_virt ( rename to maddr_to_virt ). - parenthesize va in definition of vmap_to_mfn(). - Code style fixes. --- Changes in V5: - update the comment around "struct domain *domain;" : zero -> NULL - fix ident. for unsigned long val; - put page_to_virt() and virt_to_page() close to each other. - drop unnessary leading underscore - drop a space before the comment: /* Count of uses of this frame as its current type. */ - drop comment about a page 'not as a shadow'. it is not necessary for RISC-V --- Changes in V4: - update an argument name of PFN_ORDERN macros. - drop pad at the end of 'struct page_info'. - Change message -> subject in "Changes in V3" - delete duplicated macros from riscv/mm.h - fix identation in struct page_info - align comment for PGC_ macros - update definitions of domain_set_alloc_bitsize() and domain_clamp_alloc_bitsize() - drop unnessary comments. - s/BUG/BUG_ON("...") - define __virt_to_maddr, __maddr_to_virt as stubs - add inclusion of xen/mm-frame.h for mfn_x and others - include "xen/mm.h" instead of "asm/mm.h" to fix compilation issues: In file included from arch/riscv/setup.c:7: ./arch/riscv/include/asm/mm.h:60:28: error: field 'list' has incomplete type 60 | struct page_list_entry list; | ^~~~ ./arch/riscv/include/asm/mm.h:81:43: error: 'MAX_ORDER' undeclared here (not in a function) 81 | unsigned long first_dirty:MAX_ORDER + 1; | ^~~~~~~~~ ./arch/riscv/include/asm/mm.h:81:31: error: bit-field 'first_dirty' width not an integer constant 81 | unsigned long first_dirty:MAX_ORDER + 1; - Define __virt_to_mfn() and __mfn_to_virt() using maddr_to_mfn() and mfn_to_maddr(). --- Changes in V3: - update the commit title - introduce DIRECTMAP_VIRT_START. - drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe in [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen - code style fixes. - drop get_page_nr and put_page_nr as they don't need for time being - drop CONFIG_STATIC_MEMORY related things - code style fixes --- Changes in V2: - define stub for arch_get_dma_bitsize(void) --- xen/arch/riscv/include/asm/mm.h | 235 ++++++++++++++++++++++++++++++++ xen/arch/riscv/mm.c | 2 +- xen/arch/riscv/setup.c | 2 +- 3 files changed, 237 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 07c7a0abba..25af9e1aaa 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,11 +3,241 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H +#include +#include +#include +#include +#include + #include #define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)(va))) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +static inline void *maddr_to_virt(paddr_t ma) +{ + BUG_ON("unimplemented"); + return NULL; +} + +#define virt_to_maddr(va) ({ BUG_ON("unimplemented"); 0; }) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) mfn_x(maddr_to_mfn(virt_to_maddr(va))) +#define __mfn_to_virt(mfn) maddr_to_virt(mfn_to_maddr(_mfn(mfn))) + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + } u; + + union { + /* Page is in use */ + struct { + /* Owner of this page (NULL if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) (frame_table + mfn_x(mfn)) +#define page_to_mfn(pg) _mfn((pg) - frame_table) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +#define set_gpfn_from_mfn(mfn, pfn) do { (void)(mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (PAGE_SHIFT + VPN_BITS) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + +/* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) + +/* + * Page needs to be scrubbed. Since this bit can only be set on a page that is + * free (i.e. in PGC_state_free) we can reuse PGC_allocated bit. + */ +#define _PGC_need_scrub _PGC_allocated +#define PGC_need_scrub PGC_allocated + +/* Cleared when the owning guest 'frees' this page. */ +#define _PGC_allocated PG_shift(1) +#define PGC_allocated PG_mask(1, 1) +/* Page is Xen heap? */ +#define _PGC_xen_heap PG_shift(2) +#define PGC_xen_heap PG_mask(1, 2) +/* Page is broken? */ +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +/* Mutually-exclusive page states: { inuse, offlining, offlined, free }. */ +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr((vaddr_t)_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(p) (p)->v.inuse.domain +#define page_set_owner(p, d) ((p)->v.inuse.domain = (d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void)(mfn); 0; }) + +#define domain_set_alloc_bitsize(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, b) ((void)(d), (b)) + +#define PFN_ORDER(pg) ((pg)->v.free.order) + extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); @@ -20,4 +250,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 3ebaf6da01..ae381e9581 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -4,13 +4,13 @@ #include #include #include +#include #include #include #include #include #include -#include #include #include diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..98a94c4c48 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,9 @@ #include #include +#include #include -#include /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] From patchwork Tue Jul 2 11:01:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27466C31D97 for ; Tue, 2 Jul 2024 11:02:06 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752284.1160495 (Exim 4.92) (envelope-from ) id 1sObGg-0001XO-Kp; Tue, 02 Jul 2024 11:01:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752284.1160495; Tue, 02 Jul 2024 11:01:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGg-0001X9-H5; Tue, 02 Jul 2024 11:01:50 +0000 Received: by outflank-mailman (input) for mailman id 752284; Tue, 02 Jul 2024 11:01:48 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGe-0000Yf-9Z for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:48 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7932dc43-3862-11ef-aaf1-7f3abd7486c0; Tue, 02 Jul 2024 13:01:46 +0200 (CEST) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a728f74c23dso456865166b.1 for ; Tue, 02 Jul 2024 04:01:46 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7516310768sm269306866b.218.2024.07.02.04.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 04:01:44 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7932dc43-3862-11ef-aaf1-7f3abd7486c0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719918106; x=1720522906; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dpvlbHk8NcYflQScXvllWu7mq9hw8lJB3mPUY5Yk6zc=; b=BI6pYfhN3KgD7TAj2LhLaqJbT7Kg3SoYxMb0VarwNIdXH3Oximc70acWiEQY/BhG+S BWxlKYtkdW0QRpLb8jSGgDg4D3ogdCH1zuJ3GLBhVS+w/6wiEeu70lPqxBz2QkRRVzQp iyfuyDA49HkPJimN1dPv+uqvP/TSfpJq7epkHHKIbQgwh/2fRpQK3PG60j5FBbbP8WQ8 mzQfqaLsNkF8viHFtfeGziMeRLjwYdZqxibbxOccgb0LZX9jfAqfkAvgeK9khU1wRo/7 th3+O2z8LpRqjDvMo+rh4mO+vJo7wQJ51MMSLS3mjmlzLUEondsX5EmMyP4d4Z+c7Szw dsGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719918106; x=1720522906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dpvlbHk8NcYflQScXvllWu7mq9hw8lJB3mPUY5Yk6zc=; b=oxY8GYoNopQR9JCeVjizEDxgYbXxt2UW+VhHYBknvwD76fzIDN0gRbNixSPjdQN4CP mL9uK3cCCsXSmb+Wg4zltuLWIAWtOjJd5TeTx4iMQEzq4KAdTew33wtNe6u5SLJ0X8Uw 4YY7+ta7jL+3ilWE3EE9P13OGTlq17F3S7XM26lyIuaHc+8Wu32FE9wtvQaU8sFlCnN2 Ppf3wPD3iqj9zfK85kN4YKNjwwz8uaAH9Yc3oo7P3o4dwUBb17oaBIuVoaj2M3v70drj Z0ShNrWPrd8fJ+aCw5BWQ+KSqp21U6r93noYVP+BcjmWhXybwQiCUpfxOsiu4ynWAFai iZDw== X-Gm-Message-State: AOJu0Yx25qBE0M2n5E7dMNTrJqh9j0oNBmIXHcM9hWR73EB/k3aCB+kY dx3pga09Ns2fizk2lBQXygjCmqncneH0xw3Kf7r6YDFJtPV5nXxsXPoQEUQU X-Google-Smtp-Source: AGHT+IHxYo5fAAXQt6h6399DHbHYkuUFBNXSmQK+K1+cZsl6cdcxfcdie2sDeajGYULsonTn6GNqXA== X-Received: by 2002:a17:906:30ce:b0:a6f:59dc:4ed2 with SMTP id a640c23a62f3a-a751441f068mr541946466b.12.1719918105346; Tue, 02 Jul 2024 04:01:45 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v14 4/9] xen/riscv: add minimal amount of stubs to build full Xen Date: Tue, 2 Jul 2024 13:01:31 +0200 Message-ID: <132066f2926716a759d4e13f0359c10173d09f71.1719917348.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V14: - Nothing changed. Only rebase. --- Changes in V13: - drop no_irq_type because of the patch series ( [PATCH for-4.19 0/2] arch/irq: Untangle no_irq_type ) which was merged to staging. - Drop unnessary stubs after rebasing on top of staging ( [PATCH for-4.19 0/2] arch/irq: Untangle no_irq_type ) - implement get_upper_mfn_bound() as BUG_ON("unimplemented") to not introduce max_page which will be dropped in the next patch ( xen/riscv: enable full Xen build ) - remove trainling space in stubs.c after the comment /* guest_access.h */ - drop frametable_base_pdx - drop frametable_virt_end --- Changes in V7-V12: - Only rebase was done. --- Changes in V6: - update the commit in stubs.c around /* ... common/irq.c ... */ - add Acked-by: Jan Beulich --- Changes in V5: - drop unrelated changes - assert_failed("unimplmented...") change to BUG_ON() --- Changes in V4: - added new stubs which are necessary for compilation after rebase: __cpu_up(), __cpu_disable(), __cpu_die() from smpboot.c - back changes related to printk() in early_printk() as they should be removed in the next patch to avoid compilation error. - update definition of cpu_khz: __read_mostly -> __ro_after_init. - drop vm_event_reset_vmtrace(). It is defibed in asm-generic/vm_event.h. - move vm_event_*() functions from stubs.c to riscv/vm_event.c. - s/BUG/BUG_ON("unimplemented") in stubs.c - back irq_actor_none() and irq_actor_none() as common/irq.c isn't compiled at this moment, so this function are needed to avoid compilation error. - defined max_page to avoid compilation error, it will be removed as soon as common/page_alloc.c will be compiled. --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __ro_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declaration instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/mm.c | 41 ++++ xen/arch/riscv/setup.c | 8 + xen/arch/riscv/stubs.c | 418 ++++++++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 +++ 5 files changed, 493 insertions(+) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1ed1a8369b..60afbc0ad9 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o +obj-y += stubs.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index ae381e9581..7d09e781bf 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -294,3 +295,43 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_shared_mem_info(void) +{ + BUG_ON("unimplemented"); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG_ON("unimplemented"); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG_ON("unimplemented"); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG_ON("unimplemented"); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG_ON("unimplemented"); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 98a94c4c48..8bb5bdb2ae 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include + #include +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + BUG_ON("unimplemented"); +} + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..b67d99729f --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,418 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* time.c */ + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG_ON("unimplemented"); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG_ON("unimplemented"); +} + +void send_timer_event(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG_ON("unimplemented"); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG_ON("unimplemented"); +} + +void machine_halt(void) +{ + BUG_ON("unimplemented"); +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG_ON("unimplemented"); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG_ON("unimplemented"); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG_ON("unimplemented"); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG_ON("unimplemented"); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG_ON("unimplemented"); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void irq_ack_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG_ON("unimplemented"); +} + +void continue_running(struct vcpu *same) +{ + BUG_ON("unimplemented"); +} + +void sync_local_execstate(void) +{ + BUG_ON("unimplemented"); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void startup_cpu_idle_loop(void) +{ + BUG_ON("unimplemented"); +} + +void free_domain_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_pause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +struct domain *alloc_domain_struct(void) +{ + BUG_ON("unimplemented"); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG_ON("unimplemented"); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG_ON("unimplemented"); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG_ON("unimplemented"); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG_ON("unimplemented"); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG_ON("unimplemented"); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG_ON("unimplemented"); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG_ON("unimplemented"); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */ + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* smpboot.c */ + +int __cpu_up(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +void __cpu_disable(void) +{ + BUG_ON("unimplemented"); +} + +void __cpu_die(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +unsigned long get_upper_mfn_bound(void) +{ + BUG_ON("unimplemented"); +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..5415cf8d90 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + BUG_ON("unimplemented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + BUG_ON("unimplemented"); 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7516310768sm269306866b.218.2024.07.02.04.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 04:01:46 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7a28d4cc-3862-11ef-92e8-0d9d20120eaa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719918107; x=1720522907; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JRZ/nCXNdfp/8aMKgDc8v2QqVIkEno6CGrBauxQBWcg=; b=BR/DC2Ss5mz5K27Vs85C/uhuitBeB5v1lkG8+j3XJ2iNMdUNkUvZ30jCukqpc5gzTU K82DN3F+fhruuDK55ye9z/b6N+FVDikUqR6EgPVsTtfpBa/d5W5QVMVN6+XWFM/XmAW+ BzWFko2OBYz5hyu4exmNu9/ByNIPVHk2pUECTIfrFuDiOkEPiclwnQ8MRgLVuzhu/Dke VlrLClFm6AoCIuGYZlwWkKPlJnMJNg5BYj03wfrUOQIH23b4hw6/MLEJoMYB4BERTeqX b8tIZOTqMszL0TlXiVM9gy6uvZvg9USSWV4afefaT78GtAkaD2Qj8YiFEdhvlgMfsaBU 3Zlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719918107; x=1720522907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JRZ/nCXNdfp/8aMKgDc8v2QqVIkEno6CGrBauxQBWcg=; b=oPa+5nWgAIXyp9Ywu7kTIeYv980Iomb5FKkn6zZPgS6IDXoWKRLYm0wF/nepZNrgtj QumsdgG2q4BNiYosBuUB9nekuC9iIkkJH+7hEwt7S75BEBru0C0ys732bdUFvmA7iRaR uhq9R5EVSKSIauFRSe4kLYLI/hZCKSJttBEJ+ObUrxL5BZkJTg+AvMSH52dX3B9LJtqS LiA6zZiBNi0WvJxKjxN4YTu2IuePCb4FrSbN+FnvzrIsZybvmGS5zaaSRQ04ndVFVeZb mx1qeo1SRGT+kMNEToFbVwohgSd6ia4GmJUpBa6yacIMedWcPVt/xGB6auLSksRr/8LC x7zQ== X-Gm-Message-State: AOJu0Yz00W07d5Nza8IDJNP5QceOwfMB9AeecLehpQ/exkKTONGnTxgq uXt/K/SKGOnHfjAGX2PBigfD/rKwU9MNlXoD8QmLg+mWMWxJnepTzpCztffG X-Google-Smtp-Source: AGHT+IHgB0ui/z2qNpGq1fKiW1kds1/IGj/CXbe3pmIU4fz2WLFDhTQqnaFaYqjXub3fD1kQcSrP2w== X-Received: by 2002:a17:906:6a1a:b0:a72:4c32:7d89 with SMTP id a640c23a62f3a-a7514440048mr691387966b.54.1719918106508; Tue, 02 Jul 2024 04:01:46 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v14 5/9] xen/riscv: enable full Xen build Date: Tue, 2 Jul 2024 13:01:32 +0200 Message-ID: <8ea6ebdeb3df9332f95f4ccfe42d9e439d674ae3.1719917348.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V14: - Nothing changed. Only rebase. - Update the the text in "changes in v13" by dropping some changes as they were done in different patch --- Changes in V13: - drop the footer after R-by as Andrews patch series were merged to staging. --- Changes in V5-V12: - Nothing changed. Only rebase. - Add the footer after Signed-off section. --- Changes in V4: - drop stubs for irq_actor_none() and irq_actor_none() as common/irq.c is compiled now. - drop defintion of max_page in stubs.c as common/page_alloc.c is compiled now. - drop printk() related changes in riscv/early_printk.c as common version will be used. --- Changes in V3: - Reviewed-by: Jan Beulich - unrealted change dropped in tiny64_defconfig --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 - xen/arch/riscv/early_printk.c | 168 ---------------------------------- 3 files changed, 15 insertions(+), 173 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 60afbc0ad9..81b77b13d6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8c071aff65..17827c302c 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -38,7 +38,3 @@ extensions := $(subst $(space),,$(extensions)) # -mcmodel=medlow would force Xen into the lower half. CFLAGS += $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7516310768sm269306866b.218.2024.07.02.04.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 04:01:46 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7a48722b-3862-11ef-92e8-0d9d20120eaa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719918107; x=1720522907; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2DnJInSJN8kZvos4JQuL1FC8EmJIQZBsSv+me/5mw1g=; b=gqzHaWcTCSmKiwC9CuijUZN4OUsmS826ygYOE/CjfI7PNUsEN6Yx5h37sb4r7kkX/J ++h2SnTwsm0hqcu/m/GIHgPlLcYugs+E1byRN/VzRZ7WenlJw1y5Qr4LAvCnKwCTPRL4 zTWy+9wxdBoUhPhK8ey6BXfTxv3hjD63ZvTnSCuQnA4k16aVkoeaJW/kF9gFxcbwxom3 G8Dn3U5bD0Zt+m/1TxKn3lzClmXo/MBJE5vVNxFFz8GiIM4BEJ8Mktox3xOiUILY3gGU qwlcV5lpEMVhYWKcDSbhf7s0pmlJ1gtO3B50pbdp117JP9CGdeF23SwgZRFZ6hPIaQbS Ekhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719918107; x=1720522907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2DnJInSJN8kZvos4JQuL1FC8EmJIQZBsSv+me/5mw1g=; b=IfvNjHRKoCZTJafdHFQ+YPfUTZRCcWtegj0XjqdqO/mKnVqWy/yqKjcJRBg62euKhu cv5/ZlObjS5Cb4EAQeaRrreE3fn6bEEde/a8utaP3IYe2N0sSVelGYzD7nN1o0hanbJs fxQSUnMcZ0ZeYsiGOGFxBSuoZjXnONXu3/yAaVJSIisueG/yEJ3E7805poYma/oCaP9P 9x4EfBhFXwCcXh3DcReQUNdCIedlWLNRL8wKZBFrfdbHZBC8+38snC/9bPcD/7bbk4WW Mxtj2v7JSVHEvN88OZHQFn9wx4h3whdRLIaCwQ7W4SPzgIP16pLu1nnSpHSwzJZ5J3SW 26sQ== X-Gm-Message-State: AOJu0YwEF8QC5nsP9MKI41uWhQKSJMvIOT+C51LiGpWhQecvdrahtl5R 9CaBsd1R0tdSPZj0T37RXVxqP57mAY5Rt6UM2Ka5ylVql+0DJ/Fxkzy2Av9R X-Google-Smtp-Source: AGHT+IFnYPcwToUXYD9LIAiRICiuu5UcdmHkImriuFMkrBcBDyNRTdzo8sbcKlrHP1mU2yVzGL8nRg== X-Received: by 2002:a17:906:d930:b0:a6f:cf64:a5d9 with SMTP id a640c23a62f3a-a75144f66abmr476198566b.49.1719918107211; Tue, 02 Jul 2024 04:01:47 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v14 6/9] xen/README: add compiler and binutils versions for RISC-V64 Date: Tue, 2 Jul 2024 13:01:33 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 This patch doesn't represent a strict lower bound for GCC and GNU Binutils; rather, these versions are specifically employed by the Xen RISC-V container and are anticipated to undergo continuous testing. Older GCC and GNU Binutils would work, but this is not a guarantee. While it is feasible to utilize Clang, it's important to note that, currently, there is no Xen RISC-V CI job in place to verify the seamless functioning of the build with Clang. Signed-off-by: Oleksii Kurochko Reviewed-by: Andrew Cooper --- Changes in V13: - Nothing changed. Only rebase. -- Changes in V13: - drop the line "Older GCC and GNU Binutils would work, but this is not a guarantee." in README - add Reviewed-by: Andrew Cooper -- Changes in V5-V12: - Nothing changed. Only rebase. --- Changes in V6: - update the message in README. --- Changes in V5: - update the commit message and README file with additional explanation about GCC and GNU Binutils version. Additionally, it was added information about Clang. --- Changes in V4: - Update version of GCC (12.2) and GNU Binutils (2.39) to the version which are in Xen's contrainter for RISC-V --- Changes in V3: - new patch --- README | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README b/README index 428e45549a..67e07a4a97 100644 --- a/README +++ b/README @@ -48,6 +48,9 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: + - GCC 12.2 or later + - GNU Binutils 2.39 or later * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev) From patchwork Tue Jul 2 11:01:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A09BC3065C for ; Tue, 2 Jul 2024 11:02:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752288.1160530 (Exim 4.92) (envelope-from ) id 1sObGj-0002Jp-93; Tue, 02 Jul 2024 11:01:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752288.1160530; Tue, 02 Jul 2024 11:01:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGj-0002Ia-1r; Tue, 02 Jul 2024 11:01:53 +0000 Received: by outflank-mailman (input) for mailman id 752288; Tue, 02 Jul 2024 11:01:50 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGg-0000Yf-Og for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:50 +0000 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [2a00:1450:4864:20::534]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7adea768-3862-11ef-aaf1-7f3abd7486c0; Tue, 02 Jul 2024 13:01:49 +0200 (CEST) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-57cc1c00ba6so1876455a12.1 for ; Tue, 02 Jul 2024 04:01:49 -0700 (PDT) Received: from fedora.. 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To support older version it would be better switch to .insn with operands. The following compilation error occurs: ./arch/riscv/include/asm/processor.h: Assembler messages: ./arch/riscv/include/asm/processor.h:70: Error: unrecognized opcode `0x0100000F' In case of the following Binutils: $ riscv64-linux-gnu-as --version GNU assembler (GNU Binutils for Debian) 2.35.2 Suggested-by: Andrew Cooper Signed-off-by: Oleksii Kurochko Suggested-by: Jan Beulich Reviewed-by: Jan Beulich --- Andrew, Could you please take a look if you are okay with suggested changes. Thanks in advance. --- Changes in V14: - add Suggested-By: Jan Beulich - switch from "raw" insn to .insn with operands to support older gas. --- Changes in V13: - new patch --- xen/arch/riscv/include/asm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 6846151717..3ae164c265 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -67,7 +67,7 @@ static inline void cpu_relax(void) __asm__ __volatile__ ( "pause" ); #else /* Encoding of the pause instruction */ - __asm__ __volatile__ ( ".insn 0x0100000F" ); + __asm__ __volatile__ ( ".insn r MISC_MEM, 0, 0, x0, x0, x16" ); #endif barrier(); From patchwork Tue Jul 2 11:01:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C9ADC30658 for ; Tue, 2 Jul 2024 11:02:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752287.1160522 (Exim 4.92) (envelope-from ) id 1sObGi-0002DQ-Oi; Tue, 02 Jul 2024 11:01:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752287.1160522; Tue, 02 Jul 2024 11:01:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGi-0002B7-Kb; Tue, 02 Jul 2024 11:01:52 +0000 Received: by outflank-mailman (input) for mailman id 752287; Tue, 02 Jul 2024 11:01:50 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGg-0000Yl-P8 for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:50 +0000 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [2a00:1450:4864:20::534]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7b7479ea-3862-11ef-92e8-0d9d20120eaa; Tue, 02 Jul 2024 13:01:50 +0200 (CEST) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-57cf8880f95so1613980a12.3 for ; Tue, 02 Jul 2024 04:01:50 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a7516310768sm269306866b.218.2024.07.02.04.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 04:01:48 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7b7479ea-3862-11ef-92e8-0d9d20120eaa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719918109; x=1720522909; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vXjBrtu/mn1eJNJdFhT1OrmNKZhkrDBzpy+oMb6YDGA=; b=WRU82DuMVuDosncPfJcnZKmpEFDRvDondSvNkQ4Fi81hM0YiKMKMREVzmB4IqNXhgX 7rau8SS+ASueN8HsuQ4NJ4Z3VTFPmkzzOkiQ0XDqVyl5dMhUq0n7Iavc6ZmoTzeONbu1 oGCU9SW+GSIvK8rH3lky8+lK/5aGAohMIwmRY7DHt32OekQcBPSzZwh1PiDxOROzlHvF /KBbE71J1eRfmlzFmsownVO0Jnm1LZef5WyNf5Qav/tdAGeF9IGEecMy4TUBxRR2HKXk FCRE4RLVEKFxwXLs3jsi8Cgt4v4aH+uFpqdtC9Gg2g8xh6vaPW4UmGU0lWCXZo0WgrMo dP2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719918109; x=1720522909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vXjBrtu/mn1eJNJdFhT1OrmNKZhkrDBzpy+oMb6YDGA=; b=uCCNe7EczaBUKJctOTR0dj/r+CQ8ju5rZVpa5rghSWGvy/KhlRNADFh3ZItczDxrfw ceMx15ZRaFjSambQyS7C76Fs+s5zoRtNQ5bpPbseC88CtIc3IcjHF9RVUVoriOVolQcX PpwMHC9C/aubKonWGVh4tdeDh95wgYPObaSjnBe0PMcVKdyhztpBXaYwKGqfmDn2y3Uy nz4AKWpvGqjjyGg3sJ29jwmaxQPzoL9zdtK/W2lVROv+5DhISHZVxan59d0GuPTzSyHL 0U2cxRJKo5y6WYQIqGtSf+4NCT9Ft1FKrXRdC8OAC+wZXIfVBccdre2wjB2cFWop+jgG 8Syw== X-Gm-Message-State: AOJu0YzeJoeVGoSWSRXO8v+GGvJd/xtCxjIUg8B8R4dV4tskioa5bIz3 N/7veUZjXdrGX5U80HL/+bilH9gXsnFUwGZWViP50gh+cfxPBMjn+Y6bA1wf X-Google-Smtp-Source: AGHT+IG1ElP8oExQdN2JZHAW7nJhQL+Q2M1vGiJZplWF++xD9hrNbas2UoMVjgjJXs7kodnWkRIKbg== X-Received: by 2002:a17:906:eece:b0:a75:20f7:2c71 with SMTP id a640c23a62f3a-a7520f733b6mr605166966b.38.1719918109416; Tue, 02 Jul 2024 04:01:49 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org, Andrew Cooper Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v14 8/9] xen/riscv: introduce ANDN_INSN Date: Tue, 2 Jul 2024 13:01:35 +0200 Message-ID: <07c628e8552f6e31a07e4261b273553cb4a3669b.1719917348.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: References: MIME-Version: 1.0 RISC-V does a conditional toolchain for the Zbb extension (xen/arch/riscv/rules.mk), but unconditionally uses the ANDN instruction in emulate_xchg_1_2(). Fixes: 51dabd6312c ("xen/riscv: introduce cmpxchg.h") Suggested-by: Andrew Cooper Signed-off-by: Oleksii Kurochko Suggested-By: Jan Beulich Reviewed-by: Jan Beulich --- Andrew, Could you please take a look if you are okay with suggested changes. Thanks in advance. --- Changes in V14: - update the commit on top of ANDN definition. - use .insn instead of andn to support gas which doesn't understand andn instruction. - add Suggested-By: Jan Beulich --- Changes in V13: - new patch --- xen/arch/riscv/include/asm/cmpxchg.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/asm/cmpxchg.h index d5e678c036..34d5bd48b3 100644 --- a/xen/arch/riscv/include/asm/cmpxchg.h +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -18,6 +18,19 @@ : "r" (new) \ : "memory" ); +/* + * To not face an issue that gas doesn't understand ANDN instruction + * it is encoded using .insn directive. + */ +#ifdef __riscv_zbb +#define ANDN_INSN(rd, rs1, rs2) \ + ".insn r 0x33, 0x7, 0x20, " rd ", " rs1 ", " rs2 "\n" +#else +#define ANDN_INSN(rd, rs1, rs2) \ + "not " rd ", " rs2 "\n" \ + "and " rd ", " rs1 ", " rd "\n" +#endif + /* * For LR and SC, the A extension requires that the address held in rs1 be * naturally aligned to the size of the operand (i.e., eight-byte aligned @@ -48,7 +61,7 @@ \ asm volatile ( \ "0: lr.w" lr_sfx " %[old], %[ptr_]\n" \ - " andn %[scratch], %[old], %[mask]\n" \ + ANDN_INSN("%[scratch]", "%[old]", "%[mask]") \ " or %[scratch], %[scratch], %z[new_]\n" \ " sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \ " bnez %[scratch], 0b\n" \ From patchwork Tue Jul 2 11:01:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13719409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6E8DC3065F for ; Tue, 2 Jul 2024 11:02:05 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.752289.1160545 (Exim 4.92) (envelope-from ) id 1sObGk-0002lV-P7; Tue, 02 Jul 2024 11:01:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 752289.1160545; Tue, 02 Jul 2024 11:01:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGk-0002k2-Fb; Tue, 02 Jul 2024 11:01:54 +0000 Received: by outflank-mailman (input) for mailman id 752289; Tue, 02 Jul 2024 11:01:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sObGj-0000Yf-6q for xen-devel@lists.xenproject.org; Tue, 02 Jul 2024 11:01:53 +0000 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [2a00:1450:4864:20::629]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7c5e04bc-3862-11ef-aaf1-7f3abd7486c0; Tue, 02 Jul 2024 13:01:51 +0200 (CEST) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-a724958f118so488330966b.0 for ; Tue, 02 Jul 2024 04:01:51 -0700 (PDT) Received: from fedora.. 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Requested-by: Jan Beulich Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V14: - Add Requested-by: Jan Beulich - Add Acked-by: Jan Beulich --- Changes in V13: - new patch --- xen/arch/x86/include/asm/bitops.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index f9aa60111f..8c0403405a 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -277,12 +277,6 @@ static inline int test_and_change_bit(int nr, volatile void *addr) test_and_change_bit(nr, addr); \ }) -static inline int constant_test_bit(int nr, const volatile void *addr) -{ - return ((1U << (nr & 31)) & - (((const volatile unsigned int *)addr)[nr >> 5])) != 0; -} - static inline int variable_test_bit(int nr, const volatile void *addr) { int oldbit; @@ -297,7 +291,7 @@ static inline int variable_test_bit(int nr, const volatile void *addr) #define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ - constant_test_bit(nr, addr) : \ + generic_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ })