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Wed, 3 Jul 2024 12:23:54 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 05:23:54 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mao Jinlong , "Alexander Shishkin" CC: , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , songchai , Jie Gan Subject: [PATCH v4 1/2] dt-bindings: arm: Add device-name in the coresight components Date: Wed, 3 Jul 2024 05:23:37 -0700 Message-ID: <20240703122340.26864-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240703122340.26864-1-quic_jinlmao@quicinc.com> References: <20240703122340.26864-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aoryo9K74mYuKwzieyp5VrWrOml95JZO X-Proofpoint-ORIG-GUID: aoryo9K74mYuKwzieyp5VrWrOml95JZO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_08,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030090 Current name of coresight component's folder consists of prefix of the device and the id in the device list. When run 'ls' command, we can get the register address of the device. Take CTI for example, if we want to set the config for modem CTI, but we can't know which CTI is modem CTI from all current information. cti_sys0 -> ../../../devices/platform/soc@0/138f0000.cti/cti_sys0 cti_sys1 -> ../../../devices/platform/soc@0/13900000.cti/cti_sys1 Add device-name in device tree which can provide a better description of the coresight device. It can provide the info like the system or HW it belongs to. Signed-off-by: Mao Jinlong --- .../devicetree/bindings/arm/arm,coresight-cti.yaml | 6 ++++++ .../devicetree/bindings/arm/arm,coresight-dummy-source.yaml | 6 ++++++ .../devicetree/bindings/arm/arm,coresight-stm.yaml | 6 ++++++ .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml index 2d5545a2b49c..6a73eaa66a42 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -98,6 +98,12 @@ properties: power-domains: maxItems: 1 + arm,cs-dev-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Define the name which can describe what kind of HW or system the + coresight device belongs to. + arm,cti-ctm-id: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml index 6745b4cc8f1c..578c5e3227a6 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml @@ -38,6 +38,12 @@ properties: enum: - arm,coresight-dummy-source + arm,cs-dev-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Define the name which can describe what kind of HW or system the + coresight device belongs to. + out-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml index 378380c3f5aa..3261d4f4adbb 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml @@ -51,6 +51,12 @@ properties: - const: stm-base - const: stm-stimulus-base + arm,cs-dev-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Define the name which can describe what kind of HW or system the + coresight device belongs to. + clocks: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 8eec07d9d454..12bb6403e934 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -44,6 +44,12 @@ properties: minItems: 1 maxItems: 2 + arm,cs-dev-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Define the name which can describe what kind of HW or system the + coresight device belongs to. + qcom,dsb-element-bits: description: Specifies the DSB(Discrete Single Bit) element size supported by From patchwork Wed Jul 3 12:23:38 2024 Content-Type: text/plain; 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Wed, 3 Jul 2024 12:23:55 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 05:23:54 -0700 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mao Jinlong , "Alexander Shishkin" CC: , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , songchai , Jie Gan Subject: [PATCH v4 2/2] coresight: core: Add device name support Date: Wed, 3 Jul 2024 05:23:38 -0700 Message-ID: <20240703122340.26864-3-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240703122340.26864-1-quic_jinlmao@quicinc.com> References: <20240703122340.26864-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: O4CplGfsGGw_X__9FY1jMNdWPnlcxurc X-Proofpoint-ORIG-GUID: O4CplGfsGGw_X__9FY1jMNdWPnlcxurc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_08,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030090 For some coresight components like CTI and TPDM, there could be numerous of them. From the node name, we can only get the type and register address of the component. We can't identify the HW or the system the component belongs to. Add the device-name support for adding the intuitive name of the device. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++--------- .../hwtracing/coresight/coresight-platform.c | 30 +++++++++++++++ include/linux/coresight.h | 3 +- 3 files changed, 52 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 9fc6f6b863e0..1d43333bbeb0 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1328,33 +1328,36 @@ EXPORT_SYMBOL_GPL(coresight_loses_context_with_cpu); * duplicate indices for the same device (e.g, if we defer probing of * a device due to dependencies), in case the index is requested again. */ -char *coresight_alloc_device_name(struct coresight_dev_list *dict, +const char *coresight_alloc_device_name(struct coresight_dev_list *dict, struct device *dev) { int idx; - char *name = NULL; + const char *name = NULL; struct fwnode_handle **list; mutex_lock(&coresight_mutex); - idx = coresight_search_device_idx(dict, dev_fwnode(dev)); - if (idx < 0) { - /* Make space for the new entry */ - idx = dict->nr_idx; - list = krealloc_array(dict->fwnode_list, - idx + 1, sizeof(*dict->fwnode_list), - GFP_KERNEL); - if (ZERO_OR_NULL_PTR(list)) { - idx = -ENOMEM; - goto done; + name = coresight_get_device_name(dev); + if (!name) { + idx = coresight_search_device_idx(dict, dev_fwnode(dev)); + if (idx < 0) { + /* Make space for the new entry */ + idx = dict->nr_idx; + list = krealloc_array(dict->fwnode_list, + idx + 1, sizeof(*dict->fwnode_list), + GFP_KERNEL); + if (ZERO_OR_NULL_PTR(list)) { + idx = -ENOMEM; + goto done; + } + + list[idx] = dev_fwnode(dev); + dict->fwnode_list = list; + dict->nr_idx = idx + 1; } - list[idx] = dev_fwnode(dev); - dict->fwnode_list = list; - dict->nr_idx = idx + 1; + name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", dict->pfx, idx); } - - name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", dict->pfx, idx); done: mutex_unlock(&coresight_mutex); return name; diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 64e171eaad82..66de52bd6c5e 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -183,6 +183,22 @@ static int of_coresight_get_cpu(struct device *dev) return cpu; } +static const char *of_coresight_get_device_name(struct device *dev) +{ + const char *name = NULL; + + if (!dev->of_node) + return NULL; + + /* + * Get the device name from DT. The name describes the HW or + * system the device is for. + */ + of_property_read_string(dev->of_node, "arm,cs-dev-name", &name); + + return name; +} + /* * of_coresight_parse_endpoint : Parse the given output endpoint @ep * and fill the connection information in @pdata->out_conns @@ -317,6 +333,11 @@ static inline int of_coresight_get_cpu(struct device *dev) { return -ENODEV; } + +static inline const char *of_coresight_get_device_name(struct device *dev) +{ + return NULL; +} #endif #ifdef CONFIG_ACPI @@ -796,6 +817,15 @@ int coresight_get_cpu(struct device *dev) } EXPORT_SYMBOL_GPL(coresight_get_cpu); +const char *coresight_get_device_name(struct device *dev) +{ + if (is_of_node(dev->fwnode)) + return of_coresight_get_device_name(dev); + else + return NULL; +} +EXPORT_SYMBOL_GPL(coresight_get_device_name); + struct coresight_platform_data * coresight_get_platform_data(struct device *dev) { diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f09ace92176e..f021f3e93978 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -626,7 +626,7 @@ extern int coresight_claim_device_unlocked(struct coresight_device *csdev); extern void coresight_disclaim_device(struct coresight_device *csdev); extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); -extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, +extern const char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev); extern bool coresight_loses_context_with_cpu(struct device *dev); @@ -643,6 +643,7 @@ void coresight_relaxed_write64(struct coresight_device *csdev, void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); extern int coresight_get_cpu(struct device *dev); +extern const char *coresight_get_device_name(struct device *dev); struct coresight_platform_data *coresight_get_platform_data(struct device *dev); struct coresight_connection *