From patchwork Thu Jul 4 03:15:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723133 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F1718AED for ; Thu, 4 Jul 2024 03:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062040; cv=none; b=fnCcSuyAN92vaNsCWUb0MlT9R+0izdRRbmFEAW7aQYjRe34vkYiSYq5xfIpeqK0q6nhUzFjEUOl0B/oLJtLC8PCV9VDJ6HGnDkY1RkUc9YOqzHCx/xrN8r/QdG54BxIAwPpQj7kOqmgf9+BmMd98uQJ/mCXoO3rfibO0fsNOa58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062040; c=relaxed/simple; bh=y8DVuwDfBOx2kUhfnbErHM6n5qAnJYcEiam1NpZS4vU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uazUihqy9+4S4RtMGw2TS2NMOAxa9jAGBbV7qbmBnyw6lNIsb/0cjRqhHgyGguSQJ8W9m8XIr2wcC18E2WbSDCM5QPdi04oOMCSrIIW6lGUYvR6UyIp/IX9B5y9BN2X6SHAyxsANOfCZm3zPuDbT4Q/7EM7nX73K7XonJvJnm1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L1fx3jWv; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L1fx3jWv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720062038; x=1751598038; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y8DVuwDfBOx2kUhfnbErHM6n5qAnJYcEiam1NpZS4vU=; b=L1fx3jWvzHF7iR2cIxAFdkKgMOycPEMY0Rtt9e5OaYrrlQia4dhxNc+Z w01vGTB7k4ytviHAyslq/VxHxpM5D/cqFEhFYFB+SjDBgbuSm7SqUn2Gu 4j3Ib8Bj2bo0h1b5TkA5lwYoncbE6YsjiU8GS+j+ZUomoB/C+GxdK4YgZ xG/+8WZiGrnabON7EgkNb7RrvTuw1Fdi/pSY+fN6xQx3YUqa/uyyYbM/m +nlKO8wu0J9qOjRM0+8CLoyoaweviBHGuBXov5vMR4ENUuIWP6p0UuY15 Oj9cXXXwsKtZv6JEaCAHk30F6UdbDMWzo37ib3nybzBnlbYRPWLUeMbag Q==; X-CSE-ConnectionGUID: qHVykvvYQTy5OFWaHWGwcA== X-CSE-MsgGUID: 7Hlw9RVxSJqtsFmlr/aV+g== X-IronPort-AV: E=McAfee;i="6700,10204,11122"; a="39838061" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="39838061" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2024 20:00:38 -0700 X-CSE-ConnectionGUID: i3qXcV1FRi2zABduduwTiQ== X-CSE-MsgGUID: nB3x+nD7SyOCQEcI6EAoig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052118" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:33 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 1/8] hw/core: Make CPU topology enumeration arch-agnostic Date: Thu, 4 Jul 2024 11:15:56 +0800 Message-Id: <20240704031603.1744546-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_SMT and CPU_TOPO_LEVEL_PACKAGE to CPU_TOPO_LEVEL_THREAD and CPU_TOPO_LEVEL_SOCKET. Also, enumerate additional topology levels for non-i386 arches, and add a CPU_TOPO_LEVEL_DEFAULT to help future smp-cache object de-compatibilize arch-specific cache topology settings. Signed-off-by: Zhao Liu Acked-by: Markus Armbruster --- Changes since RFC v2: * Dropped cpu-topology.h and cpu-topology.c since QAPI has the helper (CpuTopologyLevel_str) to convert enum to string. (Markus) * Fixed text format in machine.json (CpuTopologyLevel naming, 2 spaces between sentences). (Markus) * Added a new level "default" to de-compatibilize some arch-specific topo settings. (Daniel) * Moved CpuTopologyLevel to qapi/machine-common.json, at where the cache enumeration and smp-cache object would be added. - If smp-cache object is defined in qapi/machine.json, storage-daemon will complain about the qmp cmds in qapi/machine.json during compiling. Changes since RFC v1: * Used QAPI to enumerate CPU topology levels. * Dropped string_to_cpu_topo() since QAPI will help to parse the topo levels. --- include/hw/i386/topology.h | 18 +-------------- qapi/machine-common.json | 47 +++++++++++++++++++++++++++++++++++++- target/i386/cpu.c | 38 +++++++++++++++--------------- target/i386/cpu.h | 4 ++-- 4 files changed, 68 insertions(+), 39 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index dff49fce1154..10d05ff045c7 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -39,7 +39,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). */ - +#include "qapi/qapi-types-machine-common.h" #include "qemu/bitops.h" /* @@ -62,22 +62,6 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -/* - * CPUTopoLevel is the general i386 topology hierarchical representation, - * ordered by increasing hierarchical relationship. - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F]) - * or AMD (CPUID[0x80000026]). - */ -enum CPUTopoLevel { - CPU_TOPO_LEVEL_INVALID, - CPU_TOPO_LEVEL_SMT, - CPU_TOPO_LEVEL_CORE, - CPU_TOPO_LEVEL_MODULE, - CPU_TOPO_LEVEL_DIE, - CPU_TOPO_LEVEL_PACKAGE, - CPU_TOPO_LEVEL_MAX, -}; - /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { diff --git a/qapi/machine-common.json b/qapi/machine-common.json index fa6bd71d1280..82413c668bdb 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -5,7 +5,7 @@ # See the COPYING file in the top-level directory. ## -# = Machines S390 data types +# = Common machine types ## ## @@ -19,3 +19,48 @@ { 'enum': 'CpuS390Entitlement', 'prefix': 'S390_CPU_ENTITLEMENT', 'data': [ 'auto', 'low', 'medium', 'high' ] } + +## +# @CpuTopologyLevel: +# +# An enumeration of CPU topology levels. +# +# @invalid: Invalid topology level. +# +# @thread: thread level, which would also be called SMT level or +# logical processor level. The @threads option in +# SMPConfiguration is used to configure the topology of this +# level. +# +# @core: core level. The @cores option in SMPConfiguration is used +# to configure the topology of this level. +# +# @module: module level. The @modules option in SMPConfiguration is +# used to configure the topology of this level. +# +# @cluster: cluster level. The @clusters option in SMPConfiguration +# is used to configure the topology of this level. +# +# @die: die level. The @dies option in SMPConfiguration is used to +# configure the topology of this level. +# +# @socket: socket level, which would also be called package level. +# The @sockets option in SMPConfiguration is used to configure +# the topology of this level. +# +# @book: book level. The @books option in SMPConfiguration is used +# to configure the topology of this level. +# +# @drawer: drawer level. The @drawers option in SMPConfiguration is +# used to configure the topology of this level. +# +# @default: default level. Some architectures will have default +# topology settings (e.g., cache topology), and this special +# level means following the architecture-specific settings. +# +# Since: 9.1 +## +{ 'enum': 'CpuTopologyLevel', + 'prefix': 'CPU_TOPO_LEVEL', + 'data': [ 'invalid', 'thread', 'core', 'module', 'cluster', + 'die', 'socket', 'book', 'drawer', 'default' ] } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4c2e6f3a71e9..4ae3bbf30682 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -236,7 +236,7 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 0 /* Invalid value */) static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel share_level) + enum CpuTopologyLevel share_level) { uint32_t num_ids = 0; @@ -247,12 +247,12 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: num_ids = 1 << apicid_pkg_offset(topo_info); break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for THREAD and MODULE, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -301,10 +301,10 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, } static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 1; case CPU_TOPO_LEVEL_CORE: return topo_info->threads_per_core; @@ -313,7 +313,7 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, case CPU_TOPO_LEVEL_DIE: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die; - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return topo_info->threads_per_core * topo_info->cores_per_module * topo_info->modules_per_die * topo_info->dies_per_pkg; default: @@ -323,10 +323,10 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, } static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CPUTopoLevel topo_level) + enum CpuTopologyLevel topo_level) { switch (topo_level) { - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return 0; case CPU_TOPO_LEVEL_CORE: return apicid_core_offset(topo_info); @@ -334,7 +334,7 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return apicid_module_offset(topo_info); case CPU_TOPO_LEVEL_DIE: return apicid_die_offset(topo_info); - case CPU_TOPO_LEVEL_PACKAGE: + case CPU_TOPO_LEVEL_SOCKET: return apicid_pkg_offset(topo_info); default: g_assert_not_reached(); @@ -342,12 +342,12 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, return 0; } -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { case CPU_TOPO_LEVEL_INVALID: return CPUID_1F_ECX_TOPO_LEVEL_INVALID; - case CPU_TOPO_LEVEL_SMT: + case CPU_TOPO_LEVEL_THREAD: return CPUID_1F_ECX_TOPO_LEVEL_SMT; case CPU_TOPO_LEVEL_CORE: return CPUID_1F_ECX_TOPO_LEVEL_CORE; @@ -371,7 +371,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, unsigned long level, next_level; uint32_t num_threads_next_level, offset_next_level; - assert(count + 1 < CPU_TOPO_LEVEL_MAX); + assert(count + 1 < CPU_TOPO_LEVEL__MAX); /* * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. @@ -380,7 +380,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, level = CPU_TOPO_LEVEL_INVALID; for (int i = 0; i <= count; i++) { level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); /* @@ -388,7 +388,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, * and it just encodes the invalid level (all fields are 0) * into the last subleaf of 0x1f. */ - if (level == CPU_TOPO_LEVEL_PACKAGE) { + if (level == CPU_TOPO_LEVEL_SOCKET) { level = CPU_TOPO_LEVEL_INVALID; break; } @@ -399,7 +399,7 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, offset_next_level = 0; } else { next_level = find_next_bit(env->avail_cpu_topo, - CPU_TOPO_LEVEL_PACKAGE, + CPU_TOPO_LEVEL_SOCKET, level + 1); num_threads_next_level = num_threads_by_topo_level(topo_info, next_level); @@ -6462,7 +6462,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* Share the cache at package level. */ *eax |= max_thread_ids_for_cache(&topo_info, - CPU_TOPO_LEVEL_PACKAGE) << 14; + CPU_TOPO_LEVEL_SOCKET) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { @@ -7963,10 +7963,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu) env->nr_modules = 1; env->nr_dies = 1; - /* SMT, core and package levels are set by default. */ - set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); + /* thread, core and socket levels are set by default. */ + set_bit(CPU_TOPO_LEVEL_THREAD, env->avail_cpu_topo); set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); - set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); + set_bit(CPU_TOPO_LEVEL_SOCKET, env->avail_cpu_topo); } static void x86_cpu_initfn(Object *obj) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 29daf3704857..9ddba249aa9e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1653,7 +1653,7 @@ typedef struct CPUCacheInfo { * Used to encode CPUID[4].EAX[bits 25:14] or * CPUID[0x8000001D].EAX[bits 25:14]. */ - enum CPUTopoLevel share_level; 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d="scan'208";a="51052151" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:38 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 2/8] qapi/qom: Introduce smp-cache object Date: Thu, 4 Jul 2024 11:15:57 +0800 Message-Id: <20240704031603.1744546-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce smp-cache object so that user could define cache properties. In smp-cache object, define cache topology based on CPU topology level with two reasons: 1. In practice, a cache will always be bound to the CPU container (either private in the CPU container or shared among multiple containers), and CPU container is often expressed in terms of CPU topology level. 2. The x86's cache-related CPUIDs encode cache topology based on APIC ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV relies on also requires CPU containers to help indicate the private shared hierarchy of the cache. Therefore, for SMP systems, it is natural to use the CPU topology hierarchy directly in QEMU to define the cache topology. Currently, separated L1 cache (L1 data cache and L1 instruction cache) with unified higher-level cache (e.g., unified L2 and L3 caches), is the most common cache architectures. Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache with smp-cache object to add the basic cache topology support. Suggested-by: Daniel P. Berrange Signed-off-by: Zhao Liu --- Suggested by credit: * Referred to Daniel's suggestion to introduce cache JSON list, though as a standalone object since -smp/-machine can't support JSON. --- Changes since RFC v2: * New commit to implement cache list with JSON format instead of multiple sub-options in -smp. --- MAINTAINERS | 2 + hw/core/meson.build | 1 + hw/core/smp-cache.c | 103 ++++++++++++++++++++++++++++++++++++ include/hw/core/smp-cache.h | 27 ++++++++++ qapi/machine-common.json | 50 +++++++++++++++++ qapi/qapi-schema.json | 4 +- qapi/qom.json | 3 ++ 7 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 hw/core/smp-cache.c create mode 100644 include/hw/core/smp-cache.h diff --git a/MAINTAINERS b/MAINTAINERS index 6725913c8b3a..b5391a7538de 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1885,12 +1885,14 @@ F: hw/core/machine.c F: hw/core/machine-smp.c F: hw/core/null-machine.c F: hw/core/numa.c +F: hw/core/smp-cache.c F: hw/cpu/cluster.c F: qapi/machine.json F: qapi/machine-common.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/smp-cache.h F: include/hw/cpu/cluster.h F: include/sysemu/numa.h F: tests/unit/test-smp-parse.c diff --git a/hw/core/meson.build b/hw/core/meson.build index a3d9bab9f42a..6d3dae3af62e 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -14,6 +14,7 @@ hwcore_ss.add(files( common_ss.add(files('cpu-common.c')) common_ss.add(files('machine-smp.c')) +common_ss.add(files('smp-cache.c')) system_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) system_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loader.c')) system_ss.add(when: 'CONFIG_GUEST_LOADER', if_true: files('guest-loader.c')) diff --git a/hw/core/smp-cache.c b/hw/core/smp-cache.c new file mode 100644 index 000000000000..c0157ce51c8f --- /dev/null +++ b/hw/core/smp-cache.c @@ -0,0 +1,103 @@ +/* + * Cache Object for SMP machine + * + * Copyright (C) 2024 Intel Corporation. + * + * Author: Zhao Liu + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "hw/core/smp-cache.h" +#include "qapi/error.h" +#include "qapi/qapi-visit-machine-common.h" +#include "qom/object_interfaces.h" + +static void +smp_cache_get_cache_prop(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + SMPCache *cache = SMP_CACHE(obj); + SMPCachePropertyList *head = NULL; + SMPCachePropertyList **tail = &head; + + for (int i = 0; i < SMP_CACHE__MAX; i++) { + SMPCacheProperty *node = g_new(SMPCacheProperty, 1); + + node->name = cache->props[i].name; + node->topo = cache->props[i].topo; + QAPI_LIST_APPEND(tail, node); + } + + if (!visit_type_SMPCachePropertyList(v, name, &head, errp)) { + return; + } + qapi_free_SMPCachePropertyList(head); +} + +static void +smp_cache_set_cache_prop(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + SMPCache *cache = SMP_CACHE(obj); + SMPCachePropertyList *list, *node; + + if (!visit_type_SMPCachePropertyList(v, name, &list, errp)) { + return; + } + + for (node = list; node; node = node->next) { + if (node->value->topo == CPU_TOPO_LEVEL_INVALID) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology should match the valid CPU topology level", + CpuTopologyLevel_str(node->value->topo)); + goto out; + } + cache->props[node->value->name].topo = node->value->topo; + } + +out: + qapi_free_SMPCachePropertyList(list); +} + +static void smp_cache_class_init(ObjectClass *oc, void *data) +{ + object_class_property_add(oc, "caches", "SMPCacheProperties", + smp_cache_get_cache_prop, + smp_cache_set_cache_prop, + NULL, NULL); + object_class_property_set_description(oc, "caches", + "Cache property list for SMP machine"); +} + +static void smp_cache_instance_init(Object *obj) +{ + SMPCache *cache = SMP_CACHE(obj); + for (int i = 0; i < SMP_CACHE__MAX; i++) { + cache->props[i].name = (SMPCacheName)i; + cache->props[i].topo = CPU_TOPO_LEVEL_DEFAULT; + } +} + +static const TypeInfo smp_cache_info = { + .parent = TYPE_OBJECT, + .name = TYPE_SMP_CACHE, + .class_init = smp_cache_class_init, + .instance_size = sizeof(SMPCache), + .instance_init = smp_cache_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_USER_CREATABLE }, + { } + } +}; + +static void smp_cache_register_type(void) +{ + type_register_static(&smp_cache_info); +} + +type_init(smp_cache_register_type); diff --git a/include/hw/core/smp-cache.h b/include/hw/core/smp-cache.h new file mode 100644 index 000000000000..c6b4d9efc290 --- /dev/null +++ b/include/hw/core/smp-cache.h @@ -0,0 +1,27 @@ +/* + * Cache Object for SMP machine + * + * Copyright (C) 2024 Intel Corporation. + * + * Author: Zhao Liu + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + */ + +#ifndef SMP_CACHE_H +#define SMP_CACHE_H + +#include "qapi/qapi-types-machine-common.h" +#include "qom/object.h" + +#define TYPE_SMP_CACHE "smp-cache" +OBJECT_DECLARE_SIMPLE_TYPE(SMPCache, SMP_CACHE) + +struct SMPCache { + Object parent_obj; + + SMPCacheProperty props[SMP_CACHE__MAX]; +}; + +#endif /* SMP_CACHE_H */ diff --git a/qapi/machine-common.json b/qapi/machine-common.json index 82413c668bdb..8b8c0e9eeb86 100644 --- a/qapi/machine-common.json +++ b/qapi/machine-common.json @@ -64,3 +64,53 @@ 'prefix': 'CPU_TOPO_LEVEL', 'data': [ 'invalid', 'thread', 'core', 'module', 'cluster', 'die', 'socket', 'book', 'drawer', 'default' ] } + +## +# @SMPCacheName: +# +# An enumeration of cache for SMP systems. The cache name here is +# a combination of cache level and cache type. +# +# @l1d: L1 data cache. +# +# @l1i: L1 instruction cache. +# +# @l2: L2 (unified) cache. +# +# @l3: L3 (unified) cache +# +# Since: 9.1 +## +{ 'enum': 'SMPCacheName', + 'prefix': 'SMP_CACHE', + 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] } + +## +# @SMPCacheProperty: +# +# Cache information for SMP systems. +# +# @name: Cache name. +# +# @topo: Cache topology level. It accepts the CPU topology +# enumeration as the parameter, i.e., CPUs in the same +# topology container share the same cache. +# +# Since: 9.1 +## +{ 'struct': 'SMPCacheProperty', + 'data': { + 'name': 'SMPCacheName', + 'topo': 'CpuTopologyLevel' } } + +## +# @SMPCacheProperties: +# +# List wrapper of SMPCacheProperty. +# +# @caches: the SMPCacheProperty list. +# +# Since 9.1 +## +{ 'struct': 'SMPCacheProperties', + 'data': { 'caches': ['SMPCacheProperty'] } } diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json index b1581988e4eb..25394f2cda50 100644 --- a/qapi/qapi-schema.json +++ b/qapi/qapi-schema.json @@ -64,11 +64,11 @@ { 'include': 'compat.json' } { 'include': 'control.json' } { 'include': 'introspect.json' } -{ 'include': 'qom.json' } -{ 'include': 'qdev.json' } { 'include': 'machine-common.json' } { 'include': 'machine.json' } { 'include': 'machine-target.json' } +{ 'include': 'qom.json' } +{ 'include': 'qdev.json' } { 'include': 'replay.json' } { 'include': 'yank.json' } { 'include': 'misc.json' } diff --git a/qapi/qom.json b/qapi/qom.json index 8bd299265e39..797dd58a61f5 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -8,6 +8,7 @@ { 'include': 'block-core.json' } { 'include': 'common.json' } { 'include': 'crypto.json' } +{ 'include': 'machine-common.json' } ## # = QEMU Object Model (QOM) @@ -1064,6 +1065,7 @@ 'if': 'CONFIG_SECRET_KEYRING' }, 'sev-guest', 'sev-snp-guest', + 'smp-cache', 'thread-context', 's390-pv-guest', 'throttle-group', @@ -1135,6 +1137,7 @@ 'if': 'CONFIG_SECRET_KEYRING' }, 'sev-guest': 'SevGuestProperties', 'sev-snp-guest': 'SevSnpGuestProperties', + 'smp-cache': 'SMPCacheProperties', 'thread-context': 'ThreadContextProperties', 'throttle-group': 'ThrottleGroupProperties', 'tls-creds-anon': 'TlsCredsAnonProperties', From patchwork Thu Jul 4 03:15:58 2024 Content-Type: text/plain; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 3/8] hw/core: Add smp cache topology for machine Date: Thu, 4 Jul 2024 11:15:58 +0800 Message-Id: <20240704031603.1744546-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 With smp-cache object support, add smp cache topology for machine by linking the smp-cache object. Also add a helper to access cache topology level. Signed-off-by: Zhao Liu --- Changes since RFC v2: * Linked machine's smp_cache to smp-cache object instead of a builtin structure. This is to get around the fact that the keyval format of -machine can't support JSON. * Wrapped the cache topology level access into a helper. --- hw/core/machine-smp.c | 6 ++++++ hw/core/machine.c | 9 +++++++++ include/hw/boards.h | 5 ++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 5d8d7edcbd3f..88a73743eb1c 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -270,3 +270,9 @@ unsigned int machine_topo_get_threads_per_socket(const MachineState *ms) { return ms->smp.threads * machine_topo_get_cores_per_socket(ms); } + +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + SMPCacheName cache) +{ + return ms->smp_cache->props[cache].topo; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index 655d75c21fc1..09ef9fcd4a0b 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1045,6 +1045,15 @@ static void machine_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "smp", "CPU topology"); + /* TODO: Implement check() method based on machine support. */ + object_class_property_add_link(oc, "smp-cache", + TYPE_SMP_CACHE, + offsetof(MachineState, smp_cache), + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); + object_class_property_set_description(oc, "smp-cache", + "SMP cache property"); + object_class_property_add(oc, "phandle-start", "int", machine_get_phandle_start, machine_set_phandle_start, NULL, NULL); diff --git a/include/hw/boards.h b/include/hw/boards.h index ef6f18f2c1a7..56fa252cfcd2 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -6,10 +6,10 @@ #include "exec/memory.h" #include "sysemu/hostmem.h" #include "sysemu/blockdev.h" -#include "qapi/qapi-types-machine.h" #include "qemu/module.h" #include "qom/object.h" #include "hw/core/cpu.h" +#include "hw/core/smp-cache.h" #define TYPE_MACHINE_SUFFIX "-machine" @@ -45,6 +45,8 @@ void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp); unsigned int machine_topo_get_cores_per_socket(const MachineState *ms); unsigned int machine_topo_get_threads_per_socket(const MachineState *ms); +CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, + SMPCacheName cache); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); /** @@ -409,6 +411,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + SMPCache *smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; From patchwork Thu Jul 4 03:15:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723136 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F15591B7E4 for ; Thu, 4 Jul 2024 03:00:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; 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03 Jul 2024 20:00:53 -0700 X-CSE-ConnectionGUID: ng4MCgfcS9SjCwgQvP5iWg== X-CSE-MsgGUID: AHgzNJo6RNOHpJb5KadZig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052298" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:48 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 4/8] hw/core: Check smp cache topology support for machine Date: Thu, 4 Jul 2024 11:15:59 +0800 Message-Id: <20240704031603.1744546-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And implement check() method for machine's "smp-cache" link property, which will check the compatibility of the cache properties with the machine support. Signed-off-by: Zhao Liu --- Changes since RFC v2: * Split as a separate commit to just include compatibility checking and topology checking. * Allow setting "default" topology level even though the cache isn't supported by machine. (Daniel) --- hw/core/machine-smp.c | 80 +++++++++++++++++++++++++++++++++++++++++++ hw/core/machine.c | 17 +++++++-- include/hw/boards.h | 6 ++++ 3 files changed, 101 insertions(+), 2 deletions(-) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index 88a73743eb1c..bf6f2f91070d 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -276,3 +276,83 @@ CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, { return ms->smp_cache->props[cache].topo; } + +static bool machine_check_topo_support(MachineState *ms, + CpuTopologyLevel topo, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + if ((topo == CPU_TOPO_LEVEL_MODULE && !mc->smp_props.modules_supported) || + (topo == CPU_TOPO_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) || + (topo == CPU_TOPO_LEVEL_DIE && !mc->smp_props.dies_supported) || + (topo == CPU_TOPO_LEVEL_BOOK && !mc->smp_props.books_supported) || + (topo == CPU_TOPO_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) { + error_setg(errp, + "Invalid topology level: %s. " + "The topology level is not supported by this machine", + CpuTopologyLevel_str(topo)); + return false; + } + + return true; +} + +/* + * When both cache1 and cache2 are configured with specific topology levels + * (not default level), is cache1's topology level higher than cache2? + */ +static bool smp_cache_topo_cmp(const SMPCache *smp_cache, + SMPCacheName cache1, + SMPCacheName cache2) +{ + if (smp_cache->props[cache1].topo != CPU_TOPO_LEVEL_DEFAULT && + smp_cache->props[cache1].topo > smp_cache->props[cache2].topo) { + return true; + } + return false; +} + +bool machine_check_smp_cache_support(MachineState *ms, + const SMPCache *smp_cache, + Error **errp) +{ + MachineClass *mc = MACHINE_GET_CLASS(ms); + + for (int i = 0; i < SMP_CACHE__MAX; i++) { + const SMPCacheProperty *prop = &smp_cache->props[i]; + + /* + * Allow setting "default" topology level even though the cache + * isn't supported by machine. + */ + if (prop->topo != CPU_TOPO_LEVEL_DEFAULT && + !mc->smp_props.cache_supported[prop->name]) { + error_setg(errp, + "%s cache topology not supported by this machine", + SMPCacheName_str(prop->name)); + return false; + } + + if (!machine_check_topo_support(ms, prop->topo, errp)) { + return false; + } + } + + if (smp_cache_topo_cmp(smp_cache, SMP_CACHE_L1D, SMP_CACHE_L2) || + smp_cache_topo_cmp(smp_cache, SMP_CACHE_L1I, SMP_CACHE_L2)) { + error_setg(errp, + "Invalid smp cache topology. " + "L2 cache topology level shouldn't be lower than L1 cache"); + return false; + } + + if (smp_cache_topo_cmp(smp_cache, SMP_CACHE_L2, SMP_CACHE_L3)) { + error_setg(errp, + "Invalid smp cache topology. " + "L3 cache topology level shouldn't be lower than L2 cache"); + return false; + } + + return true; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index 09ef9fcd4a0b..802dd56ba717 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -926,6 +926,20 @@ static void machine_set_smp(Object *obj, Visitor *v, const char *name, machine_parse_smp_config(ms, config, errp); } +static void machine_check_smp_cache(const Object *obj, const char *name, + Object *child, Error **errp) +{ + MachineState *ms = MACHINE(obj); + SMPCache *smp_cache = SMP_CACHE(child); + + if (ms->smp_cache) { + error_setg(errp, "Invalid smp cache property. which has been set"); + return; + } + + machine_check_smp_cache_support(ms, smp_cache, errp); +} + static void machine_get_boot(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1045,11 +1059,10 @@ static void machine_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "smp", "CPU topology"); - /* TODO: Implement check() method based on machine support. */ object_class_property_add_link(oc, "smp-cache", TYPE_SMP_CACHE, offsetof(MachineState, smp_cache), - object_property_allow_set_link, + machine_check_smp_cache, OBJ_PROP_LINK_STRONG); object_class_property_set_description(oc, "smp-cache", "SMP cache property"); diff --git a/include/hw/boards.h b/include/hw/boards.h index 56fa252cfcd2..5455848c3e58 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -47,6 +47,9 @@ unsigned int machine_topo_get_cores_per_socket(const MachineState *ms); unsigned int machine_topo_get_threads_per_socket(const MachineState *ms); CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms, SMPCacheName cache); +bool machine_check_smp_cache_support(MachineState *ms, + const SMPCache *smp_cache, + Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); /** @@ -147,6 +150,8 @@ typedef struct { * @books_supported - whether books are supported by the machine * @drawers_supported - whether drawers are supported by the machine * @modules_supported - whether modules are supported by the machine + * @cache_supported - whether cache topologies (l1d, l1i, l2 and l3) are + * supported by the machine */ typedef struct { bool prefer_sockets; @@ -156,6 +161,7 @@ typedef struct { bool books_supported; bool drawers_supported; bool modules_supported; + bool cache_supported[SMP_CACHE__MAX]; } SMPCompatProps; /** From patchwork Thu Jul 4 03:16:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723137 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 025951B7E4 for ; Thu, 4 Jul 2024 03:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062060; cv=none; b=DpxKIn2L61oAIRVdCJ5QOugZxmoNxT9ygt6SFq6b6WQ/Bn/l3tFKENCkyd9BXhftjZ26UmMMdGFFsRe2a1BCJPiZQGYUUoHBa8n8IrCg1vTx1m/wXPqNurzMzOocgryAs4O8OU+mHais8oX/HvhTHXWA31rWwocRE3FSAOfnsJs= ARC-Message-Signature: i=1; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 5/8] i386/cpu: Support thread and module level cache topology Date: Thu, 4 Jul 2024 11:16:00 +0800 Message-Id: <20240704031603.1744546-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allows cache to be defined at the thread and module level. This increases flexibility for x86 users to customize their cache topology. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ae3bbf30682..0ddbfa577caf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -241,9 +241,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, uint32_t num_ids = 0; switch (share_level) { + case CPU_TOPO_LEVEL_THREAD: + num_ids = 1; + break; case CPU_TOPO_LEVEL_CORE: num_ids = 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids = 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids = 1 << apicid_die_offset(topo_info); break; @@ -251,10 +257,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, num_ids = 1 << apicid_pkg_offset(topo_info); break; default: - /* - * Currently there is no use case for THREAD and MODULE, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } From patchwork Thu Jul 4 03:16:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723138 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91ACC1BC23 for ; Thu, 4 Jul 2024 03:01:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062065; cv=none; b=eT6SEB+WXaojucDR/iK224jOaZY1eVhoF398bqFaDRDZZGV9bPyrgZAcziTfnRM0ZrYL6X496wuywax9NHJludATUalTPAGQ+7hoiE507I+wpAzGsaDoBMgsHOg9OceDfqDyZ8IrIWGZovP4Ihj8YtV8VTGrqHyoYpSlfUHBRUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062065; c=relaxed/simple; bh=fujCsC8Dys68Pql9dJtKAju+zQdGhBxq4c+kPZSh5nE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S4fbcpWYSmjyJSoK4nUZQDZWe3+8VfrbXaLKrenfAPBOJEbmOXVD9n5DPnn44hq41p1jqUKAudLf0ZqzG25ipevOxxpipRD4GPU/xTESpfRRtTodhZl//y7tTQ3EcA/Ek5HeYTkr2JJCuB82d3OGhJ7EvUvrrI8k8mPAfazgfqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DBgWmsH9; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DBgWmsH9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720062064; x=1751598064; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fujCsC8Dys68Pql9dJtKAju+zQdGhBxq4c+kPZSh5nE=; b=DBgWmsH9IrGbrPuSTzHt3Txpl4PfHO4gUo2Q5gNp5nMkm+Wbt0n/N8G3 T+KJkXNZMusFNC9ag1D1SWAlgiQO6a5SQ/Z9cbAGxnqgulNdL1HBXX2ZI zRegFH8MY8GPgHdTWzdo4h7trlPTounIeCTi+cueSJkITsUj+nMKJUv4T r0h/UgpB3SyiI+xKx+ta8T2f4o8kqjO8WoYPDe57tioOUUTTPqDQ5QnCB OQs/cK5n6wq5b/Fd+YhYRWuykDnEwVhpt8aOP8Rv0tNZFvRQe0NkpDXMf /ML9HJyzyv0GMZlYpdLOrxmNEQAdXruDtYUklG2U0Aa6NHM4S2gMjLj2t g==; X-CSE-ConnectionGUID: odQ+FStZQCOWTdTI4qE+lg== X-CSE-MsgGUID: 4FHRB40qSUiWPPAPvqDG8w== X-IronPort-AV: E=McAfee;i="6700,10204,11122"; a="39838138" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="39838138" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2024 20:01:03 -0700 X-CSE-ConnectionGUID: SWw29a7FTiSSxRr5IbNo7w== X-CSE-MsgGUID: P2ER7FN4T+qcoemaxtpO5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052438" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:00:58 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 6/8] i386/cpu: Update cache topology with machine's configuration Date: Thu, 4 Jul 2024 11:16:01 +0800 Message-Id: <20240704031603.1744546-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User will configure smp cache topology via smp-cache object. For this case, update the x86 CPUs' cache topology with user's configuration in MachineState. Signed-off-by: Zhao Liu --- Changes since RFC v2: * Used smp_cache array to override cache topology. * Wrapped the updating into a function. --- target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0ddbfa577caf..403a089111ca 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7568,6 +7568,38 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu) cpu->hyperv_limits[2] = 0; } +#ifndef CONFIG_USER_ONLY +static void x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + CpuTopologyLevel level; + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L1D); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1d_cache->share_level = level; + env->cache_info_amd.l1d_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L1I); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l1i_cache->share_level = level; + env->cache_info_amd.l1i_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L2); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l2_cache->share_level = level; + env->cache_info_amd.l2_cache->share_level = level; + } + + level = machine_get_cache_topo_level(ms, SMP_CACHE_L3); + if (level != CPU_TOPO_LEVEL_DEFAULT) { + env->cache_info_cpuid4.l3_cache->share_level = level; + env->cache_info_amd.l3_cache->share_level = level; + } +} +#endif + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -7792,6 +7824,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) #ifndef CONFIG_USER_ONLY MachineState *ms = MACHINE(qdev_get_machine()); + + if (ms->smp_cache) { + x86_cpu_update_smp_cache_topo(ms, cpu); + } + qemu_register_reset(x86_cpu_machine_reset_cb, cpu); if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { From patchwork Thu Jul 4 03:16:02 2024 Content-Type: text/plain; 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Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 7/8] i386/pc: Support cache topology in -machine for PC machine Date: Thu, 4 Jul 2024 11:16:02 +0800 Message-Id: <20240704031603.1744546-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC machine. Signed-off-by: Zhao Liu --- Changes since RFC v2: * Used cache_supported array. --- hw/i386/pc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 77415064c62e..1614a3b1bf19 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1773,6 +1773,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->smp_props.modules_supported = true; + mc->smp_props.cache_supported[SMP_CACHE_L1D] = true; + mc->smp_props.cache_supported[SMP_CACHE_L1I] = true; + mc->smp_props.cache_supported[SMP_CACHE_L2] = true; + mc->smp_props.cache_supported[SMP_CACHE_L3] = true; mc->default_ram_id = "pc.ram"; pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; From patchwork Thu Jul 4 03:16:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhao Liu X-Patchwork-Id: 13723140 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 896B417C67 for ; Thu, 4 Jul 2024 03:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062075; cv=none; b=CvKGIuR7a28FBiM92LZ5KHgHtngyAWP69xz7fl1TcUR55mpMUu7H9nrRJ29Rrm9cO8aj0b3hPXJUPRMqFPaYMo/8GnahLpJg51yr6j/nZFzq7UI2RGuZx3e5VTwXA55seORZuR7XxinB4QBsG4shw1GmOcWJBeszhVw3yx/9ggE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720062075; c=relaxed/simple; bh=7xazZwz0EnajiB5Y3BpYOkdjmqrqDIqJeO1R5Tf6FMU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=L3u0ZC92G+/4T8AE4m+NIjayaY9qnYcTT3h858DWcn/ga7ZOQNgiCwNtQctdQ+SJ/xLSGt8VHcz2mUPwYy3RCSoB10zjRFd934ubTau5AwhD3+4iaKwlFPUHgqKrc+VhWDl2rCcqY8qo4eS4EZ8hCqDMEHH0JzpkFVxECF03l60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XT7DiQri; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XT7DiQri" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720062074; x=1751598074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7xazZwz0EnajiB5Y3BpYOkdjmqrqDIqJeO1R5Tf6FMU=; b=XT7DiQriR2FX6Z4mUcy61QZJ/jd8kO22Q/qIfYbyyK2X/9iP+7hdVhb8 hhmDhkhKlwIR4cYQPLF0B3LibxRx6ZGw1+BEyx3HZqwGENm5QLq4xPKpy GkOrcXp2/e4/mC4vdBmNDNbTWvsekMm2p0mdJPO6v9TAT20qXHAu2khRy YF17kPJ1lPUDHrmOcGpDVKPd8cd2m99g4fYqeRc3S5766/Vcqka4BFwOH hdxVGW8TOuZ8bVZDxvtRE9BV+9yIGd0QTCbMkTzLzDHJITjAOkZ3mV4ij e0w7JG1xyOFP7JVYM0PcJohUqdznOw1jJH1S3X3zBtLf7w7uM4Ts/8/QA Q==; X-CSE-ConnectionGUID: fzAqoshPSfuFUoawlLI2TQ== X-CSE-MsgGUID: syT9+eg/Ts2x6/vnjZpHbg== X-IronPort-AV: E=McAfee;i="6700,10204,11122"; a="39838163" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="39838163" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2024 20:01:13 -0700 X-CSE-ConnectionGUID: uK+DmRjmRO6RTIeeRo8L0Q== X-CSE-MsgGUID: PAO0ufSFQueLjRECY+D3Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="51052503" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by fmviesa004.fm.intel.com with ESMTP; 03 Jul 2024 20:01:08 -0700 From: Zhao Liu To: =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Paolo Bonzini , Richard Henderson , Eric Blake , Markus Armbruster , Marcelo Tosatti , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Jonathan Cameron , Sia Jee Heng Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Zhenyu Wang , Dapeng Mi , Yongwei Ma , Zhao Liu Subject: [PATCH 8/8] qemu-options: Add the description of smp-cache object Date: Thu, 4 Jul 2024 11:16:03 +0800 Message-Id: <20240704031603.1744546-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240704031603.1744546-1-zhao1.liu@intel.com> References: <20240704031603.1744546-1-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Zhao Liu --- Changes since RFC v2: * Rewrote the document of smp-cache object. Changes since RFC v1: * Use "*_cache=topo_level" as -smp example as the original "level" term for a cache has a totally different meaning. (Jonathan) --- qemu-options.hx | 58 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 8ca7f34ef0c8..4b84f4508a6e 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -159,6 +159,15 @@ SRST :: -machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512 + + ``smp-cache='id'`` + Allows to configure cache property (now only the cache topology level). + + For example: + :: + + -object '{"qom-type":"smp-cache","id":"cache","caches":[{"name":"l1d","topo":"core"},{"name":"l1i","topo":"core"},{"name":"l2","topo":"module"},{"name":"l3","topo":"die"}]}' + -machine smp-cache=cache ERST DEF("M", HAS_ARG, QEMU_OPTION_M, @@ -5871,6 +5880,55 @@ SRST :: (qemu) qom-set /objects/iothread1 poll-max-ns 100000 + + ``-object '{"qom-type":"smp-cache","id":id,"caches":[{"name":cache_name,"topo":cache_topo}]}'`` + Create an smp-cache object that configures machine's cache + property. Currently, cache property only include cache topology + level. + + This option must be written in JSON format to support JSON list. + + The ``caches`` parameter accepts a list of cache property in JSON + format. + + A list element requires the cache name to be specified in the + ``name`` parameter (currently ``l1d``, ``l1i``, ``l2`` and ``l3`` + are supported). ``topo`` parameter accepts CPU topology levels + including ``thread``, ``core``, ``module``, ``cluster``, ``die``, + ``socket``, ``book``, ``drawer`` and ``default``. The ``topo`` + parameter indicates CPUs winthin the same CPU topology container + are sharing the same cache. + + Some machines may have their own cache topology model, and this + object may override the machine-specific cache topology setting + by specifying smp-cache object in the -machine. When specifying + the cache topology level of ``default``, it will honor the default + machine-specific cache topology setting. For other topology levels, + they will override the default setting. + + An example list of caches to configure the cache model (l1d cache + per core, l1i cache per core, l2 cache per module and l3 cache per + socket) supported by PC machine might look like: + + :: + + { + "caches": [ + { "name": "l1d", "topo": "core" }, + { "name": "l1i", "topo": "core" }, + { "name": "l2", "topo": "module" }, + { "name": "l3", "topo": "socket" }, + ] + } + + An example smp-cache object would look like:() + + .. parsed-literal:: + + # |qemu_system| \\ + ... \\ + -object '{"qom-type":"smp-cache","id":id,"caches":[{"name":cache_name,"topo":cache_topo}]}' \\ + ... ERST