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Fri, 5 Jul 2024 14:15:27 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1720145727; bh=pwUN5lYMsmvuVpK7tHjZdOJjDehz/TxwOscJJ7zxGmo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MawbdCNY+bOz031/n7ESn3SOYLzWrnqbKa0dWhrzHrwTKOclIV3fJVBEWJTWbr4Ty poK1Hw1M62jix6FiPF1rxa30578eKRrSS/TUCmVy5Nm4ItQsMwUhC66s3mYl1845Co Eto6byAHG/Q5C/gY2N6RQvpByFxDZOQZ45VDY2EC13z29k+DQQBunbFD2JgtmheDhp QODOtgiS1br4yZO+oiH+xsEJmDTkgxuuVfNgTRucpAlULJfRfcDGE8HstjgWlOSvGD wQZ8gYrFGLq8I1C1xwDc2YXcddbQ6jpH6hJ660mVhqRJ+WCuJDju4rGlhiZ3USgT/u aLVvnmyfI0tKg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 76F2F13EE52; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 7157E280018; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 1/9] mips: dts: realtek: use "serial" instead of "uart" in node name Date: Fri, 5 Jul 2024 14:15:12 +1200 Message-ID: <20240705021520.2737568-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=IkcTkHD0fZMA:10 a=4kmOji7k6h8A:10 a=VwQbUJbxAAAA:8 a=fO4XG2tHwy1-jxZR0dsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=vBONLeOcVZgRSqRidLXE:22 a=AjGcO6oz07-iQ99wixmX:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Update the node name for the UARTs to resolve the following dtbs_check complaints: uart@2000: $nodename:0: 'uart@2000' does not match '^serial(@.*)?$' uart@2100: $nodename:0: 'uart@2100' does not match '^serial(@.*)?$' Signed-off-by: Chris Packham Reviewed-by: Marek Behún --- Notes: Changes in v4: - Add r-by from Marek Changes in v3: - None Changes in v2: - New arch/mips/boot/dts/realtek/rtl83xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi index de65a111b626..03ddc61f7c9e 100644 --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi @@ -22,7 +22,7 @@ soc: soc { #size-cells = <1>; ranges = <0x0 0x18000000 0x10000>; - uart0: uart@2000 { + uart0: serial@2000 { compatible = "ns16550a"; reg = <0x2000 0x100>; @@ -39,7 +39,7 @@ uart0: uart@2000 { status = "disabled"; }; - uart1: uart@2100 { + uart1: serial@2100 { compatible = "ns16550a"; reg = <0x2100 0x100>; From patchwork Fri Jul 5 02:15:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724327 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D0A65C83 for ; Fri, 5 Jul 2024 02:15:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720145739; cv=none; b=jPi3lnPE2gC5Wpkd/Dg5ZeEPk9Z7+in1erw43WsUZml11XSPJQClLOTazKR2qHFWUrS8mJRS8S5gDIC2YrsoE56yeIyc1hmGjNNfGPPvWY/oiBeJHCLfxo1Vt08XKDvcNiqsCiaNddK/iu0hO7i7orE+zyqUSuJO6xDXJ+KTQ7M= ARC-Message-Signature: i=1; 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This resolves the following dtbs_check complaint: cpus: cpu@0: 'cache-level' is a required property Signed-off-by: Chris Packham Reviewed-by: Marek Behún --- Notes: Changes in v4: - Add r-by from Marek Changes in v3: - None Changes in v2: - New arch/mips/boot/dts/realtek/rtl838x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi index 6cc4ff5c0d19..722106e39194 100644 --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi @@ -6,6 +6,7 @@ cpus { #size-cells = <0>; cpu@0 { + device_type = "cpu"; compatible = "mips,mips4KEc"; reg = <0>; clocks = <&baseclk 0>; From patchwork Fri Jul 5 02:15:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724324 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D2E214A81 for ; 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Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 7E6B813EE87; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 7BCFF280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 3/9] dt-bindings: vendor-prefixes: Add Cameo Communications Date: Fri, 5 Jul 2024 14:15:14 +1200 Message-ID: <20240705021520.2737568-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=9AoCKF9XAAAA:8 a=KKAkSRfTAAAA:8 a=L4MHaItcyTsGJ2lxC4sA:9 a=3ZKOabzyN94A:10 a=zuUzDCw_FVeVL6jMbh0G:22 a=cvBusfyB2V15izCimMoJ:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add entry for Cameo Communications (https://www.cameo.com.tw/) Signed-off-by: Chris Packham Acked-by: Krzysztof Kozlowski --- Notes: Changes in v4: - Add ack from Krzysztof Changes in v3: - new Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..67550f0dd189 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -246,6 +246,8 @@ patternProperties: description: CALAO Systems SAS "^calxeda,.*": description: Calxeda + "^cameo,.*": + description: Cameo Communications, Inc "^canaan,.*": description: Canaan, Inc. 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Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski --- Notes: Changes in v4: - Add r-by from Krzysztof Changes in v3: - Use full board name - I've decided to stick with rtl9302-soc to disambiguate it from what I eventually plan to add as rtl9302-switch which is in the same package but are separate dies. Changes in v2: - Use specific compatible for rtl9302-soc - Fix to allow correct board, soc compatible Documentation/devicetree/bindings/mips/realtek-rtl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml index f8ac309d2994..d337655bfbf8 100644 --- a/Documentation/devicetree/bindings/mips/realtek-rtl.yaml +++ b/Documentation/devicetree/bindings/mips/realtek-rtl.yaml @@ -20,5 +20,9 @@ properties: - enum: - cisco,sg220-26 - const: realtek,rtl8382-soc + - items: + - enum: + - cameo,rtl9302c-2x-rtl8224-2xge + - const: realtek,rtl9302-soc additionalProperties: true From patchwork Fri Jul 5 02:15:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724329 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56AE726AD3 for ; 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Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 879FA13EE9C; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 84D13280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 5/9] dt-bindings: timer: Add schema for realtek,otto-timer Date: Fri, 5 Jul 2024 14:15:16 +1200 Message-ID: <20240705021520.2737568-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=KKAkSRfTAAAA:8 a=gEfo2CItAAAA:8 a=2AJCWd3gv_sDiQv9-YsA:9 a=3ZKOabzyN94A:10 a=cvBusfyB2V15izCimMoJ:22 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add the devicetree schema for the realtek,otto-timer present on a number of Realtek SoCs. Signed-off-by: Chris Packham Reviewed-by: Krzysztof Kozlowski --- Notes: Changes in v4: - Add r-by from Krzysztof Changes in v3: - Use items to describe regs and interrupt properties - Remove minItems condition Changes in v2: - Use specific compatible (rtl9302-timer instead of rtl930x-timer) - Remove unnecessary label - Remove unused irq flags (interrupt controller is one-cell) - Set minItems for reg and interrupts based on compatible .../bindings/timer/realtek,otto-timer.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml b/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml new file mode 100644 index 000000000000..7b6ec2c69484 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/realtek,otto-timer.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/realtek,otto-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Otto SoCs Timer/Counter + +description: + Realtek SoCs support a number of timers/counters. These are used + as a per CPU clock event generator and an overall CPU clocksource. + +maintainers: + - Chris Packham + +properties: + $nodename: + pattern: "^timer@[0-9a-f]+$" + + compatible: + items: + - enum: + - realtek,rtl9302-timer + - const: realtek,otto-timer + + reg: + items: + - description: timer0 registers + - description: timer1 registers + - description: timer2 registers + - description: timer3 registers + - description: timer4 registers + + clocks: + maxItems: 1 + + interrupts: + items: + - description: timer0 interrupt + - description: timer1 interrupt + - description: timer2 interrupt + - description: timer3 interrupt + - description: timer4 interrupt + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; From patchwork Fri Jul 5 02:15:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724332 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D70673D55D for ; Fri, 5 Jul 2024 02:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720145742; cv=none; b=bBzagWhBp68zi/AZPCJU126vX27FRDDNaFW/ZSUIYLwHNjhrtlCuKXxZlWLfOma8xwM8jeP6Clcf5tuPjTsyrtuKZPuNbtcIxKaRWqrVFNn31ICBLE0SJ5zegQBRvLboNk3TH5kQYEMzhQktjEV5dTdc9dqYaJk3qLCjbd40VaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720145742; c=relaxed/simple; bh=ljU6sRcs7sQuHTpD9/5+A8t80/9OARDwl6j8aTgrIpc=; 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Fri, 5 Jul 2024 14:15:28 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1720145728; bh=adwuxCP0b2iJnp5YoKfId4BXKuJvpUjFFbukitvRfSg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kj7LJRynW0OKdN3cy9AewJ1zWDtpQmmyygowmRfwLvYlaSjeCuHllpNBI5WFGyoLf WUI7TVx8819fbMlBo2JeLJYead2GUeYk25Xvr2U5fYvelMxUF0l3HmjQhWMplQL35+ XgRWATrVgIxTA3jYxDYcyDbXzsgGkgnaRHsHjyM9V3fKjhLYmtS9wodLBI+iEg0R9z SxyfrZHve5yjrnQV04b2mAz+SR7CmpUFWPERcmEGVaPcXzCnRTby37W5AgI1G7SWpv eP6tHyKJBuQ/tZ5wplMCWMhaE7eKM2k3v8DQjVnAbD0syft2eE5lYGPvhyiwkBgiOp a7KvY/AjCptHA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 8C28813ED5B; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 896AC280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 6/9] dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc Date: Fri, 5 Jul 2024 14:15:17 +1200 Message-ID: <20240705021520.2737568-7-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=RxOWC8M5BiJtX5JSj5EA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add a compatible string for the interrupt controller found on the rtl930x SoCs. The interrupt controller has registers for VPE1 so these are added as a second reg cell. Signed-off-by: Chris Packham --- Notes: Changes in v3: - Add reg::minItems where required Changes in v3: - Use items to describe the regs property Changes in v2: - Set reg:maxItems to 2 to allow for VPE1 registers on the rtl9300. Add a condition to enforce the old limit on other SoCs. - Connor and Krzysztof offered acks on v1 but I think the changes here are big enough to void those. .../realtek,rtl-intc.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml index fb5593724059..f36aaab73c01 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - realtek,rtl8380-intc + - realtek,rtl9300-intc - const: realtek,rtl-intc - const: realtek,rtl-intc deprecated: true @@ -35,7 +36,10 @@ properties: const: 1 reg: - maxItems: 1 + minItems: 1 + items: + - description: vpe0 registers + - description: vpe1 registers interrupts: minItems: 1 @@ -71,6 +75,20 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: realtek,rtl9300-intc + then: + properties: + reg: + minItems: 1 + maxItems: 2 + else: + properties: + reg: + maxItems: 1 additionalProperties: false From patchwork Fri Jul 5 02:15:18 2024 Content-Type: text/plain; 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Fri, 5 Jul 2024 14:15:27 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1720145727; bh=OpiSNE+pGrnmvWVxJe9dW4AF0oPVsI3d6AdbWaZzcoc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VYfVEWOUNPIjG6WiI/ypl5mylJ2nKUSCrvlkfa5DovLWPiB2pTnj4Sxw+x39kkzHa X2dYs3mMt2mkmYBkKVSGfjUDMr1t8s28FxNIoW9qSS4Wll25HDYoEpw5evmB7/qqHs rKfwJ6TXTbAN6hT34kA5xv0DbtivM0EjDCM8S+MP+zSOGYsosjJeyUUJ0WO7KQMCSe hJt2HGgIPHUEqVxfWqcMiMEBca5cpyRsAsDQTrqAAUskOCY9s+dBoJXYp/MQkQEkLy hdJxrMGEX0hN0x3Z3NmQGB5NbogQoSys0Rk1Hlm5lECl96Y+nvzv29JI597/Q5tZVy SySEPYQnHxzbg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 90E5913EE52; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 8E268280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham , Markus Stockhausen Subject: [PATCH v4 7/9] clocksource: realtek: Add timer driver for rtl-otto platforms Date: Fri, 5 Jul 2024 14:15:18 +1200 Message-ID: <20240705021520.2737568-8-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=jU52IrjdAAAA:8 a=jdP34snFAAAA:8 a=lYcVSoeQvU4dK_rf-5cA:9 a=3ZKOabzyN94A:10 a=udjdHy_fWrGJRxLc5KTh:22 a=jlphF6vWLdwq7oh3TaWq:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat The timer/counter block on the Realtek SoCs provides up to 5 timers. It also includes a watchdog timer which is handled by the realtek_otto_wdt.c driver. One timer will be used per CPU as a local clock event generator. An additional timer will be used as an overal stable clocksource. Signed-off-by: Markus Stockhausen Signed-off-by: Sander Vanheule Signed-off-by: Chris Packham --- Notes: This is derrived from openwrt[1],[2]. I've retained the original signoff and added my own. [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob_plain;f=target/linux/realtek/files-5.15/drivers/clocksource/timer-rtl-otto.c;hb=HEAD [2] https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob_plain;f=target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch;hb=HEAD Changes in v4: - Reword comment about watchdog timer - Add includes for cpumask.h, io.h, jiffies.h and printk.h - Remove unnecessary casts Changes in v3: - Remove unnecessary select COMMON_CLK - Use %p when printing pointer Changes in v2 - None drivers/clocksource/Kconfig | 10 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rtl-otto.c | 291 +++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 303 insertions(+) create mode 100644 drivers/clocksource/timer-rtl-otto.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 34faa0320ece..70ba57210862 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -134,6 +134,16 @@ config RDA_TIMER help Enables the support for the RDA Micro timer driver. +config REALTEK_OTTO_TIMER + bool "Clocksource/timer for the Realtek Otto platform" + select TIMER_OF + help + This driver adds support for the timers found in the Realtek RTL83xx + and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381 + and RTL832, as well as chips from the RTL839x series, such as RTL8390 + RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series + such as RTL9301, RTL9302 or RTL9303. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 4bb856e4df55..22743785299e 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o obj-$(CONFIG_RDA_TIMER) += timer-rda.o +obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-rtl-otto.c b/drivers/clocksource/timer-rtl-otto.c new file mode 100644 index 000000000000..8a3068b36e75 --- /dev/null +++ b/drivers/clocksource/timer-rtl-otto.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define RTTM_DATA 0x0 +#define RTTM_CNT 0x4 +#define RTTM_CTRL 0x8 +#define RTTM_INT 0xc + +#define RTTM_CTRL_ENABLE BIT(28) +#define RTTM_INT_PENDING BIT(16) +#define RTTM_INT_ENABLE BIT(20) + +/* + * The Otto platform provides multiple 28 bit timers/counters with the following + * operating logic. If enabled the timer counts up. Per timer one can set a + * maximum counter value as an end marker. If end marker is reached the timer + * fires an interrupt. If the timer "overflows" by reaching the end marker or + * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and + * the timer is in operating mode COUNTER it stops. In mode TIMER it will + * continue to count up. + */ +#define RTTM_CTRL_COUNTER 0 +#define RTTM_CTRL_TIMER BIT(24) + +#define RTTM_BIT_COUNT 28 +#define RTTM_MIN_DELTA 8 +#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) + +/* + * Timers are derived from the LXB clock frequency. Usually this is a fixed + * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. + * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its + * base. The only meaningful frequencies we can achieve from that are 175.000 + * MHz and 153.125 MHz. The greatest common divisor of all explained possible + * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. + */ +#define RTTM_TICKS_PER_SEC 3125000 + +struct rttm_cs { + struct timer_of to; + struct clocksource cs; +}; + +/* Simple internal register functions */ +static inline void rttm_set_counter(void __iomem *base, unsigned int counter) +{ + iowrite32(counter, base + RTTM_CNT); +} + +static inline unsigned int rttm_get_counter(void __iomem *base) +{ + return ioread32(base + RTTM_CNT); +} + +static inline void rttm_set_period(void __iomem *base, unsigned int period) +{ + iowrite32(period, base + RTTM_DATA); +} + +static inline void rttm_disable_timer(void __iomem *base) +{ + iowrite32(0, base + RTTM_CTRL); +} + +static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) +{ + iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); +} + +static inline void rttm_ack_irq(void __iomem *base) +{ + iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); +} + +static inline void rttm_enable_irq(void __iomem *base) +{ + iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); +} + +static inline void rttm_disable_irq(void __iomem *base) +{ + iowrite32(0, base + RTTM_INT); +} + +/* Aggregated control functions for kernel clock framework */ +#define RTTM_DEBUG(base) \ + pr_debug("------------- %d %p\n", \ + smp_processor_id(), base) + +static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clkevt = dev_id; + struct timer_of *to = to_timer_of(clkevt); + + rttm_ack_irq(to->of_base.base); + RTTM_DEBUG(to->of_base.base); + clkevt->event_handler(clkevt); + + return IRQ_HANDLED; +} + +static void rttm_stop_timer(void __iomem *base) +{ + rttm_disable_timer(base); + rttm_ack_irq(base); +} + +static void rttm_start_timer(struct timer_of *to, u32 mode) +{ + rttm_set_counter(to->of_base.base, 0); + rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); +} + +static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, delta); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_oneshot(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_COUNTER); + + return 0; +} + +static int rttm_state_periodic(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); + rttm_start_timer(to, RTTM_CTRL_TIMER); + + return 0; +} + +static int rttm_state_shutdown(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + RTTM_DEBUG(to->of_base.base); + rttm_stop_timer(to->of_base.base); + + return 0; +} + +static void rttm_setup_timer(void __iomem *base) +{ + RTTM_DEBUG(base); + rttm_stop_timer(base); + rttm_set_period(base, 0); +} + +static u64 rttm_read_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + return rttm_get_counter(rcs->to.of_base.base); +} + +/* Module initialization part. */ +static DEFINE_PER_CPU(struct timer_of, rttm_to) = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, + .of_irq = { + .flags = IRQF_PERCPU | IRQF_TIMER, + .handler = rttm_timer_interrupt, + }, + .clkevt = { + .rating = 400, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_periodic = rttm_state_periodic, + .set_state_shutdown = rttm_state_shutdown, + .set_state_oneshot = rttm_state_oneshot, + .set_next_event = rttm_next_event + }, +}; + +static int rttm_enable_clocksource(struct clocksource *cs) +{ + struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); + + rttm_disable_irq(rcs->to.of_base.base); + rttm_setup_timer(rcs->to.of_base.base); + rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER, + rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC); + + return 0; +} + +struct rttm_cs rttm_cs = { + .to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, + }, + .cs = { + .name = "realtek_otto_timer", + .rating = 400, + .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .read = rttm_read_clocksource, + } +}; + +static u64 notrace rttm_read_clock(void) +{ + return rttm_get_counter(rttm_cs.to.of_base.base); +} + +static int rttm_cpu_starting(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&rttm_to, cpu); + + RTTM_DEBUG(to->of_base.base); + to->clkevt.cpumask = cpumask_of(cpu); + irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask); + clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC, + RTTM_MIN_DELTA, RTTM_MAX_DELTA); + rttm_enable_irq(to->of_base.base); + + return 0; +} + +static int __init rttm_probe(struct device_node *np) +{ + unsigned int cpu, cpu_rollback; + struct timer_of *to; + unsigned int clkidx = num_possible_cpus(); + + /* Use the first n timers as per CPU clock event generators */ + for_each_possible_cpu(cpu) { + to = per_cpu_ptr(&rttm_to, cpu); + to->of_irq.index = to->of_base.index = cpu; + if (timer_of_init(np, to)) { + pr_err("setup of timer %d failed\n", cpu); + goto rollback; + } + rttm_setup_timer(to->of_base.base); + } + + /* Activate the n'th + 1 timer as a stable CPU clocksource. */ + to = &rttm_cs.to; + to->of_base.index = clkidx; + timer_of_init(np, to); + if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) { + rttm_enable_clocksource(&rttm_cs.cs); + clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC); + sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC); + } else + pr_err(" setup of timer %d as clocksource failed", clkidx); + + return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING, + "timer/realtek:online", + rttm_cpu_starting, NULL); +rollback: + pr_err("timer registration failed\n"); + for_each_possible_cpu(cpu_rollback) { + if (cpu_rollback == cpu) + break; + to = per_cpu_ptr(&rttm_to, cpu_rollback); + timer_of_cleanup(to); + } + + return -EINVAL; +} + +TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 7a5785f405b6..56b744dc1317 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -171,6 +171,7 @@ enum cpuhp_state { CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, CPUHP_AP_ARC_TIMER_STARTING, + CPUHP_AP_REALTEK_TIMER_STARTING, CPUHP_AP_RISCV_TIMER_STARTING, CPUHP_AP_CLINT_TIMER_STARTING, CPUHP_AP_CSKY_TIMER_STARTING, From patchwork Fri Jul 5 02:15:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724328 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2256F1E880 for ; Fri, 5 Jul 2024 02:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; 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Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 9550C13EE85; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 92A88280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 8/9] mips: generic: add fdt fixup for Realtek reference board Date: Fri, 5 Jul 2024 14:15:19 +1200 Message-ID: <20240705021520.2737568-9-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=x-EMvBfK1kxHbq4Brr4A:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat The bootloader used on the Realtek RTL9302C boards is an ancient vendor fork of U-Boot that doesn't understand device trees. So to run a modern kernel it is necessary use one of the APPENDED_DTB options. When appending the DTB the inintrd information, if present, needs to be inserted into the /chosen device tree node. The bootloader provides the initrd start/size via the firmware environment. Add a fdt fixup that will update the device tree with the initrd information. Signed-off-by: Chris Packham --- Notes: Changes in v4: - use correct compatible string - include printk.h - remove unnecessary include of of_address.h - put realtek_of_match entry on one line - one piece of feedback not addressed is whether this fixup is required on more platforms. I don't have a supply of other mips platforms to check so I can't confirm. It should be relatively easy to move realtek_add_initrd() to a more generic place, boards could then opt in to it with the existing apply_mips_fdt_fixups() mechanism. Changes in v3: - None Changes in v2: - update compatible string arch/mips/generic/Makefile | 1 + arch/mips/generic/board-realtek.c | 79 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 arch/mips/generic/board-realtek.c diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile index 56011d738441..ea0e4ad5e600 100644 --- a/arch/mips/generic/Makefile +++ b/arch/mips/generic/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o obj-$(CONFIG_MACH_INGENIC) += board-ingenic.o obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o +obj-$(CONFIG_MACH_REALTEK_RTL) += board-realtek.o diff --git a/arch/mips/generic/board-realtek.c b/arch/mips/generic/board-realtek.c new file mode 100644 index 000000000000..9cce6103d24e --- /dev/null +++ b/arch/mips/generic/board-realtek.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Allied Telesis + */ + +#include +#include +#include +#include + +#include +#include + +static __init int realtek_add_initrd(void *fdt) +{ + int node, err; + u32 start, size; + + node = fdt_path_offset(fdt, "/chosen"); + if (node < 0) { + pr_err("/chosen node not found\n"); + return -ENOENT; + } + + start = fw_getenvl("initrd_start"); + size = fw_getenvl("initrd_size"); + + if (start == 0 && size == 0) + return 0; + + pr_info("Adding initrd info from environment\n"); + + err = fdt_setprop_u32(fdt, node, "linux,initrd-start", start); + if (err) { + pr_err("unable to set initrd-start: %d\n", err); + return err; + } + + err = fdt_setprop_u32(fdt, node, "linux,initrd-end", start + size); + if (err) { + pr_err("unable to set initrd-end: %d\n", err); + return err; + } + + return 0; +} + +static const struct mips_fdt_fixup realtek_fdt_fixups[] __initconst = { + { realtek_add_initrd, "add initrd" }, + {}, +}; + +static __init const void *realtek_fixup_fdt(const void *fdt, const void *match_data) +{ + static unsigned char fdt_buf[16 << 10] __initdata; + int err; + + if (fdt_check_header(fdt)) + panic("Corrupt DT"); + + fw_init_cmdline(); + + err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf), fdt, realtek_fdt_fixups); + if (err) + panic("Unable to fixup FDT: %d", err); + + return fdt_buf; + +} + +static const struct of_device_id realtek_of_match[] __initconst = { + { .compatible = "realtek,rtl9302-soc" }, + {} +}; + +MIPS_MACHINE(realtek) = { + .matches = realtek_of_match, + .fixup_fdt = realtek_fixup_fdt, +}; From patchwork Fri Jul 5 02:15:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13724331 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56A32225AE for ; Fri, 5 Jul 2024 02:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720145741; cv=none; b=Q7ug6qLmJk00Pm5uF2BWicCP0Al2KjIdUSrcIgavWh+2zgQmNYJIo3irbnQgj1VtHyM4vtyziVNVqwhyfYJkVCHi9uYVvCKy+HrRULHOK6KfgX/303IyNg3+SnZ4Esx0iLQ2dxDDfUccQLDMoP1LbwVHW2fGHSmyKgZdk4Ca5+I= ARC-Message-Signature: i=1; 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Fri, 5 Jul 2024 14:15:28 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1720145728; bh=AaoonlzQY7AjfYhYyuw1OGQjwznAzBKn4fTqEmrnqps=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WWoN9k0CTqwAGlMkxT5K+6upyTB9VS9sQZofKeYH2981NN7AEv0lu8BUY0H9mLYfk qwgEILicMjITe2i7pXsoaNaNwSoxACIgCNw5rMmj/iQWj5ULtFiPiUHFYjomvWIyGj GDI3Ak+3rMHgH9jPdM9pYdHrrKf1hioxS339IVcwizd17rqTk+zCtTuv/xdqh4DQnd lNmHjwerYA3L3EBsp98H7XLHJbORNO/dvDtniQWtjrcth3r/bigqz7gQSluytQg8/l qdK3tlkia2k6259sL4YIBouloHBQgaj4i9Yay3CLx4aMsd6RatiUPyQO5lNw885OzO DUHDTmbJX1dVg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 05 Jul 2024 14:15:26 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 9A94913EE87; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 97D69280930; Fri, 5 Jul 2024 14:15:26 +1200 (NZST) From: Chris Packham To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, tsbogend@alpha.franken.de, daniel.lezcano@linaro.org, paulburton@kernel.org, peterz@infradead.org, mail@birger-koblitz.de, bert@biot.com, john@phrozen.org, sander@svanheule.net Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, kabel@kernel.org, ericwouds@gmail.com, Chris Packham Subject: [PATCH v4 9/9] mips: dts: realtek: Add RTL9302C board Date: Fri, 5 Jul 2024 14:15:20 +1200 Message-ID: <20240705021520.2737568-10-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> References: <20240705021520.2737568-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=CvQccW4D c=1 sm=1 tr=0 ts=6687573e a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=jdP34snFAAAA:8 a=KBD_zhYaegNxfykauC4A:9 a=3ZKOabzyN94A:10 a=jlphF6vWLdwq7oh3TaWq:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE reference board. The RTL930x family of SoCs are Realtek switches with an embedded MIPS core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x SoC and can make use of many existing drivers. Add in full DSA switch support is still a work in progress. Signed-off-by: Chris Packham --- Notes: Changes in v4: - None Changes in v3: - Use full board name Changes in v2: - Use specific compatibles instead of rtl930x - Remove unnecessary irq flags (interrupt controller is one-cell) - Remove earlycon - Name clocks as recommended in dt schema Changes in v2: - Use specific compatible for rtl9302-soc - Fix to allow correct board, soc compatible This is derrived from openwrt[1],[2]. I've retained the original signoff and added my own. [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob_plain;f=target/linux/realtek/files-5.15/drivers/clocksource/timer-rtl-otto.c;hb=HEAD [2] https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob_plain;f=target/linux/realtek/patches-5.15/302-clocksource-add-otto-driver.patch;hb=HEAD Changes in v3: - Remove unnecessary select COMMON_CLK - Use %p when printing pointer Changes in v2 - None Changes in v3: - Use full board name Changes in v2: - Use specific compatibles instead of rtl930x - Remove unnecessary irq flags (interrupt controller is one-cell) - Remove earlycon - Name clocks as recommended in dt schema arch/mips/boot/dts/realtek/Makefile | 1 + .../cameo-rtl9302c-2x-rtl8224-2xge.dts | 73 +++++++++++++++++ arch/mips/boot/dts/realtek/rtl930x.dtsi | 79 +++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts create mode 100644 arch/mips/boot/dts/realtek/rtl930x.dtsi diff --git a/arch/mips/boot/dts/realtek/Makefile b/arch/mips/boot/dts/realtek/Makefile index fba4e93187a6..d2709798763f 100644 --- a/arch/mips/boot/dts/realtek/Makefile +++ b/arch/mips/boot/dts/realtek/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-y += cisco_sg220-26.dtb +dtb-y += cameo-rtl9302c-2x-rtl8224-2xge.dtb diff --git a/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts new file mode 100644 index 000000000000..b51e10ae4950 --- /dev/null +++ b/arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl930x.dtsi" + +#include +#include +#include +#include + +/ { + compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc"; + model = "RTL9302C Development Board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0xe0000>; + read-only; + }; + partition@e0000 { + label = "u-boot-env"; + reg = <0xe0000 0x10000>; + }; + partition@f0000 { + label = "u-boot-env2"; + reg = <0xf0000 0x10000>; + read-only; + }; + partition@100000 { + label = "jffs"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "jffs2"; + reg = <0x200000 0x100000>; + }; + partition@300000 { + label = "runtime"; + reg = <0x300000 0xe80000>; + }; + partition@1180000 { + label = "runtime2"; + reg = <0x1180000 0xe80000>; + }; + }; + }; +}; diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi new file mode 100644 index 000000000000..f271940f82be --- /dev/null +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause + +#include "rtl83xx.dtsi" + +/ { + compatible = "realtek,rtl9302-soc"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips34Kc"; + reg = <0>; + clocks = <&baseclk 0>; + clock-names = "cpu"; + }; + }; + + baseclk: clock-800mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + }; + + lx_clk: clock-175mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <175000000>; + }; +}; + +&soc { + intc: interrupt-controller@3000 { + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; + reg = <0x3000 0x18>, <0x3018 0x18>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; + }; + + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + timer0: timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; + + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; +}; + +&uart0 { + /delete-property/ clock-frequency; + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <30>; +}; + +&uart1 { + /delete-property/ clock-frequency; + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; +}; +