From patchwork Mon Jul 8 15:44:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726742 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01337143729; Mon, 8 Jul 2024 15:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=qstOUUuc6n6CLWZG6iXPA/dcda/BA2wW6dxjZCYsprvBLDZRSpqJ4lJfmsijxiw6naRhS/eQLLL1n6qhoJJQ5WG5GP8zPsSokDC3JyD0SHY0autlzKSMBi8k6rfy9RbUk94ObtlRg0qAsPEQOEe8XqxSD1ofkEqxd9uET1DImAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=z+XPKWi16ciRyxOZ+JoGHM1luReodmKcD3K070W/iM0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hoUEA7ah6hAd/ccRNYxWxV2sJJ8Esvn4c4/+jhsXsiw/O7DcMuygX1GLiFNZNgCOf/GD68gSiLKe00tj5s9EmaNdeLbfoqg+CNjV5W06m7s4VisToTxXWhaSDDvvXUD6fGAXWh6/wB0oA12RRTlSALeG61nZtQsV2THJRc1/R+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eM2Lm+0T; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eM2Lm+0T" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A536C116B1; Mon, 8 Jul 2024 15:44:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453494; bh=z+XPKWi16ciRyxOZ+JoGHM1luReodmKcD3K070W/iM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eM2Lm+0T9sDaXxYc64rGyTgOqgCVKgHzPAPV0Abww0GRMVvBgfmh9a3TpIpJLhhXZ 0qLhfpqfvWVD0RLQX4Vj6nVh+jD3MuG3rW2+zLEUesS6z8/N3M3W2QP6Nz3dn3TU6p ZtXA8X8ymgliMvFUVu5xlRzj2kdK3nMdJuDZVwUamxw0jz+8j6u/6c0/ex7wPZH7oa oSKyBBAp+u/5sZ6O+sZgUD7BtT3MILDIzC+LGe8bw7g7HQ15v10Jb0xpypI9qbiPeS cdif+VCclm+Kr3k3AMNqWP7dm9oxEoC6V6p4cqMDSuQOq2mWC425jW4sTIa7IoTOfy /ZOa6mfWscL6g== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXs-00Ae1P-Hk; Mon, 08 Jul 2024 16:44:52 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 1/7] KVM: arm64: Move SVCR into the sysreg array Date: Mon, 8 Jul 2024 16:44:32 +0100 Message-Id: <20240708154438.1218186-2-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false SVCR is just a system register, and has no purpose being outside of the sysreg array. If anything, it only makes it more difficult to eventually support SME one day. If ever. Move it into the array with its little friends, and associate it with a visibility predicate. Although this is dead code, it at least paves the way for the next set of FP-related extensions. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 4 +++- arch/arm64/kvm/fpsimd.c | 2 +- arch/arm64/kvm/sys_regs.c | 11 ++++++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 25a3b72fbacf2..0b3d7697ca0a7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -446,6 +446,9 @@ enum vcpu_sysreg { GCR_EL1, /* Tag Control Register */ TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ + /* FP/SIMD/SVE */ + SVCR, + /* 32bit specific registers. */ DACR32_EL2, /* Domain Access Control Register */ IFSR32_EL2, /* Instruction Fault Status Register */ @@ -664,7 +667,6 @@ struct kvm_vcpu_arch { void *sve_state; enum fp_type fp_type; unsigned int sve_max_vl; - u64 svcr; u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index c53e5b14038dc..e6425414d301f 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -134,7 +134,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_state = vcpu->arch.sve_state; fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; - fp_state.svcr = &vcpu->arch.svcr; + fp_state.svcr = &__vcpu_sys_reg(vcpu, SVCR); fp_state.fpmr = &vcpu->arch.fpmr; fp_state.fp_type = &vcpu->arch.fp_type; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c90324060436b..2dc6cab43b2f8 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1669,6 +1669,15 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, return REG_HIDDEN; } +static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) + return 0; + + return REG_HIDDEN; +} + static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2535,7 +2544,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { CTR_EL0_IDC_MASK | CTR_EL0_DminLine_MASK | CTR_EL0_IminLine_MASK), - { SYS_DESC(SYS_SVCR), undef_access }, + { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, From patchwork Mon Jul 8 15:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726744 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 012AD1422CA; Mon, 8 Jul 2024 15:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=A9Pn8/Bh5zLN6VLzsj//hYIuUyp2hEnT4+sjVlKdiy/GJU1DOcf8cEfbNY69+CRG7dgp+AwTiJCjs1wzrT5dLCSQq0nxbVoeKF2hndlx4i0cg3FFyfCqALr4duaR6PQkqmiszk62eo6Uy4v6bY4syv5FyXzCSVUX4u6mXPEeL3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=iFWcrgnnLVyozv323EWmLqXVQmcY+xMWCYUY9LRYxjs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BP80wbYNyPD/kW3J1PXf+jfzj3b7XNHgJAQdL9oJW+DLHvlXW2Xadu4vFGWIZ+FsGpv1Q4o4CPbpsRqgffTovb/vpD4q2uYPtDWlu2BwpiFf3Z7NN+c4TCezdX8hxWLy4ymVhfEiK6spEEfHIxjv02UvOS/VcRoSUt4shx36Vdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XKz2zPN+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XKz2zPN+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A56CC32786; Mon, 8 Jul 2024 15:44:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453494; bh=iFWcrgnnLVyozv323EWmLqXVQmcY+xMWCYUY9LRYxjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XKz2zPN+vPcCH67ovDxSFL6OpG2f86/OM9Xo5c3U6TJzZwtEgfAOX83JVRGXqI2ky wh3DicfoZwDxI+ziJQnB1oJUU7gg/OVjeLLSPrqfauo2REzOfdOf7KaUWqjMqirWIV S6DG54LTYqfEeT49tm9G2Fm6CRvFazsKMsU9LRN82GnAtRcnqvyKaJuFc8XVm0Fa5y 5ZFzeN00V/H+My/dd63QRJioSoE51bAXLYLPbk0udH+QUAbc3nR44ZILKHS/Q7LlRt naJmtkvzvyHRqL+CKywml44rJ/prl5NEk4fnI+kYc8+GNyGdw6DvasShABpiV8EuIm IinGCKI8l5+WQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXs-00Ae1P-QA; Mon, 08 Jul 2024 16:44:52 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 2/7] KVM: arm64: Move FPMR into the sysreg array Date: Mon, 8 Jul 2024 16:44:33 +0100 Message-Id: <20240708154438.1218186-3-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Just like SVCR, FPMR is currently stored at the wrong location. Let's move it where it belongs. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/kvm/fpsimd.c | 2 +- arch/arm64/kvm/sys_regs.c | 10 ++++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0b3d7697ca0a7..a14c18e8b173a 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -448,6 +448,7 @@ enum vcpu_sysreg { /* FP/SIMD/SVE */ SVCR, + FPMR, /* 32bit specific registers. */ DACR32_EL2, /* Domain Access Control Register */ @@ -667,7 +668,6 @@ struct kvm_vcpu_arch { void *sve_state; enum fp_type fp_type; unsigned int sve_max_vl; - u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index e6425414d301f..4cb8ad5d69a80 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -135,7 +135,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &__vcpu_sys_reg(vcpu, SVCR); - fp_state.fpmr = &vcpu->arch.fpmr; + fp_state.fpmr = &__vcpu_sys_reg(vcpu, FPMR); fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2dc6cab43b2f8..326262abc2ff4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1678,6 +1678,15 @@ static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, return REG_HIDDEN; } +static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (kvm_has_feat(vcpu->kvm, ID_AA64PFR2_EL1, FPMR, IMP)) + return 0; + + return REG_HIDDEN; +} + static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2545,6 +2554,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { CTR_EL0_DminLine_MASK | CTR_EL0_IminLine_MASK), { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, + { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, From patchwork Mon Jul 8 15:44:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726746 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F074143C45; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=A0xjE23VXgCzpFTh0+ghW6sqf1C1MuUiauxtZmXRt04dDz3AgWl/8GlnVzZ2as3QSu+533wIXCBGpVvA+MV4ZzgBjPTlukb6MMYVEUW3AxKSo3T1VhMUVF8305XUyxsszWjsXDNH0F5cj8q0Ym2Yxe0NkM52Y+BFeHIiSqVfw0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=D8Xbgc7QO/XpodPOM7J+nYMvERnS5AGZFqZ3iGgsOI8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DOdfPNyV6R7/rtMLSOcUisBxhQObnhPcBDz/+lX59cu21fcOJd+D9N+LoSdBndOJV0aWo2JCgv71Hv48THppK4LuWiHeMPbHxNEw/jRpkUwOu8aTyNM5Vohj1OnvpIER+qDBUgACnjG5e3qH+yvNv/aMjA41YIBm2fETGQWuwOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sy+dVDPZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sy+dVDPZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F4CBC4AF0E; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453495; bh=D8Xbgc7QO/XpodPOM7J+nYMvERnS5AGZFqZ3iGgsOI8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sy+dVDPZuObk3y6KRA2ju03xHq6CjPmdWBMsw4WfVH1PsdpAahgW+4AwT0gcYV5Pp +DlXI6AV+vKec+cdXoNuDOT5giGR/Nz0XKYStFIz+IDX5HkI35I3AHcbr/RM4TzH8B 5InaSad+TtFVJD79Uj32s3doF597kJ3e0xJ/QK7eODnUYnYghnzc+XAmZ4Y90bRs9J LMNvNsj8amZtv3Ib/dkREKfXWyog+lsO/7woOWcEdQbnRu9L9rh4qJhT/JFr8KT1CG OPaIBuC4P38q3OVB3XUxbcF+975CpBu2zGwH0V4HM2PxDaH+Mcmd+0oK/JJ6F5qo0W CpwHKLV+NYx0A== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXt-00Ae1P-1A; Mon, 08 Jul 2024 16:44:53 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 3/7] KVM: arm64: Add save/restore support for FPMR Date: Mon, 8 Jul 2024 16:44:34 +0100 Message-Id: <20240708154438.1218186-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Just like the rest of the FP/SIMD state, FPMR needs to be context switched. The only interesting thing here is that we need to treat the pKVM part a bit differently, as the host FP state is never written back to the vcpu thread, but instead stored locally and eagerly restored. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 10 ++++++++++ arch/arm64/kvm/fpsimd.c | 1 + arch/arm64/kvm/hyp/nvhe/hyp-main.c | 4 ++++ arch/arm64/kvm/hyp/nvhe/switch.c | 10 ++++++++++ arch/arm64/kvm/hyp/vhe/switch.c | 4 ++++ 5 files changed, 29 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a14c18e8b173a..764d23082eb91 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -599,6 +599,16 @@ struct kvm_host_data { struct cpu_sve_state *sve_state; }; + union { + /* HYP VA pointer to the host storage for FPMR */ + u64 *fpmr_ptr; + /* + * Used by pKVM only, as it needs to provide storage + * for the host + */ + u64 fpmr; + }; + /* Ownership of the FP regs */ enum { FP_STATE_FREE, diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 4cb8ad5d69a80..ea5484ce1f3ba 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -63,6 +63,7 @@ void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) */ *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; *host_data_ptr(fpsimd_state) = kern_hyp_va(¤t->thread.uw.fpsimd_state); + *host_data_ptr(fpmr_ptr) = kern_hyp_va(¤t->thread.uw.fpmr); vcpu_clear_flag(vcpu, HOST_SVE_ENABLED); if (read_sysreg(cpacr_el1) & CPACR_EL1_ZEN_EL0EN) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index f43d845f3c4ec..6b14a2c13e287 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -78,6 +78,10 @@ static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) else __fpsimd_restore_state(*host_data_ptr(fpsimd_state)); + if (system_supports_fpmr() && + kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR2_EL1, FPMR, IMP)) + write_sysreg_s(*host_data_ptr(fpmr), SYS_FPMR); + *host_data_ptr(fp_owner) = FP_STATE_HOST_OWNED; } diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index 6af179c6356d6..47d24ecd68fec 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -198,6 +198,16 @@ static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu) } else { __fpsimd_save_state(*host_data_ptr(fpsimd_state)); } + + if (system_supports_fpmr() && + kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR2_EL1, FPMR, IMP)) { + u64 fpmr = read_sysreg_s(SYS_FPMR); + + if (unlikely(is_protected_kvm_enabled())) + *host_data_ptr(fpmr) = fpmr; + else + **host_data_ptr(fpmr_ptr) = fpmr; + } } static const exit_handler_fn hyp_exit_handlers[] = { diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 77010b76c150f..a307c1d5ac874 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -312,6 +312,10 @@ static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code) static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu) { __fpsimd_save_state(*host_data_ptr(fpsimd_state)); + + if (system_supports_fpmr() && + kvm_has_feat(vcpu->kvm, ID_AA64PFR2_EL1, FPMR, IMP)) + **host_data_ptr(fpmr_ptr) = read_sysreg_s(SYS_FPMR); } static bool kvm_hyp_handle_tlbi_el2(struct kvm_vcpu *vcpu, u64 *exit_code) From patchwork Mon Jul 8 15:44:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726745 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F0B9143C47; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=SysbrIj0rm+2pred6jVpGZFUALdHkJa4KLpvFP8LVzX/odaeeFGjE3OKzwB8hLFUwEfK9etoPWgCzlaaCLxc4UMORRtH2auj04j4Uj7ssablQqaC4l0qUsLmtlLhoe237L2Xlf6YEsIuQV0g7visyGjXIIYFT/29EMFgCHmq1O4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=1eMOdbXNYwvJnyM8pmY0Pmrc14+KgT3XcJYTFkP+K5s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f1kNMKuBRiAeCij7bPx5FSoTKAPZlKJaiWW0i3IBteJSbTh8W1DelynEonHmalh/zVFuHffX2yongjxpobqGemqHE5cxE7KOVOMXoYrtbP8rqLLM+NDditdC2vl2n5AR+NTtoX4yUL8Grh40zYI2ShSLZZu9+q90y/khTnRCa+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KsY6F0gR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KsY6F0gR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20163C4AF0F; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453495; bh=1eMOdbXNYwvJnyM8pmY0Pmrc14+KgT3XcJYTFkP+K5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KsY6F0gRaieUN2Gtu6D1YxODI+vTcdhocQszJrTmSpfdqe8O99gJytex6ywSlqV8J nYnpBktaQsJTWtCipObPZfhTr6p2jLOgLuiEXct5E2MUBJ6jAxYvR0fhekTiRa/S17 GMO2E7gBuqRZd27MFHawKaQ1N1XTLMLXivw1YCoBRKZz7XA/w6eyyqMr7ZVMj2a9jN p/rNDdJ3XSGyZteBYA1xo1Q2Dn/dP6QrcqGk8Vr2ZIEdITwD6I41nph8ZD2lbIrpZq fux4+IPAXSpBVFg4RNemb7fpHS5P+5x3l79b88eaGniUvQsi8JdfLTJAbXr2X6P1Ry AI8EXiZsGWtTA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXt-00Ae1P-8S; Mon, 08 Jul 2024 16:44:53 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 4/7] KVM: arm64: Honor trap routing for FPMR Date: Mon, 8 Jul 2024 16:44:35 +0100 Message-Id: <20240708154438.1218186-5-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false HCRX_EL2.EnFPM controls the trapping of FPMR (as well as the validity of any FP8 instruction, but we don't really care about this last part). Describe the trap bit so that the exception can be reinjected in a NV guest. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/emulate-nested.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index 05166eccea0a6..ee280239f14f4 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -83,6 +83,7 @@ enum cgt_group_id { CGT_CPTR_TAM, CGT_CPTR_TCPAC, + CGT_HCRX_EnFPM, CGT_HCRX_TCR2En, /* @@ -372,6 +373,12 @@ static const struct trap_bits coarse_trap_bits[] = { .mask = CPTR_EL2_TCPAC, .behaviour = BEHAVE_FORWARD_ANY, }, + [CGT_HCRX_EnFPM] = { + .index = HCRX_EL2, + .value = 0, + .mask = HCRX_EL2_EnFPM, + .behaviour = BEHAVE_FORWARD_ANY, + }, [CGT_HCRX_TCR2En] = { .index = HCRX_EL2, .value = 0, @@ -1108,6 +1115,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN), SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN), SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN), + SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM), }; static DEFINE_XARRAY(sr_forward_xa); From patchwork Mon Jul 8 15:44:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726747 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C99B2144D25; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=c6P5SRPZLUlK0qbucPn5HJGbRhLwH9/VaPGrML7R1V/BbatGpgRpExTywSOEo+pB8JhcRsd7cy82PvFjWRCn6wJWzF1VH8RI5iQa+QjrvR5VYBzkc9YPuOK5Gdnx7zlrl6xCfWOLw+FtxQh5lXBPQRUbXBhcUOn8GrS8Bsz1OlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=TgBIaQlXHfAb7OU3eNgvMSbHhAj0/iNzDpujav5PLFM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=W8JKJzDFeW4x43HrWgfUDjtrfv8OwN+LPAC4+vRXkjB3kf8Av2w4A+6Quj6bYIFf6GX/hK3rOBrHRjaxWCC5pCCxcezPBvrU0/XWV6n/ipvmPW/Stox0IUUXTzlrKeJA6WPvWsoBAcbN7CfQEXx/jtiZhuRJeG5b0Eam2nRkX8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EU7PGTxV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EU7PGTxV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C793C4AF10; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453495; bh=TgBIaQlXHfAb7OU3eNgvMSbHhAj0/iNzDpujav5PLFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EU7PGTxV4EvkB6ybPZ4lWM71Lfk3cDNCFW/ciUREVCufJGnkCIcEabcbnZSAGOf6w 28eXcF8ALvNLlLtdP7YeCEBkPXVKPbg6sX/MMPPLv21UBRLfMAJXLTSC9+SMQ0zZlh QoeMiLkm4DI6Cx/I4kNRHkiwBW+6Tmt0uiSCrYxQDClfPBOVapia7wVtWrKB061A2i B9ItxYKN9Pn5hFMhIaaYuoqlAbgu3WwC97Tr+3fHH1jXV0AxKt/elo+GET/a+/Z6xD 2/SpW8FZ3/khoPjsd0D9TqUnHVFwdRqpuks0U0Jy9s8YjJKlGi3Tq7OxdBoW6RyJSv KksgZZzbaRLDQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXt-00Ae1P-Fk; Mon, 08 Jul 2024 16:44:53 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 5/7] KVM: arm64: Expose ID_AA64FPFR0_EL1 as a writable ID reg Date: Mon, 8 Jul 2024 16:44:36 +0100 Message-Id: <20240708154438.1218186-6-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false ID_AA64FPFR0_EL1 contains all sort of bits that contain a description of which FP8 subfeatures are implemented. We don't really care about them, so let's just expose that register and allow userspace to disable subfeatures at will. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 326262abc2ff4..1157c38568e22 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2386,7 +2386,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), + ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), /* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), From patchwork Mon Jul 8 15:44:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726748 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C99F6144D29; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=M2bbT4D694OSIGVKo8FYhmCCLXhtSfP5B62ccccBiZO6+u2LXOBFNuM6ugtnu27aRLCuwyqeqnyfEIke3LaeY55ZnpglVeJKL0ll59MQdW2b7w5IsUQ6PkJW6epJehn5F3EhsqeCcu0/IxrRELBm+1NSAeJWYFSHuPpGrxE6e68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=JsX6GaTs7Vi33NMLLUOYXeMXmeUqBGTgNLnsPE11cdk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T7xWtJ5adeoaE+3tUWW9j0B3YILxLWbS+EG3yRRLoH+Z2NSrlzzXB0G4M0vuEFIBAAS3qNBsopMC+vpnwa9rGEScTbMTDzcIBH9oKWWh+6RuXHIEmnPuCR1gSORk4Br/PRakt8XO5jXbbymaQQJvds/z626SabKm99rLV/qsxpc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bu/8PvUP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bu/8PvUP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 784E2C4AF0C; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453495; bh=JsX6GaTs7Vi33NMLLUOYXeMXmeUqBGTgNLnsPE11cdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bu/8PvUPlZ22Q8ni+39V+88hKotMKO8bpsopdo9VWOJ6cRSEWTu+Ek8TaMlSlgKoL bBcm6a43DAmETjnZ7lRXve8My8WCE1d2vXG7tvcGoaCM2RVTBCYgYQjO+q1vYnADJB JRdcrqSWO5dBPE7F3/7VlrZ/Vr5wrGLb/tIHs3zYMfSVnFbjgW3+GktLzC/LWPW5p7 aCxmqiCEokHMD8U1+b9HPKwyyivQyEHfsnsXuQYMFo9eJDx7NcbJe3gk6SDL3EB6Xw adRzC3XDdmzef+8v81ZDEPhN5/bzaSJ9c9n3UHA3IGgRhSQ+LUw7ABklA58Bblqns8 789UgnzLOYMEw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXt-00Ae1P-NS; Mon, 08 Jul 2024 16:44:53 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 6/7] KVM: arm64: Enable FP8 support when available and configured Date: Mon, 8 Jul 2024 16:44:37 +0100 Message-Id: <20240708154438.1218186-7-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false If userspace has enabled FP8 support (by setting ID_AA64PFR2_EL1.FPMR to 1), let's enable the feature by setting HCRX_EL2.EnFPM for the vcpu. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1157c38568e22..8b5caad651512 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4579,6 +4579,9 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; + + if (kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP)) + vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; } if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) From patchwork Mon Jul 8 15:44:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13726749 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB26A14532B; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; cv=none; b=Eg69t7uzSnI5XJ0pT2kAhubdaTx1+32SOLWzX4Fwx8s0cAEoQiFkBq/Mosfi4iaMr91PDUqjxHv5r95WY8xqXhUFUcm+BMCOUSb+DPEGjoU6AhXoRoWA7k0x4LJsIGUwVfF44dm9rD71BlROHXGx6eAXLTZHLkBu2doQQfg9sHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720453495; c=relaxed/simple; bh=Uv0z9ntISDWqUONsGZqFUTjAheaQ1E1mlpLqi6+ng6M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BynuGTs8iSUiU+RVD8htGxnuC2HzJT2Y+u+/921qAJ0E0b3lVUAbDGfHx3tsBmoflWGXHI+mkEtSW3uVZTKgSQSs8pKututBY5XueK8h5JYSQvpF71sO6NEGjuLadG8Qn6KRO/BGTvQWKbyKpQpXzCzrOAvf9BCey9LfPC65QDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vRyoxTCQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vRyoxTCQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B358FC4AF11; Mon, 8 Jul 2024 15:44:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720453495; bh=Uv0z9ntISDWqUONsGZqFUTjAheaQ1E1mlpLqi6+ng6M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vRyoxTCQSNWbyMYEHSAdVp0bBfgm63kTrCTK4sKrZ7D1jt0sYg0AieQ968QNw9AyI J+/A4sLDMwriiaD/2MtU2sRGwj3uwSoGx25+4XdiihXQ8evspg2dOCf6ymS6PFi6bu k4/4p6OgE1KwtIVLCZpBg6WEXnoZ7bzi43aGf0aV1LTRtyIRdpWKVr5ZJqnXCGBiSm gyNtclQmEtfCPchp6aAw5Ydlpt1KOIGfPl5m4kgyEM2eCfvtbTNf/E2uz3gL7U6Xmr 0kKBejlDN8pZpvqW1Jbtu3WdI0r+HpZJcTOuNjYYn8zsf85U30ohPXjLAzfBLuZbSm nvPaGr0BT/CSw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sQqXt-00Ae1P-Ua; Mon, 08 Jul 2024 16:44:54 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Joey Gouly , Mark Brown Subject: [PATCH 7/7] KVM: arm64: Expose ID_AA64PFR2_EL1 to userspace and guests Date: Mon, 8 Jul 2024 16:44:38 +0100 Message-Id: <20240708154438.1218186-8-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240708154438.1218186-1-maz@kernel.org> References: <20240708154438.1218186-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, tabba@google.com, joey.gouly@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Everything is now in place for a guest to "enjoy" FP8 support. Expose ID_AA64PFR2_EL1 to both userspace and guests, with the explicit restriction of only being able to clear FPMR. All other features (MTE* at the time of writing) are hidden and not writable. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8b5caad651512..e6f9e380283ea 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1722,6 +1722,15 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +static u64 read_sanitised_id_aa64pfr2_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR2_EL1); + + /* We only expose FPMR */ + return val & ID_AA64PFR2_EL1_FPMR; +} + #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ ({ \ u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ @@ -2381,7 +2390,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64PFR0_EL1_AdvSIMD | ID_AA64PFR0_EL1_FP), }, ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), + { SYS_DESC(SYS_ID_AA64PFR2_EL1), + .access = access_id_reg, + .get_user = get_id_reg, + .set_user = set_id_reg, + .reset = read_sanitised_id_aa64pfr2_el1, + .val = ID_AA64PFR2_EL1_FPMR, }, ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), ID_HIDDEN(ID_AA64SMFR0_EL1),