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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4y16WC5k3Hf3Ro46jzSWnkW6tChByvXuSCOU55d3f/oJvO9CawX+o4K7pUbdn64cl4xstKa6fDNP7nA1D1ZHwyXkr4YzMzMFiSmL5tLkJCLpHwP8phim8EbDo9JML7ciCAxccrLSRqfiNiU8u6Q2FoAopJ/4Ty0QVFB/qJAfP9EttiZYcBiCOaTUP2nFYLQeC/9cFSSbxcTG1MjThFZ5WQ3mDhjrVOcduLUg1IPWCrSnTPnONKwSNFCVHWXQRUpfjbqQcDl+3eAtDCxMl5948i/xjwMkgPkCPK/v5XLvkeFkKtw6SX389QTyy22r/fZCuPVQ87Jwsa25ngzYMZuFC3dvOG7Im6n/6fM6IzQ5GsvcMxA+t+qMBZHFjgvdDxfrAH0KQpiO4iTKs+jiNmn7fLzuGlEmoD+7WTMqklKjOrlgjSTADUyy4HjGZ0uCdMwzkX8qkKQvsMPqOnO04rfxMx2pRbaBHxNnfnVTWo4gEhtBDFWDrRXOpeF7y+4CeEq3+YFxSNLLFqsSNNZfS3yWpxojRxf5hb/3wEERnWBGVFccWJpdLMOIwxi5wmJHj4PKOpZ6Q8KFv6mwqlwb+x7ND1osBZMO0mpBUJjOnucoZ4TwiNEiJ1MTQXFrF5iH8pOhgrd53WuS0MeO13nKIVlDLlXacegdFGhbjZiub4ThdYNyBtdR8WJ0TQ/Qc86cjzkZqBzD1znxGx/uetz7Y85r7jt/mxijj+hXXZu8e9N0sMXr7HIpaZGDO5Gklijx5WoKi86vrFmLxYgRmaMkEVt701ugOIHzZ8FzGcOFSxxbgXn153vKByRaJxpqy+cSHc/EDj4Zcegjt3D5UlFz4EPdrK2SnLk0L0hChxDYn7C4jA3xdSR2p2ksMGBXQFct7xo/7CPuvXC2UieTXwMBSQoXk+J9zSkD/joCGGPhZjVu33fswMit+KLLc/to0ftqauqLlmpfYVKTNaLukWOsk50oprVZTdeKkeMktA7TUcFjDJQIblSQ7R6w9VseqsdVjKsv60Q9Hoi6JBN/Bch+8OumkpBjV/phS2ZsulN11JYj3ysO17TR8vGxoPq2vNQwnYr31wPKMDEWarGp1bpbPsbr6aUnEdHWTnZIB+Kq+Ow2kq1TblK2k0t8GAlfRs7WgzxwOT5P8oTZK+WoU4qF+uAaYyTNCtKQC5VU29o8bFYVO934DE6ERg1odvRF2/YZ5BfwvjVqpIOE9Ebmj3J0XtTnEEWJKYhRCa5MRZE6S7HTE8eOMM+BnybZcf39mCT5rfeGOsKeZMxrkwoCo3XnIrAyc86VTXsHucztyhpVUdxldcR6Tl6QH0V+1K5ERr7hNSFe6fu28eRr8j0PZBHWW6rM/YzXE0e3dH1mEdU2FDE5DfhUD5kXBm+wF06ukaxWafQV7uyv/4+VM70NUTCv3CxAgW5b8bb5+x8+ffRHA3tr/Odeb74R441aosWH3/enSHKoF+3MxR+Cvucs+BOLrtLF2pCz3NdtIrrmf+XN6PsBk2ZgKQhaJKvPI5F/nmIE3Iy4q+Vg8sj9rzQUXfLROi+i02ewZPP9gPZKgtjL5x6O4zZQTum2jqDF0IgMkf1NFiyR X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3c4ddb58-0274-474b-b568-08dca2922476 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2024 16:46:14.1512 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: s8+ELPX7zygIk9+vgeG16+HgJrmXCu1zu5+eFLY3DTb40+9mhNMZ7qwEewVYKt05kAWVDqgNegFaaUJcu3cqNA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8756 From: Carlos Song According to I3C Specification(Version 1.1) 5.1.2.4 "Use of Clock Speed to Prevent Legacy I2C Devices From Seeing I3C traffic", when slow i2c devices(FM/FM+ rate i2c frequency without 50ns filter) works on i3c bus, i3c SDR should work at FM/FM+ rate. Adjust timing for difference mode. Signed-off-by: Clark Wang Signed-off-by: Carlos Song Signed-off-by: Frank Li Acked-by: Miquel Raynal --- drivers/i3c/master/svc-i3c-master.c | 66 +++++++++++++++++------------ 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c index bb299ce02cccb..26dc6d833c6e3 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -127,6 +127,8 @@ /* This parameter depends on the implementation and may be tuned */ #define SVC_I3C_FIFO_SIZE 16 +#define SVC_I3C_PPBAUD_MAX 15 +#define SVC_I3C_QUICK_I2C_CLK 4170000 #define SVC_I3C_EVENT_IBI BIT(0) #define SVC_I3C_EVENT_HOTJOIN BIT(1) @@ -535,6 +537,7 @@ static int svc_i3c_master_bus_init(struct i3c_master_controller *m) struct i3c_bus *bus = i3c_master_get_bus(m); struct i3c_device_info info = {}; unsigned long fclk_rate, fclk_period_ns; + unsigned long i2c_period_ns, i2c_scl_rate, i3c_scl_rate; unsigned int high_period_ns, od_low_period_ns; u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg; int ret; @@ -555,44 +558,55 @@ static int svc_i3c_master_bus_init(struct i3c_master_controller *m) } fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate); - - /* - * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. - * Simplest configuration is using a 50% duty-cycle of 40ns. - */ - ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1; - pplow = 0; - - /* - * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a - * duty-cycle tuned so that high levels are filetered out by - * the 50ns filter (target being 40ns). - */ - odhpp = 1; - high_period_ns = (ppbaud + 1) * fclk_period_ns; - odbaud = DIV_ROUND_UP(240 - high_period_ns, high_period_ns) - 1; - od_low_period_ns = (odbaud + 1) * high_period_ns; + i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c); + i2c_scl_rate = bus->scl_rate.i2c; + i3c_scl_rate = bus->scl_rate.i3c; switch (bus->mode) { case I3C_BUS_MODE_PURE: + /* Using I3C Push-Pull mode and I2C OP 50% duty-cycle. */ + pplow = 0; + ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1; + high_period_ns = (ppbaud + 1) * fclk_period_ns; + odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2; + od_low_period_ns = (odbaud + 1) * high_period_ns; i2cbaud = 0; odstop = 0; break; case I3C_BUS_MODE_MIXED_FAST: - case I3C_BUS_MODE_MIXED_LIMITED: /* - * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference - * between the high and low period does not really matter. + * I3C in <= 12.5M PP + I3C OP + I2C OP in clk rate + * keep I3C OD clk high period <= 40ns and use odbaud and pplow + * to adjust the i2c/i3c duty cycle. */ - i2cbaud = DIV_ROUND_UP(1000, od_low_period_ns) - 2; + ppbaud = DIV_ROUND_UP(fclk_rate / 2, I3C_BUS_TYP_I3C_SCL_RATE) - 1; + high_period_ns = (ppbaud + 1) * fclk_period_ns; + pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud); + + odhpp = 1; + odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2; + + /* i2c FM/FM+ */ + od_low_period_ns = (odbaud + 1) * high_period_ns; + i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; odstop = 1; break; + case I3C_BUS_MODE_MIXED_LIMITED: case I3C_BUS_MODE_MIXED_SLOW: - /* - * Using I2C Fm mode, target is 0.4MHz/2500ns, with the same - * constraints as the FM+ mode. - */ - i2cbaud = DIV_ROUND_UP(2500, od_low_period_ns) - 2; + /* I3C PP + I3C OP + I2C OP both use i2c clk rate */ + ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1; + pplow = 0; + if (ppbaud > SVC_I3C_PPBAUD_MAX) { + ppbaud = SVC_I3C_PPBAUD_MAX; + pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud); + } + + high_period_ns = (ppbaud + 1) * fclk_period_ns; + odhpp = 0; + odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1; + + od_low_period_ns = (odbaud + 1) * high_period_ns; + i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; odstop = 1; break; default: