From patchwork Mon Jul 15 12:09:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13733368 X-Patchwork-Delegate: kw@linux.com Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890F918A944; Mon, 15 Jul 2024 12:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045415; cv=none; b=SkqXxzZudJEVJs3TPWJz4qAbP6TuU7SszRZz6GyapkodhdD0wgsjqtbXGAcHqxJVwRD1vgGJnqHE18yj0FAPvCrsnZNzHTUemHcBOq1AUXwaVkHrA4oQ32usxZnNixQecW9PqkzNNGbuNfvw3QC1EQ11/KHPW3dClEXSEoB80W4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045415; c=relaxed/simple; bh=Ffsd04pWiaoT9ORxIGqRa1ioi+6zLm29fu6Ecnk7ffg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aDeXaR7txgjs4bFcEQt4xm3bUc8Cnv4zHonjA3Cpt7QOCQOqQaFcIcNrBtyrjwfJIo7vjIrbgbtHMAoMXzImjUa6cggHT/ltrXp2flI1DtDpkhB9CHdFcpWXtOgRYxlDyRnySAkJN711EY4ltVuElU0D0bu4KCcqVCMCV5UnH6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=PrYpgJyq; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PrYpgJyq" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9kNI024076; Mon, 15 Jul 2024 07:09:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1721045386; bh=e1bMDhcKO64D9bQTeeRYaeGcwchVy5zOu1+7tRpUtuE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PrYpgJyq2ieq8yOjOB/ywnyG6tuQ3c+m4JK6dBA/9dZqUKwC+QLtL/CK3FauipboO 9eKrPTf0B5O7Jh3Q9qsYu441wH6KmaUA2nd8h6QmhetjdT/Se6TnDbbOExB8cr8yY8 M/yJAZhTURwRC8MemoVz23mHo1x4XAEhSjQkEfDw= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46FC9ku9101155 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jul 2024 07:09:46 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jul 2024 07:09:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jul 2024 07:09:46 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9anW060344; Mon, 15 Jul 2024 07:09:42 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 1/3] dt-bindings: mfd: syscon: Add ti,j784s4-acspcie-proxy-ctrl compatible Date: Mon, 15 Jul 2024 17:39:34 +0530 Message-ID: <20240715120936.1150314-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240715120936.1150314-1-s-vadapalli@ti.com> References: <20240715120936.1150314-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The ACSPCIE_PROXY_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC are used to drive the reference clock to the PCIe Endpoint device via the PAD IO Buffers. Add the compatible for allowing the PCIe driver to obtain the regmap for the ACSPCIE_CTRL register within the System Controller device-tree node in order to enable the PAD IO Buffers. The Technical Reference Manual for J784S4 SoC with details of the ASCPCIE_CTRL registers is available at: https://www.ti.com/lit/zip/spruj52 Signed-off-by: Siddharth Vadapalli Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 9dc594ea3654..13cbc6fe996e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -113,6 +113,7 @@ select: - ti,am625-dss-oldi-io-ctrl - ti,am62p-cpsw-mac-efuse - ti,am654-dss-oldi-io-ctrl + - ti,j784s4-acspcie-proxy-ctrl - ti,j784s4-pcie-ctrl - ti,keystone-pllctrl required: From patchwork Mon Jul 15 12:09:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13733367 X-Patchwork-Delegate: kw@linux.com Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890A52B9A3; Mon, 15 Jul 2024 12:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045415; cv=none; b=n9RE+o4M/LViYW5GBmoXB1dy7nngi//rIrH/WOSq8ZdsU83tlxQIwqXQ9OW3Ak3jzBF2o9YFDKvqO80NVlwCKh9vWcrX/DTGjZ1SKTiJbmOJY+bMUwnM1wCsOu2WQja8v4Cm6534KKhEb952mZo8lv8hVZg4M5/pDS4hMmWnrcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045415; c=relaxed/simple; bh=Np7FjnMeZr9L2hYzr0T3jrWbzJznqSgUpJHIgVSxNYw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZcFowdCoV4OczaUmHUraDqq8GZoVNcYQRWoL+nU5INTOZNB0TwAxUdHSKdgx24yDrVvMi2Xf/AIMm/f6ewyEUxcDgK6JHt6dflXxPVi6VB1H0bG5LEvNEvcBQLYdhPclfwU3AzL5xFa53wdwg68j6d9nVc1QP2+J5KPCd1ZXG/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pxxqlX1s; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pxxqlX1s" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9pHT024084; Mon, 15 Jul 2024 07:09:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1721045391; bh=oWdZfGEhKAneWVQdWVjdFiCIeJCzvhKBZKftmlYHpQI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pxxqlX1sg+1QpB6O8zFKbxwuSC6dl6NQIFtYC8UP1JY/SxRNAOt4+hblZ6KiEhzy6 zbbsYxBowRyaOH8kJ7N2x6ZU1gIddWcAFsANr0SbxUcBm+bG2j7a3O5QO2iuNP6IzO jU4P0GIq5Ccbj+XKYSTONqceDya09mge1zxymNrA= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46FC9pKk012700 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jul 2024 07:09:51 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jul 2024 07:09:51 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jul 2024 07:09:51 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9anX060344; Mon, 15 Jul 2024 07:09:46 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 2/3] dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property Date: Mon, 15 Jul 2024 17:39:35 +0530 Message-ID: <20240715120936.1150314-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240715120936.1150314-1-s-vadapalli@ti.com> References: <20240715120936.1150314-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add the "ti,syscon-acspcie-proxy-ctrl" device-tree property which is used to obtain a reference to the ACSPCIE Proxy Control register along with the details of the PAD IO Buffer output enable bits. The ACSPCIE Proxy Control register is used to drive the reference clock for the PCIe Endpoint device via the PAD IO Buffers of the ACSPCIE module. The ACSPCIE module can be used as an alternative to either an on-board clock generator or an external clock generator for providing the reference clock to the PCIe Endpoint device. Signed-off-by: Siddharth Vadapalli Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 15a2658ceeef..69b499c96c71 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -38,6 +38,16 @@ properties: - const: reg - const: cfg + ti,syscon-acspcie-proxy-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the ACSPCIE Proxy Control Register + - description: Bitmask corresponding to the PAD IO Buffer + output enable fields (Active Low). + description: Specifier for enabling the ACSPCIE PAD outputs to drive + the reference clock to the Endpoint device. + ti,syscon-pcie-ctrl: $ref: /schemas/types.yaml#/definitions/phandle-array items: From patchwork Mon Jul 15 12:09:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13733370 X-Patchwork-Delegate: kw@linux.com Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA8CC18A94D; Mon, 15 Jul 2024 12:10:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045426; cv=none; b=gcC/SnJ24fjxxmP+CWWbHw1/8Mo5QCwHYjyN/I1QShWJLZAcrn50p1kaFvysH003tn1SmAe90JWBD9loEz4Ef84d2cp6xvcDd6jGrTtwe3I7M0x3lKTwHKjnt6lKQp11qAdII/zlDN5KFv6F4GIvr7ZjjVHGoN1pAyvoZTjoTbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721045426; c=relaxed/simple; bh=v3553iIgcc42jQYcQ+pstZfsr9CSKDdUoEVW71SEanM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=likf+CGWT/wceqVRp8BAEnsJjRptf8uXumNMnDPQAcoYQKg/K15omHqHuVnZ7eu65SIvSIywdoR7jxammV65znKd7dCa6Wa82cdmMfW0DodnSsD8IPIIaNb5UeT0h5KzGE7Vr2QEm+VbhBiYEk9D4KLYxFTRTJS5Vo2dt7bjnNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=PM9bN5nW; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PM9bN5nW" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9uJn128448; Mon, 15 Jul 2024 07:09:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1721045396; bh=ghvzRkFVMnN78k4235eqbUPodO5QMcK9davRELJsKEI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PM9bN5nWM5kuQ00txO1vEO1EbCFOBkRJpzS8t31wgjiUhe8H7BbLBK20m8fpFlCKM VMnubsFt7dLROD+sdZGi5dV/CoXTI7Ob30Eb+rv7dbe6eYHUAm01YNssDSqTlZkLYo XLk5C1V8fu1OfTS2C8tRu2xcFGfuShDtFzsMwXM8= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 46FC9u3X107180 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jul 2024 07:09:56 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jul 2024 07:09:55 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jul 2024 07:09:55 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46FC9anY060344; Mon, 15 Jul 2024 07:09:51 -0500 From: Siddharth Vadapalli To: , , , , , , , , CC: , , , , , Subject: [PATCH 3/3] PCI: j721e: Add support for enabling ACSPCIE PAD IO Buffer output Date: Mon, 15 Jul 2024 17:39:36 +0530 Message-ID: <20240715120936.1150314-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240715120936.1150314-1-s-vadapalli@ti.com> References: <20240715120936.1150314-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The ACSPCIE module is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on-board and external reference clock generators. Enabling the output from the ACSPCIE module's PAD IO Buffers requires clearing the "PAD IO disable" bits of the ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space. Signed-off-by: Siddharth Vadapalli --- drivers/pci/controller/cadence/pci-j721e.c | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 85718246016b..2fa0eff68a8a 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -44,6 +44,7 @@ enum link_status { #define J721E_MODE_RC BIT(7) #define LANE_COUNT(n) ((n) << 8) +#define ACSPCIE_PAD_ENABLE_MASK GENMASK(1, 0) #define GENERATION_SEL_MASK GENMASK(1, 0) struct j721e_pcie { @@ -220,6 +221,30 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, return ret; } +static int j721e_acspcie_pad_enable(struct j721e_pcie *pcie, struct regmap *syscon) +{ + struct device *dev = pcie->cdns_pcie->dev; + struct device_node *node = dev->of_node; + u32 mask = ACSPCIE_PAD_ENABLE_MASK; + struct of_phandle_args args; + u32 val; + int ret; + + ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-acspcie-proxy-ctrl", + 1, 0, &args); + if (!ret) { + /* PAD Enable Bits have to be cleared to in order to enable output */ + val = ~(args.args[0]); + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) + dev_err(dev, "Enabling ACSPCIE PAD output failed: %d\n", ret); + } else { + dev_err(dev, "ti,syscon-acspcie-proxy-ctrl has invalid parameters\n"); + } + + return ret; +} + static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) { struct device *dev = pcie->cdns_pcie->dev; @@ -259,6 +284,14 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) return ret; } + /* Enable ACSPCIe PAD IO Buffers if the optional property exists */ + syscon = syscon_regmap_lookup_by_phandle_optional(node, "ti,syscon-acspcie-proxy-ctrl"); + if (syscon) { + ret = j721e_acspcie_pad_enable(pcie, syscon); + if (ret) + return ret; + } + return 0; }