From patchwork Wed Jul 17 17:03:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735636 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FC69181BBD; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=n+hvSc1nPJzpbAc7VrQLMexi3IWki/ZIif09uRe6kJTgKw/sKCh+bBWeR+aG+G95ySNUkzFOc0qu3Ckw4qIHtu42X41QbfOkSZe0eMKPB+6UIB0jb/kjnSmKKuHYO+ucaWEHtvY+AUT9ogQ3k/RExRNCStd82DaVREacvARbhjg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=evFgs4kLdaF/LNItO0+gi9PVYQpfbb7qEPdc1llL0kv9vsyr2i/PtGcs+L9pqOeLkt/9C9SqPcckdsdI741UqUSguG/MkRcbeARfZYIJTYNdMNEXVsUWw/19tdIrbIb9pCtB20LhQIfespsctTsn9NUgcnlgEYyjUKgC4JDD5mI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=r7jyZa+w; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="r7jyZa+w" Received: by smtp.kernel.org (Postfix) with ESMTPS id D045DC4AF0B; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235794; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=r7jyZa+wEaM5dgZsSrg9LTvDVxNojSyFtXugKwGUjrFvSKnCCQt6FkXFcdwIVj085 1nI5mMCvpQ3QO5bImJhZyqeLGdSrku0RZ/oi1w/ItgUEzuMZMe8b+EvacNrKcpzm2Q QO46KD0BuDDNVZ8GkqqQ/d6wK1RsxxXWdg5hkoGfHe3KdwgQbj33/P1qXd/bmkspxY hsUGx6RXSCOK2OaXrA95BmCqQcuRLGUkPu7ZCoEbVRB3AinAA6Iar4wlUmema9Ui4v I/n44jAdZfoo9bEVB6y37HP2goX3fw99bhyTT2T0ZlxDMZXDtj24NrywgykVU3VAiX n8MGzEr4VtOyg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD070C3DA62; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:06 +0530 Subject: [PATCH v2 01/13] PCI: qcom-ep: Drop the redundant masking of global IRQ events Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-1-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1288; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=dIwxxT9MwJPav4RVeIZrg0i1F93yyMgBj6gEWSQjRyU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lMS8IeKnGvWYtg6R8/GQUOZIVLE+i/Y22Yi EtANDfadNiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TAAKCRBVnxHm/pHO 9Yy8CACM6ADfPk4VnUNZr4POA/dfxFciV3UUIFeQ9LBdFrZ6N8IJUY4nw1RLiCErYbcq6xbYNw1 lpfhuGQQwXNuhIyipHx3eJOsp9B+22AMN1+m6j8GueXmP3sPFYkCWYE23cJkoXvO0FHKV1pIX95 hA5FILdSh0KqP43CevDN9K/q93Ro/AdDGYypsjKIBFQBJf+TVc4VaAVoM/Qm8Cg8Vz9R1xuMRaO PogwsRu5wPaJDmOy/FaH6V5NqetdmaUm/MQ0bXrkGdEzjth9RnOyYC3ZyfB9hfqXdtzsgvhZN6E 1ZYf9LpMyMGkOM3w+xzwoq7OQiJ3F2SH8mmjyE6d4kEhxrfW X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Once the events are disabled in PARF_INT_ALL_MASK register, only the enabled events will generate global IRQ. So there is no need to do the masking again in the IRQ handler, drop it. If there are any spurious IRQs getting generated, they will be reported using the existing dev_err() in the handler. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..972a90eba494 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -647,11 +647,9 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct dw_pcie *pci = &pcie_ep->pci; struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); - u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); - status &= mask; if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); From patchwork Wed Jul 17 17:03:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735638 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FC1E181B9A; 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a=openpgp-sha256; l=1256; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=B8RUdvVv9QEg4h2fDtSWIh3luhRVOKTDULQMHpO/Rk0=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYkib/tNXaTf3+oRjsXtz5yuu3C7eMKHk55G+qVlyZYt0J lY+eJ03s5PRmIWBkYtBVkyRJX2ps1ajx+kbSyLUp8MMYmUCmcLAxSkAE2l4wsHQMJ+VPVogK3H2 x/uMN/f9Vb+W5VAql/rB74JId1/KqdzoU39NqzhyFKsuZhdPlXB3muSaGBTiViT/5mL0A5mQ5dx bkr0F9/eKG+09Ft78JGqOUgpLJHvvFcmYJadtNP9u6Jkxs7CzTWyXXad3dt+Z9PWTzjfN49vpbu Ucpll68OhFo4o7cd1hfvsmqjzhvCHG0SNgW8pi5uBbfchNxPSz2VyxWXVfGj0FHlQWsPyWvTx3d 7elkmt9YW11eWN0r17wpfM+ue8k7V7/ybo7xTmGNfnszJVKC436Q8z1GpJWLdX4lPByxqTla6w6 +V5tV8uf9TX90exPa/1tk1sLfrQYM/LYSN8rnqv3vvsFAA== X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Current error message just prints the contents of PARF_INT_ALL_STATUS register as if like the IRQ event number. It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ storm won't flood the kernel log buffer. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..0bb0a056dd8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Wed Jul 17 17:03:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735642 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8001B182A79; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=uR4CbS8lVHrLYmN5ZyNQ3C5hCSTc8EAtaMvzarmm1HnLnCiXaz15Rv4lLlLOn6Eqz8SbNdNO/m/Oo35S/BVxlaOPJrzzWZQOUar+6uDgF1W3qZ6lAO9r75k/TDN4McTO3lsrdD0yYVi206ps+pe3sdwidRoaca8EaK7RyrmXEmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=LRGU1ZUSjT7pMjV8SjmoQEmYcbLwDjL9G1AFtQWIDsM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tgt1M9F/vBYo4tvJ/Y9HbU7s1Af7Az/YhYsaut97JTsaMLWquCqC3ClaQA8AyjSZfqE6AUN3OX6HdSjGrre95u9BvNz2QoK1IRmte/P4mL1cc5X2BN3bAbNHDess0gqEx1PirqnRF7nRYhRiPmMXelvvtf62pW0roZtiqN9jp20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RDetYLCJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RDetYLCJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id EBEE8C4AF14; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=LRGU1ZUSjT7pMjV8SjmoQEmYcbLwDjL9G1AFtQWIDsM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RDetYLCJeh7EXB2FwEv3KPfj+0hfPbm1CizCYQb1YtI4etNOPfgxuPBJIXuBCS9Bc WWGA6i41putpOmcaqC/fp2SxdAU9p154PPuiKa4ZI4GGULpIXs2OOFovv+e2otIbrM r38gBJyGu7Oonbzg7Y8D8tu9VN7ODyWCt7JLmUXdSQq4OvWU7y0w7n/hkBc0cnzhh/ 7GeGdkht1TkurL9Hv/rzldTdg0OdNGG4ohEIqIA9bKeO4is9awcq3VMYyNMy664ity dT3EZQoGPnxitnssU1GgjxgwLlPww85Dni3CJu20WaBg/D/EezMsyocUWoSekUqrqf cVbxCwQrS2kEA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8EA2C3DA65; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:08 +0530 Subject: [PATCH v2 03/13] dt-bindings: PCI: pci-ep: Update Maintainers Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-3-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=988; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=hjExGhGjQYtIRypMJXzdJurZJRAD466HOf0lMqV3fm8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lNfQg31fke8+7oE4tHhiVq2trkn1dGnRBUr XPgVijg6keJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TQAKCRBVnxHm/pHO 9au6B/wPjAG890Ex6xuP3e/ld/sG4k3HMnWw4SNgGuWBUlbG0HRtEstH87bHLLybXjXBhnxu8Ap lTfSu4AWyCuwvfW3nIsqqjSXL47MrsJxtj3V/h2l9EuGZc4P76S0/d+h+KXyjscab7Tiho2/ThA 5FgBVTmZ/In+XcxMSx94uKj3jxZX36OXPVJM69piD21ZkdCeU3NMrDfT9ELPh8LohvhycCKgaxE EjUoqvxZwZ9W0XMCIoPBxCV7DY8H9IKtkpE1mBH78ESyt9ifmUT5B0FWvbtIzTMqK+oV62C0QxJ dfazQj0E3ELoLFT8EODzryuYlc/XNzzuq7wkrkI+nn7zVU3K X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Kishon's TI email ID is not active anymore, so use his korg ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the Co-maintainer. Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index d1eef4825207..0b5456ee21eb 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -10,7 +10,8 @@ description: | Common properties for PCI Endpoint Controller Nodes. maintainers: - - Kishon Vijay Abraham I + - Kishon Vijay Abraham I + - Manivannan Sadhasivam properties: $nodename: From patchwork Wed Jul 17 17:03:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735637 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FCB1182A40; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l4WLFn4k" Received: by smtp.kernel.org (Postfix) with ESMTPS id F2D5FC4AF15; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=8znAZBcirLJ8Efx48e0wAJqyTm86Mv7/PWdHuyyfnFY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=l4WLFn4k4kL7R+8+NA2DXQC3rmJonpCPAJhL46vDYEuuAA8BFFnNBupupAPPp+Ko3 Ywh6fF0gk5otvfS+4JNfPuo0q0pLh3dlkE9pLZkhw8pdwUioIhJH7c8dOYsVUQgyD5 KkOt9z+FHmjRe+zj5tRjFk2dC7qBd2D3Ywhw6I5A2mG95k0zBPjcJbSrP/Yj2SD3Z8 Fdnte0yl2lWIDzGSqgkiqBor8IwFnT1unLETVw8JlZfk5xnSl4VhquW5IuqvK3Ctw7 cGa39VKd/R6UBJBAbPCJv6XdvHKW9lltpIESfFErQM8IkGAR+Y4fa8yoKYMc9Sxwqc vFJ+f+edj1Dfg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9070C3DA60; Wed, 17 Jul 2024 17:03:14 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:09 +0530 Subject: [PATCH v2 04/13] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-4-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2026; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=ZuN+bx8IKdLBF21t1VI/ja/rCNR5Gv+31UWAdkgegn8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lNOungbljczBVTQEbuVGUsSyBz514OTIUe1 XwRJf+2l0mJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TQAKCRBVnxHm/pHO 9W4TB/4+mQi+zmPUNe4N+A+8BE58IM6mcrr1saFbdM8Fgvd2+J60vl8DNlvStJ3ur9oGHtscFmv G6PqO/JxrE92lN2Ele/1qv4qaYEysMGDrMCuBhq2F1kpui1Pp/G9debqLKR0Mr9biZtF7/GZzjv bRhIxErl2K8zifTUeRXkXC1oGUthAW3obCaDd0aqTd7jBFixvasyMhd0zbmeXxKR2mkaQCbdxOs Tje3RIXecdZk4DuWtL+SevmREnYbMIFSF7OGOTAvbc571M67eq3bSPUNm6rF96ooNapgALrXDdY IehQIrNMwRTmhQYH8Bhm8NP9rDoNEZnwoodxn4j12FhcjbJP X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Wed Jul 17 17:03:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735641 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B2AF18306D; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=IS5WDe7xcQGuH+Nn6nXWD7BBtX1SIW4w5maOD/G3FovrlF8NtFibAc+/zYtmN2GXDYLMJlFns41idiIIzACjNIFcUJu2dNuWP/dPW7DyGeFgbQpedtdK897quTHhQDoCWcy6XlMZn8iEFF9OeAfDbm0X35DQSW8eilpBMDaCZUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=0rGn+aPcpL0pLEHeouG5eEtAwVJpEH+6CnS4Upe21fc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dx2WSfEIt/p7zU7rODwmyYlAbTV2rkBYEULHOPmWxw6jatE0RQPS0DD/jzGUaKnht9oKJm6DrSELlXU0r0A/o4edW+ZHUoXki+XAEY4WxTVy+1g+xR+nTWhZYbsUWiyJzAXqp7h1TUGHE4I5cjcElAVOzN22EDfx+ykvZEDZAUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pY4cL4l3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pY4cL4l3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 15403C4AF1D; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=0rGn+aPcpL0pLEHeouG5eEtAwVJpEH+6CnS4Upe21fc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pY4cL4l3zdbNEZ7t+o1w6YgflZVzGNhFpjj3dzt/QpJ5RKSgj9gUddvDXn2GhXIc0 q9vhZwWrG9aaK7VKUfXop4iOF5bPOwGImb+GR8NLLSRxGWa4nJAQQW9s2GWRx+3LoR xgB/hIRx3CAbpF3e4vfDooH5fkxXL5WTyW4PELr5RdQw+XNjQ0k/Yt7/cV8R82YA2b u6wYgjQayvQDhyDTajrznJ+PRH14V4mSNXuasBMY76LFixpfvVhojwL6He6Cm96ium 9/kDomnK9fy/7pnfPkfiv8AT/43vMIrXWu8GQXQCvdZEQe2s1Es1ycJERoQ2wiTrvi 9nD/4GIsKRS6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 087EAC3DA62; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:10 +0530 Subject: [PATCH v2 05/13] PCI: endpoint: Assign PCI domain number for endpoint controllers Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-5-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3043; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=RgNx60ASNj1W+S8yTFl/XDFmb63UnDz74gKp1lFMkIw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lNJr0HPlA1u3KlDHSrQVmia8YznHXb4MGCI eq+KVVpCtqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TQAKCRBVnxHm/pHO 9c1MCACf1G9ULGICZoGu33tG6Da4yMhnoVZQjnNzAGUwjufpNwuc57Ze/yb8vcYtVdyV2KjvcjX o+sBZj0mbpbo5lOVD3A8/MLJppD2S1Bb3OEmPpHHkS5T8fIDxxgs+RBXEUriO6Ebl1hNkplz/c4 7LT1QmMbpF5+94YFGvgalfAy3rsjOZFp5rVxHC023qBvNY6CAQkjbic6wEFJOgjMsBM9BQA3CdJ w74vH+FZ2zuG3n1wCXTgMQBa9xfgFTuCD3ycjuaS/YzakIwGTi8WNH8s6n62TKSD2Dj7OjTmZXP HEi3phA1+SkPddEz41ZiSCOp0YYI3o5DnWg4FjV1KdJcnBfT X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. If the architecture doesn't support CONFIG_PCI_DOMAINS_GENERIC (rare), then currently a warning is thrown to indicate that the architecture specific implementation is needed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 10 ++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..7fa81b91e762 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -838,6 +838,9 @@ void pci_epc_destroy(struct pci_epc *epc) { pci_ep_cfs_remove_epc_group(epc->group); device_unregister(&epc->dev); + + if (IS_ENABLED(CONFIG_PCI_DOMAINS_GENERIC)) + pci_bus_release_domain_nr(NULL, &epc->dev); } EXPORT_SYMBOL_GPL(pci_epc_destroy); @@ -900,6 +903,13 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.release = pci_epc_release; epc->ops = ops; + /* + * TODO: If the architecture doesn't support generic PCI domains, then + * a custom implementation has to be used. + */ + if (!WARN_ON_ONCE(!IS_ENABLED(CONFIG_PCI_DOMAINS_GENERIC))) + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); + ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) goto put_dev; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + int domain_nr; bool init_complete; }; From patchwork Wed Jul 17 17:03:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735640 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9997218306C; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="azMpTza3" Received: by smtp.kernel.org (Postfix) with ESMTPS id 292FFC4AF0C; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=YFMeGAfhyM9bHtPXFygVWmHaeqfsPIqirTRI+ZUhVcY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=azMpTza3Ty1tTGFDoJG4XsKQEBVFUwl2xAqtbqrAG5DF1ggqC1vg5NVFVl7Zyql0C s8BDiiu+JlhTFplD+CXftTXoQ9E0ru/d48DtO+0eBknkRW0mix2MF0E0LE/LwgnUrU rA6jZP9QQEb+5KHf1Pgk4m9zGF0WIQSOe3WGj29RaNFEA/e32kE/6agXy7OAxEhFtC i61HFotX2oYXZocdAaLL37xcvw2d5u4yWXAc+feC1ed6qLX7FLcLqt/PCpqxMcAEyK VoOk08G/QgR9U8GQZrqkC6kzasKwCv6vdkZ2qYLvdFzOsDVqs/InOwdi3URnNOsQ6V ApQWZm5Zhb+9Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AD72C3DA63; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:11 +0530 Subject: [PATCH v2 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-6-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2451; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=OLDTA2u7a/IhWC3MtFf6Stnx+Z4B5OLjl/uildv1v/c=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lOI08j7Wv5M424aLdNTgYCTZGLtQ2VGQxDP 0fiBGevU7OJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9TDNB/9vDbfXwQESIcTjCcZVnQergPptI/QsVRlGP8dFnXeKhn/nkuGPUhKAMZL81Y/c6dAbdRT abrX1cbyoNPdSzclS68FG7yBmUHB+qFoBOkCBwYgId8Asxi3iM9hSOyWkM+mO+SJuAsIisIkNKz +uBrO4RVoAUi2x+W7JL86PyqSlW9kwJGpi/aZFQTIJ4FUrtsr4fllIEf2vJjD8qghREegIdmLGp +alvir5UiGeWiSBR7zVvy889TAWf5nCUW2ZOGiRdlBaTb76D2l2AemIgBqRDTd96rD5KN3RURGI GYx+37itzRcFPJUuqNlFkHtsDAOpTGFwWl6YMFtL4vlDZKAq X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Currently, the IRQ device name for both of these IRQs doesn't have Qcom specific prefix and PCIe domain number. This causes 2 issues: 1. Pollutes the global IRQ namespace since 'global' is a common name. 2. When more than one EP controller instance is present in the SoC, naming conflict will occur. Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ names to uniquely identify the IRQs and also to fix the above mentioned issues. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0bb0a056dd8f..d0a27fa6fdc8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + char *name; int ret; + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); if (pcie_ep->global_irq < 0) return pcie_ep->global_irq; @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, - "global_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request Global IRQ\n"); return ret; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "perst_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); disable_irq(pcie_ep->global_irq); From patchwork Wed Jul 17 17:03:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735643 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DE6218306F; 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a=openpgp-sha256; l=986; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Lb2vcF7RPFdOyct+N0+V3AMTmLDYS+SRQY7Fw3HIuE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lO5lBDAIgog7/DCQS8jI0fHtovZQlYwqd5B WyOgUwNCS+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9drCCACjiN6bdLASGYBDuhq74Vb33fBJv4q/jyLQI7eY1YopkvdioFtdULJXkMXon5Zuk0IaPku kTBOiAX6Fn8kn/Xlj5sScthaADAb3cWT0JlJyEMgcpT52ASfJAroHamUTcqSigY5q4qh+j9yIC9 7BkhTsQjOnd7TLxKYFC4A59LbfM8Rd7loU2mV0Et8D8agByUjG9JrtsxXjxvYhaI+JbV4OBvXrJ qjDsuvabamJDN3ijnuhEeC6DsCu1povehl1QaFsAzAtPJdQ62Kjn6HUiYSBQB3y1PNw7YmwLIkR B3++UcnUscWAB4kR2N2KnO4ZQ5P1Es90cNCEk8EtGiAME9pD X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735639 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E51183065; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=giiUt47IrfGfEwfgz3MhPd5rCPhzBBb4IZzLUKMomo9G5jlwwX6Low4eeQTvkgAxzZc1C7oQOcWSj/ztp55kVczy156Ovn3FK4jRr8XFHv9U15drDX7XamqzLOPA9SJSussVWJHX0W1pWaqtYBi6orGaHMlGZB4v9brp8o+KLNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YDjJkcUNRY3PtLuh2M3wrm5ru1GcPAftALaF7TJb3NsGqyz1OR+9Hoemm5ly0GZCO0UkgwtbBqD8A9I7zebb1nLq1z+hpGGhVaBQSrgXh4ZL68yKqKL8ZZeHmMgNqtsD3iobFvgVPyWNEWsRiwL+Y80Um7Fl13afojHyf1DIbho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DTZ8CXwj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DTZ8CXwj" Received: by smtp.kernel.org (Postfix) with ESMTPS id 491DEC4DDE8; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DTZ8CXwjoQWzwYBGgBSCy0kUhYdWaM+9JZ1kJvMw7qpGQYkViY/95j9XqL0lZIf21 fkwCbS2eucxyXGN12M56HYTtyRSNtC9wgd0LRTITMyLXzjp2Kz4sTrUvMg6xKvXVis lHKS2hYwe6R2x4ln265ZNwRv55G9OyjgMHk2zzayCncSPoHC/X7oEgXDy8nfnKZKSB o7K61yR0rFUgI/SARgIxAIrh1Btg3ilekQ5NMTNPyNwvVEtiG4DaT5xXDjq2UTQgHX eM3eNQTmxlThIHCS1nGsycKYpmFy32Y8rtknl1fsk02h7ScQ+zeSunyZtxpTz6eKWG cR/zBC2kvj4Ow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E64EC3DA64; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:13 +0530 Subject: [PATCH v2 08/13] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-8-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=961; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=4ksb8gQi6XxtqZHvRIfOuO8m7D/GXep6HzglfrtwSCA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lOaxt8p1VgGOZBseIX6KvazP7qZyjP7I2qJ 67f4dQ5/OCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9dS3B/9Rjk+/ba3zu1H6d/sG4cj9IPKv0Z942GUAmrfXH8YUbpeUaBSFG88mexbV8zlFoZz61wQ 7G1MgSo7bm8JbY/qVmvk0AOxJn/O3y5sW5z5LGupXMkz2ffMp7pN12e9bO8cS3cuaVQll3fVFSr ZLzzhTezyNKcZw22kyRKEQ0F3BSg3kFHWeIDQb9OgjPNTv28OhO6rcnZT2JwcHpVLVimvASPMNR kclkd+tzsE8wIbW7RE5W3UIbvkvWkFYn5VpjcqyTTMTfslxEE6jlphoqh4Dc4GDyqTzVlfyhqm0 2IC950TCA0ZOBe+3E6jyu6sxHb3rrsn23W5BZYFfCk6XloRB X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..fcfec4228670 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735645 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C87018306E; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=MmK8FJNUm4m7iryb/H5x6VbbO6IuxHdy015t6T4E5pcUJcFjte8azrmmd+RSOfAZzzxRQDaCQDHh/IMIl3Ifemn/y1TokDuCP40MXa4mvixhStxyqK/29uVGIEpK7uaM29iw70D0cNuvVNIAKeUdHK8uEaPwcrcU1tg1JubZlCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; c=relaxed/simple; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VIeyRCQkclH2mUPkaR4i5657Z4ya9A/NO1SReiZMd+QD4XyKyU+GB1LuTUeV2XaNlgjlu8kmJ/tABLHIIRWfi3lfgPwa6phViMiYOeXIj0EjwQ36CAPB1333Ekjf30AAEjD2WCsUD7CpoCQI31VuuTGzvLdwN0zZUb3KTWdWXLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OobH63Br; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OobH63Br" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5E999C4AF1A; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=OobH63Brw5e3Wl00GuzcRP2jf+t3XLCUngEkFnINvwfybj6SyL81DSLEUjsHboTeD rnYSeSP7DWb01ej/VkNuPz1UA2tPDCsnBAQ+qa9l/ndtNYkaBv/2PipNSrvmEalpWR TReq7ReTvp9nQebNaCvVnocYWtoOXGvEemi7QXUI4C807+8cqA0RQy4iqqs9xgN/2D CDt9wRFYtQKQqNo26NOYxk+jtoSyHFFjhf1gfmBLW5M/rZ28Dakc43yYVhJINaaewA zFF7eDzXqGl177+jE4X5uZajrlpJWMZ6aa8ki1ADUIlpQ7DKB6mM3L3HCCaTRHCsKu KMY9XKc39cGBw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FCC4C3DA63; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:14 +0530 Subject: [PATCH v2 09/13] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-9-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1289; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=YKSy5vPklQvLJA99UbdPy4mFyoiPQChYvArhByAGkpA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lO0Dmif7USBFz5hYoCiza5W/fd8O+FngHr/ 24+q3osoLiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TgAKCRBVnxHm/pHO 9awtB/4kSxxPulCuNa6RgrOTzuAeI/hkw6WQQ97HhrEZToQEkUZvp8WMGZ2aQIHLxS2xYUQxE5R EdJWwjl83+26qlrhNwwR60/fltegr6Wyb4g3dhiRBrYGav0cCt7hSwbEatBc5axOyxNNwf80eg3 y4xM9rVaSJICwe8FTw+d4oYXWwcS6HdAR9W8PJpcVI/iFGOr7Dtia2yH1XKywUNyVAdS/JynHxV nQfS2SIHXiCs3b2v6xYBx1NBgGVcKZoh7CM1u0bWJkaY4s+QlWL1QMJEK1JkLAzstaWYk/W2lth pQLivgbf7hZuXjpGbCnm8+FbHBu0Gd3uSXy1T4cSCTa33tsV X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Wed Jul 17 17:03:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735647 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D61CD1836C8; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A5k/ff+k" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6A0E0C4DDF1; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721235795; bh=gpFkVvbXM7bCqPYW+aDVZ3Ody8SHFkjq1FkAoOcZ9yQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A5k/ff+kojrUZicsQxusOfefvYvGscS7lPv2v7Btk8GNADzwviJQnlO9b5EbAFGep OLY5ssSp/wSouPRV8zhw1cNRi7ceLQhdoHSxPBe0GZuXDatG0Z59CRv24R1MLGs/Nl e+YIpU9ezcc7iPmZhYPx++PDUQuygADS/vPi012h/3OibcqG0SiNbXWfn9yHHQMrek XzdHPys5y7SR7zlwl4snG+sLlf3VZHhXgLYi5Vw+apMotj6iSZMJSJwGoj9xeGz+X7 Y6hKx2t3OadPhX55UgPKPgVzaD6cIupMtRDkXyE7w3bG0+YULulXiA5VvENvDKI8GG Vtc/8N9wwWYvA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6065EC3DA60; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:15 +0530 Subject: [PATCH v2 10/13] dt-bindings: PCI: qcom: Add 'global' interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-10-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1044; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=UnqChimHBG0jtzlN6KxFR0yebxEqg1erfRRq9qEP0p0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lPbog6HMzM14ffuorA6JAroE66s8hMQxxvS 6uDBQeGfSmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5TwAKCRBVnxHm/pHO 9ZBDB/97pJk0fM/DxV2aQn2c/+/glj5xjJYHG8hLSjWp1JoZDbXyZjRhn9+JeFUtLzdcyc3uuQe DuCPTNpiADDPM9WQqJOlVW01Iq3gBDvWePUubjNax4+ug+4BJUiRKTPttTTYqP6362OUQV2UaZE xCAm4n0Jz9DafsHpQ9ALN4l+fpCVjL43IkzSoGji/SomcdWQ8bK7o2z97Sbh8THFydl1pG/XxR8 G0Cr2r/EJdoFEjAo2NHb6jyQ5gXP98gCjPCSlgvRRHFGc7xi9RhRVPkPCWZ6E4aRQ+VqFqVCSFM B/ff6u6YIQVrhI7HlTK+GvLGaSE/xkwfcbQRe8wrRh3sy2+D X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0a39bbfcb28b..704c0f58eea5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -21,11 +21,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 From patchwork Wed Jul 17 17:03:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735644 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7924183087; 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This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..0d68ce073383 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,11 +55,12 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: + - const: global - const: msi0 - const: msi1 - const: msi2 @@ -142,7 +143,8 @@ examples: "aggre0", "aggre1"; - interrupts = , + interrupts = , + , , , , @@ -150,7 +152,7 @@ examples: , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", + interrupt-names = "global", "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; 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Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:17 +0530 Subject: [PATCH v2 12/13] PCI: qcom: Simulate PCIe hotplug using 'global' interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-12-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4482; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; 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So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by simulating the PCIe hotplug using Qcom specific way. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this event to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to simulate the PCIe hotplug in the Qcom SoCs. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices, thus simulating hotplug. All of the Qcom SoCs have only one rootport per controller instance. So only a single 'Link up' event is generated for the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..a1d678fe7fa5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -50,6 +50,9 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_ALL_MASK 0x22c #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -121,6 +124,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_UP BIT(13) + /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) #define RD_NO_SNOOP_OVERIDE_EN BIT(3) @@ -1488,6 +1494,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) qcom_pcie_link_transition_count); } +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie_rp *pp = &pcie->pci->pp; + struct device *dev = pcie->pci->dev; + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); + + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } else { + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); + } + + return IRQ_HANDLED; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1498,7 +1527,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; - int ret; + int ret, irq; + char *name; pcie_cfg = of_device_get_match_data(dev); if (!pcie_cfg || !pcie_cfg->ops) { @@ -1617,6 +1647,27 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", + pci_domain_nr(pp->bridge->bus)); + if (!name) { + ret = -ENOMEM; + goto err_host_deinit; + } + + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, name, pcie); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "Failed to request Global IRQ\n"); + goto err_host_deinit; + } + + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + } + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) @@ -1624,6 +1675,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) return 0; +err_host_deinit: + dw_pcie_host_deinit(pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: From patchwork Wed Jul 17 17:03:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13735648 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7FDC1836D0; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721235795; cv=none; b=Ej42um1480Ag2OcGMbLD7GzSI1Pkk9xGRIycatcjA0DSurop6S5DlWrh93GSIgjKITXwlmHV1wfP9UK2iZLza0uf5t0F7m81xDEYhLtY7CzYA6v7vndoHyrDZypBwbxzy23ASXIj/xxbU0DmxGsxjRJEWyu3+aR8zq3CYPVWaik= ARC-Message-Signature: i=1; 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b=X4mxQYh0fLC9varOig9yX1D5WtdciHuKfKvfc0PkeWH9KMV8yiZpjVzUHi+bpSjB4 3W09PMkqw93yik7dM+Z8DNA7Jpcuo5wi05cUViGZyNVUXs8wqCSjTJy3oocd4BNIdt t4FmnBRzz83icGbWyr5+otI4WQ8Q3gMNJGhQYklkSb+aoHz3Ygf6mYGWHH4xyFtu/9 3PMXBsqPyrIGF2su/Bq5yEYIob0iXNu7kMSom1dLaen7L90to/A/L2NKIy0SZ057ka GtKpKa9vA61QzUgIdruN/k5nH5cWr2XiBMTkd2ic96ls6R1ZFnvc8GdG3BQuUnyuBv MjOJA7Aubclkg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91787C3DA63; Wed, 17 Jul 2024 17:03:15 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 17 Jul 2024 22:33:18 +0530 Subject: [PATCH v2 13/13] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240717-pci-qcom-hotplug-v2-13-71d304b817f8@linaro.org> References: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> In-Reply-To: <20240717-pci-qcom-hotplug-v2-0-71d304b817f8@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2237; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=gNxsaYyTdguve7w+Y8w7ph9rzM45Fb14SQIqKjXqzUk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBml/lQoc5gOTjQlnoV9RFWf55lHtNK/snPAA/Zj AI6kMTF6tmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZpf5UAAKCRBVnxHm/pHO 9VH/CACTkmifJa0vTjLza77wfkUEX/oPKk0rTwvANJ/pMgp4G5k6FeA/Th87DPhIa0TiYTKeTwL aVXm3E/uB868s/Z/7tDG4MNGgTrQkFY+jEYYw/DWzg/skU7trqFF4KOtjyygUdedTN++yuytm93 98RUt0xXWB/e1w5bZxBL3z71exaGnb5bFgokv9dKGSXCEPatFX+n24fDYEHTwtOnE/LqfkhUz2+ 7G+SjIL4u6aKmMYt1X8nWpl/0KR5j7DMsxSsU0ACvvY/Gq9rWE5MH7SYeTks7SqTXdzB7nO1b5x +kRChxgMeypiQtE3VZC8LlsT4FAW+YSFNK+Ur1KQr2gW7xNP X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..90d16cb83669 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1780,7 +1780,8 @@ pcie0: pcie@1c00000 { msi-map = <0x0 &gic_its 0x5980 0x1>, <0x100 &gic_its 0x5981 0x1>; msi-map-mask = <0xff00>; - interrupts = , + interrupts = , + , , , , @@ -1788,7 +1789,8 @@ pcie0: pcie@1c00000 { , , ; - interrupt-names = "msi0", + interrupt-names = "global", + "msi0", "msi1", "msi2", "msi3", @@ -1942,7 +1944,8 @@ pcie1: pcie@1c08000 { msi-map = <0x0 &gic_its 0x5a00 0x1>, <0x100 &gic_its 0x5a01 0x1>; msi-map-mask = <0xff00>; - interrupts = , + interrupts = , + , , , , @@ -1950,7 +1953,8 @@ pcie1: pcie@1c08000 { , , ; - interrupt-names = "msi0", + interrupt-names = "global", + "msi0", "msi1", "msi2", "msi3",