From patchwork Mon Jul 22 00:58:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13738203 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68FFA8BEA for ; Mon, 22 Jul 2024 01:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721610521; cv=none; b=DFPnJXjU9VvZ3Xz0DJEPpjUqjTi/XUH9pgEQCJ/lo28cTnpejwZdiYbgJVany9Po4yixqnYxD7OUeVMmwmsv6D7Earxpbt4dHTJePxqBlKD/cUTa+hlYHc7TxanouCfb0WFe4X7WISWKZ338XYGyuO7NRxnDXR3cs8Sco9trLdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721610521; c=relaxed/simple; bh=sBAG8CgQvJNf1n1v9OA5RdPMZATzxBlvnrmNXiecv08=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lD8ByHRlwU0ancbi824YNPFrMIqM+TjxjeP4yKcMQLJjNNDXkBpUUizerqX/7NPXr/sBwHBb2YvDIajAhFZ3mC4BH2jYc6F5VkKonfD55Ha4Ltle+f8u9Q8yDsbFJJTDALJ5Syy2x3oNE5D3nquHusm3R756OP/b2rkorMR/bBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=zCEVQkxz; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="zCEVQkxz" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8E0142C0E30; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1721609921; bh=CEQoIEZwGjggOOe+cMGdGFt8ELGSd5VDRabos8qlvQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zCEVQkxzbS6k6P9vF8NkLfxGpsx5COsZzlU1m626EWug8vYY1qsBK6vyW/052rcu0 KHDk9JZd/LPotcfbT+h8jI4ymW9Dya2avGe23sixicctmI+/QizCNWjdmlOxe2sFlS UoApyrQxs3a9Ku1ViIvnFkKVluKwsEea6Kev1fpzJDC65TCh3WJk2B6q1NP9xD8fRq KMKd9DOpx5ttq9QbPlvXJSDkLTCTjdEbaW0R/am0fzosc65ZR0MLuCQMN7qoSYGZFn uw3zERKWnt6fgrp1YQ8vdznhnxR2AI79PTwV8aIeaVKcIzocfsfOttNFUpIRtH3814 6QKzTs8MhMYAg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 22 Jul 2024 12:58:41 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 38D0613EE6D; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 34E522808D5; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v6 1/3] dt-bindings: hwmon: Add adt7475 fan/pwm properties Date: Mon, 22 Jul 2024 12:58:23 +1200 Message-ID: <20240722005825.1800403-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> References: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Gqbh+V1C c=1 sm=1 tr=0 ts=669daec1 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=VwQbUJbxAAAA:8 a=nd0hpPEdzzsPhCuWCasA:9 a=3ZKOabzyN94A:10 a=MKNsf3uAAu3gLl-MH12z:22 a=AjGcO6oz07-iQ99wixmX:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add fan child nodes that allow describing the connections for the ADT7475 to the fans it controls. This also allows setting some initial values for the pwm duty cycle and frequency. Signed-off-by: Chris Packham Reviewed-by: Rob Herring (Arm) --- Notes: Changes in v6: - Collect r-by from Rob Changes in v5: - Use nanoseconds for PWM frequency and duty cycle as per existing conventions for PWMs - Set flags to 0 in example to match adi,pwm-active-state setting Changes in v4: - 0 is not a valid frequency value Changes in v3: - Use the pwm provider/consumer bindings Changes in v2: - Document 0 as a valid value (leaves hardware as-is) .../devicetree/bindings/hwmon/adt7475.yaml | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index 051c976ab711..df2b5b889e4d 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -51,6 +51,24 @@ properties: enum: [0, 1] default: 1 + "#pwm-cells": + const: 4 + description: | + Number of cells in a PWM specifier. + - 0: The PWM channel + - 1: The PWM period in nanoseconds + - 90909091 (11 Hz) + - 71428571 (14 Hz) + - 45454545 (22 Hz) + - 34482759 (29 Hz) + - 28571429 (35 Hz) + - 22727273 (44 Hz) + - 17241379 (58 Hz) + - 11363636 (88 Hz) + - 44444 (22 kHz) + - 2: PWM flags 0 or PWM_POLARITY_INVERTED + - 3: The default PWM duty cycle in nanoseconds + patternProperties: "^adi,bypass-attenuator-in[0-4]$": description: | @@ -81,6 +99,10 @@ patternProperties: - smbalert# - gpio + "^fan-[0-9]+$": + $ref: fan-common.yaml# + unevaluatedProperties: false + required: - compatible - reg @@ -89,11 +111,12 @@ additionalProperties: false examples: - | + #include i2c { #address-cells = <1>; #size-cells = <0>; - hwmon@2e { + pwm: hwmon@2e { compatible = "adi,adt7476"; reg = <0x2e>; adi,bypass-attenuator-in0 = <1>; @@ -101,5 +124,15 @@ examples: adi,pwm-active-state = <1 0 1>; adi,pin10-function = "smbalert#"; adi,pin14-function = "tach4"; + #pwm-cells = <4>; + + /* PWMs at 22.5 kHz frequency, 50% duty*/ + fan-0 { + pwms = <&pwm 0 44444 0 22222>; + }; + + fan-1 { + pwms = <&pwm 2 44444 0 22222>; + }; }; }; From patchwork Mon Jul 22 00:58:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13738202 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 677048801 for ; Mon, 22 Jul 2024 01:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; 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Mon, 22 Jul 2024 12:58:41 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 3E4DC13ED2A; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 3AC3E2808D5; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v6 2/3] dt-bindings: hwmon: adt7475: Deprecate adi,pwm-active-state Date: Mon, 22 Jul 2024 12:58:24 +1200 Message-ID: <20240722005825.1800403-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> References: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Gqbh+V1C c=1 sm=1 tr=0 ts=669daec1 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=VwQbUJbxAAAA:8 a=A1YWOaG1RMH6ymt1ZYoA:9 a=3ZKOabzyN94A:10 a=TmF2cBh53Nm6oE2QjmZc:22 a=AjGcO6oz07-iQ99wixmX:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Now that we have fan child nodes that can specify flags for the PWM outputs we no longer need the adi,pwm-active-state property. Signed-off-by: Chris Packham Acked-by: Rob Herring (Arm) --- Notes: Changes in v5: - Add ack from Rob Changes in v4: - None Changes in v3: - New Documentation/devicetree/bindings/hwmon/adt7475.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index df2b5b889e4d..79e8d62fa3b3 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -45,6 +45,7 @@ properties: the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm uses a logic high output for 100% duty cycle. $ref: /schemas/types.yaml#/definitions/uint32-array + deprecated: true minItems: 3 maxItems: 3 items: @@ -121,7 +122,6 @@ examples: reg = <0x2e>; adi,bypass-attenuator-in0 = <1>; adi,bypass-attenuator-in1 = <0>; - adi,pwm-active-state = <1 0 1>; adi,pin10-function = "smbalert#"; adi,pin14-function = "tach4"; #pwm-cells = <4>; From patchwork Mon Jul 22 00:58:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13738201 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DEC1610D for ; Mon, 22 Jul 2024 01:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721610520; cv=none; b=uWU8/gMtSD2u9rs9J63XO0mh55gF67zncV+8bwS4ibBxTv/9wF628QT4G1YZ+LRYs2Gk2+gNCPWa7Xv5zwSX9n1J/OKkMV/PUX7IfJOC4rdZ77woByuWr0C4pkNVBg0ggOKHhtm85uzAZUYYrlryfGxjYx/omxsOZYmQtW/1p1g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721610520; c=relaxed/simple; bh=DNyVObbdbJVdi/P6CGl+fix7Tl3TWS/WBFlw4NpsCsQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n9QxBbOq2kqAp62wePWLDmUpboq+MWKoqjDgiTGe3PD8i0540i7MKJjf9jLhyK39A9IncUposqQG5O9ABK1GfeMIo5QeXxfCQz6NJuT1qOHU1EtUZ9wy0pNJkR+9Ys+xx0451anoSeDw0bNvcZFr6HsOzLFbBWtTfcXCWagfboo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=FG+0njog; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="FG+0njog" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 80B312C0E27; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1721609921; bh=VV02Np9Kd7WYDspFLZTpFMwWK72ogN13gPcn8ggs8Lo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FG+0njog8cgOJF/tNziMXmA3EkuYdMrEcl2C4OW9xkG56NP3ZanE6u0OvSBE6z3/N PRRjqJYB+LidqBCa+FtTJ4WaACEs7lvzy4GibHPIRtG3tKyxM7sOD5Z8S1Ssc45uAa n6x5FoUPWuuQ4pVq3G5bnurYITk30RLYk2yh0hlypdxb1CzdF5S8DA2U7TLMr1SMPL r2yefD6Mre2eUU0NpeTwlBpE0JcbGbkyqYCKsjKT7TPSfFoNVMhhb75dEWhrYMcfwG Ep12Z/Ct3XWvCx0neBqrA9aQCkAABzujiLaUy6DQu2KKTlznaMDAUREmjYB+kHZ4Z1 wiFT/3BZwTWmA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 22 Jul 2024 12:58:41 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 40F1413EE85; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 3F403280B00; Mon, 22 Jul 2024 12:58:41 +1200 (NZST) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ukleinek@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Chris Packham Subject: [PATCH v6 3/3] hwmon: (adt7475) Add support for configuring initial PWM state Date: Mon, 22 Jul 2024 12:58:25 +1200 Message-ID: <20240722005825.1800403-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> References: <20240722005825.1800403-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=Gqbh+V1C c=1 sm=1 tr=0 ts=669daec1 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=4kmOji7k6h8A:10 a=oTqbJ0pJKTyCvHz9JCwA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat By default the PWM duty cycle in hardware is 100%. On some systems this can cause unwanted fan noise. Add the ability to specify the fan connections and initial state of the PWMs via device properties. Signed-off-by: Chris Packham --- Notes: Changes in v6: - Use do_div() instead of plain / - Use a helper function to avoid repetition between the of and non-of code paths. Changes in v5: - Deal with PWM frequency and duty cycle being specified in nanoseconds Changes in v4: - Support DT and ACPI fwnodes - Put PWM into manual mode Changes in v3: - Use the pwm provider/consumer bindings Changes in v2: - Use correct device property string for frequency - Allow -EINVAL and only warn on error - Use a frequency of 0 to indicate that the hardware should be left as-is drivers/hwmon/adt7475.c | 130 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 4224ffb30483..fc5605d34f36 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -21,6 +21,8 @@ #include #include +#include + /* Indexes for the sysfs hooks */ #define INPUT 0 @@ -1662,6 +1664,130 @@ static int adt7475_set_pwm_polarity(struct i2c_client *client) return 0; } +struct adt7475_pwm_config { + int index; + int freq; + int flags; + int duty; +}; + +static int _adt7475_pwm_properties_parse_args(u32 args[4], struct adt7475_pwm_config *cfg) +{ + unsigned long freq_hz; + unsigned long duty; + + if (args[1] == 0) + return -EINVAL; + + freq_hz = 1000000000UL; + do_div(freq_hz, args[1]); + duty = 255 * args[3]; + do_div(duty, args[1]); + + cfg->index = args[0]; + cfg->freq = find_closest(freq_hz, pwmfreq_table, ARRAY_SIZE(pwmfreq_table)); + cfg->flags = args[2]; + cfg->duty = clamp_val(duty, 0, 0xFF); + + return 0; +} + +static int adt7475_pwm_properties_parse_reference_args(struct fwnode_handle *fwnode, + struct adt7475_pwm_config *cfg) +{ + int ret, i; + struct fwnode_reference_args rargs = {}; + u32 args[4] = {}; + + ret = fwnode_property_get_reference_args(fwnode, "pwms", "#pwm-cells", 0, 0, &rargs); + if (ret) + return ret; + + if (rargs.nargs != 4) { + fwnode_handle_put(rargs.fwnode); + return -EINVAL; + } + + for (i = 0; i < 4; i++) + args[i] = rargs.args[i]; + + ret = _adt7475_pwm_properties_parse_args(args, cfg); + + fwnode_handle_put(rargs.fwnode); + + return ret; +} + +static int adt7475_pwm_properties_parse_args(struct fwnode_handle *fwnode, + struct adt7475_pwm_config *cfg) +{ + int ret; + u32 args[4] = {}; + + ret = fwnode_property_read_u32_array(fwnode, "pwms", args, ARRAY_SIZE(args)); + if (ret) + return ret; + + return _adt7475_pwm_properties_parse_args(args, cfg); + +} + +static int adt7475_fan_pwm_config(struct i2c_client *client) +{ + struct adt7475_data *data = i2c_get_clientdata(client); + struct fwnode_handle *child; + struct adt7475_pwm_config cfg = {}; + int ret; + + device_for_each_child_node(&client->dev, child) { + if (!fwnode_property_present(child, "pwms")) + continue; + + if (is_of_node(child)) + ret = adt7475_pwm_properties_parse_reference_args(child, &cfg); + else + ret = adt7475_pwm_properties_parse_args(child, &cfg); + + if (cfg.index >= ADT7475_PWM_COUNT) + return -EINVAL; + + ret = adt7475_read(PWM_CONFIG_REG(cfg.index)); + if (ret < 0) + return ret; + data->pwm[CONTROL][cfg.index] = ret; + if (cfg.flags & PWM_POLARITY_INVERTED) + data->pwm[CONTROL][cfg.index] |= BIT(4); + else + data->pwm[CONTROL][cfg.index] &= ~BIT(4); + + /* Force to manual mode so PWM values take effect */ + data->pwm[CONTROL][cfg.index] &= ~0xE0; + data->pwm[CONTROL][cfg.index] |= 0x07 << 5; + + ret = i2c_smbus_write_byte_data(client, PWM_CONFIG_REG(cfg.index), + data->pwm[CONTROL][cfg.index]); + if (ret) + return ret; + + data->pwm[INPUT][cfg.index] = cfg.duty; + ret = i2c_smbus_write_byte_data(client, PWM_REG(cfg.index), + data->pwm[INPUT][cfg.index]); + if (ret) + return ret; + + data->range[cfg.index] = adt7475_read(TEMP_TRANGE_REG(cfg.index)); + data->range[cfg.index] &= ~0xf; + data->range[cfg.index] |= cfg.freq; + + ret = i2c_smbus_write_byte_data(client, TEMP_TRANGE_REG(cfg.index), + data->range[cfg.index]); + if (ret) + return ret; + } + + return 0; +} + static int adt7475_probe(struct i2c_client *client) { enum chips chip; @@ -1778,6 +1904,10 @@ static int adt7475_probe(struct i2c_client *client) if (ret && ret != -EINVAL) dev_warn(&client->dev, "Error configuring pwm polarity\n"); + ret = adt7475_fan_pwm_config(client); + if (ret) + dev_warn(&client->dev, "Error %d configuring fan/pwm\n", ret); + /* Start monitoring */ switch (chip) { case adt7475: