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Peter Anvin" , Maxim Levitsky Subject: [PATCH 1/2] KVM: x86: relax canonical checks for some x86 architectural msrs Date: Thu, 25 Jul 2024 11:01:09 -0400 Message-Id: <20240725150110.327601-2-mlevitsk@redhat.com> In-Reply-To: <20240725150110.327601-1-mlevitsk@redhat.com> References: <20240725150110.327601-1-mlevitsk@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Several architectural msrs (e.g MSR_KERNEL_GS_BASE) must contain a canonical address, and according to Intel PRM, this is enforced by #GP on a MSR write. However with the introduction of the LA57 the definition of what is a canonical address became blurred. Few tests done on Sapphire Rapids CPU and on Zen4 CPU, reveal: 1. These CPUs do allow full 57-bit wide non canonical values to be written to MSR_GS_BASE, MSR_FS_BASE, MSR_KERNEL_GS_BASE, regardless of the state of CR4.LA57. Zen4 in addition to that even allows such writes to MSR_CSTAR and MSR_LSTAR. 2. These CPUs don't prevent the user from switching back to 4 level paging with values that will be non canonical in 4 level paging, and instead just allow the msrs to contain these values. Since these MSRS are all passed through to the guest, and microcode allows the non canonical values to get into these msrs, KVM has to tolerate such values and avoid crashing the guest. To do so, always allow the host initiated values regardless of the state of CR4.LA57, instead only gate this by the actual hardware support for 5 level paging. To be on the safe side leave the check for guest writes as is. Signed-off-by: Maxim Levitsky --- arch/x86/kvm/x86.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a6968eadd418..c599deff916e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1844,7 +1844,36 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, case MSR_KERNEL_GS_BASE: case MSR_CSTAR: case MSR_LSTAR: - if (is_noncanonical_address(data, vcpu)) + + /* + * Both AMD and Intel cpus tend to allow values which + * are canonical in the 5 level paging mode but are not + * canonical in the 4 level paging mode to be written + * to the above msrs, regardless of the state of the CR4.LA57. + * + * Intel CPUs do honour CR4.LA57 for the MSR_CSTAR/MSR_LSTAR, + * AMD cpus don't even do that. + * + * Both CPUs also allow non canonical values to remain in + * these MSRs if the CPU was in 5 level paging mode and was + * switched back to 4 level paging, and tolerate these values + * both in native MSRs and in vmcs/vmcb fields. + * + * To avoid crashing a guest, which manages using one of the above + * tricks to get non canonical value to one of + * these MSRs, and later migrates, allow the host initiated + * writes regardless of the state of CR4.LA57. + * + * To be on the safe side, don't allow the guest initiated + * writes to bypass the canonical check (e.g be more strict + * than what the actual ucode usually does). + */ + + if (!host_initiated && is_noncanonical_address(data, vcpu)) + return 1; + + if (!__is_canonical_address(data, + boot_cpu_has(X86_FEATURE_LA57) ? 57 : 48)) return 1; break; case MSR_IA32_SYSENTER_EIP: From patchwork Thu Jul 25 15:01:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxim Levitsky X-Patchwork-Id: 13742027 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 794CC7482 for ; Thu, 25 Jul 2024 15:01:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721919688; cv=none; b=YDd6YIIBruw/p2zPjUAHOxxYgwCmELuyGJ6j+ME06Df8/+Ml+d8b41QT28/8YNLl7oK3evH7a6m0P+CzmhdRzpx+HE7omTh5rNCC0MapQPGa5vyuOvNiNFihj0Ulssi1yW+WMEeMMnPW9zIUaBGycCNvsIAAj0osdjmGxNDkMFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721919688; c=relaxed/simple; bh=KhGQutkuUF3lfyGgp4QnoP1AzxbSh/MzUrDflGzKQWg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=btPte/z3tW8e0Ky+Rt3yzOB32OaYSQ6G6Z41RdsPOyXedkekaSCszgg2AEGu8NVtNeG2Rnpq4eyNcw2YHIeQ3Ll3PNbyTWKPHsFmUaBcSuXgs8pzc/JpFsnp3ZJLHSITZYB6Jn9hIwxhA2ZOkppURnuq0hhTtT29EirhxQqYwi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=QGSt16xY; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="QGSt16xY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1721919685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DVAMN3U4tDyBzO81PDmsnSjhouOzOOdSN5L9d+/nJFg=; b=QGSt16xY4lKkrP6BWn1C647Xh4W9Q9vJS8ez7HWWULbxHofA/gziuj20eNr1v9Sm/YRJgY HLQVT3nCu+v6nMlfXF5+TevKo90mRETyB/oQXhC2WuS92k8Vi7g8125M0TDfzim2xWCCFI cqPjGeBMYpeKLYOabWBKAu7JCLGn1nQ= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-156-A0MbT0NwNbuP-TLZwjqGGA-1; Thu, 25 Jul 2024 11:01:24 -0400 X-MC-Unique: A0MbT0NwNbuP-TLZwjqGGA-1 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id D5B5D1956046; Thu, 25 Jul 2024 15:01:18 +0000 (UTC) Received: from starship.lan (unknown [10.22.8.132]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5DD211955F40; Thu, 25 Jul 2024 15:01:16 +0000 (UTC) From: Maxim Levitsky To: kvm@vger.kernel.org Cc: Dave Hansen , Sean Christopherson , Borislav Petkov , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, Ingo Molnar , Paolo Bonzini , "H. Peter Anvin" , Maxim Levitsky Subject: [PATCH 2/2] KVM: SVM: fix emulation of msr reads/writes of MSR_FS_BASE and MSR_GS_BASE Date: Thu, 25 Jul 2024 11:01:10 -0400 Message-Id: <20240725150110.327601-3-mlevitsk@redhat.com> In-Reply-To: <20240725150110.327601-1-mlevitsk@redhat.com> References: <20240725150110.327601-1-mlevitsk@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 If these msrs are read by the emulator (e.g due to 'force emulation' prefix), SVM code currently fails to extract the corresponding segment bases, and return them to the emulator. Fix that. Signed-off-by: Maxim Levitsky --- arch/x86/kvm/svm/svm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index c58da281f14f..3fc01ba2bd4a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2875,6 +2875,12 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CSTAR: msr_info->data = svm->vmcb01.ptr->save.cstar; break; + case MSR_GS_BASE: + msr_info->data = svm->vmcb01.ptr->save.gs.base; + break; + case MSR_FS_BASE: + msr_info->data = svm->vmcb01.ptr->save.fs.base; + break; case MSR_KERNEL_GS_BASE: msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base; break; @@ -3100,6 +3106,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) case MSR_CSTAR: svm->vmcb01.ptr->save.cstar = data; break; + case MSR_GS_BASE: + svm->vmcb01.ptr->save.gs.base = data; + break; + case MSR_FS_BASE: + svm->vmcb01.ptr->save.fs.base = data; + break; case MSR_KERNEL_GS_BASE: svm->vmcb01.ptr->save.kernel_gs_base = data; break;