From patchwork Tue Jul 30 09:13:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 13747082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25CF9C3DA61 for ; Tue, 30 Jul 2024 09:14:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; 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Features of ARM Cortex-A9 - Optimized L1 caches for system performance and power. - Integrated 1 MB L2 Cache using standard compiled RAMs. Signed-off-by: Anand Moon --- arch/arm/boot/dts/samsung/exynos4412.dtsi | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9 diff --git a/arch/arm/boot/dts/samsung/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi index dcbe0ce6180f..d133c8a8e8d4 100644 --- a/arch/arm/boot/dts/samsung/exynos4412.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412.dtsi @@ -48,6 +48,13 @@ cpu0: cpu@a00 { clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2>; }; cpu1: cpu@a01 { @@ -58,6 +65,13 @@ cpu1: cpu@a01 { clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2>; }; cpu2: cpu@a02 { @@ -68,6 +82,13 @@ cpu2: cpu@a02 { clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2>; }; cpu3: cpu@a03 { @@ -78,6 +99,22 @@ cpu3: cpu@a03 { clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; /* L2, 1M */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From patchwork Tue Jul 30 09:13:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Moon X-Patchwork-Id: 13747083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2125DC3DA49 for ; Tue, 30 Jul 2024 09:14:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Features: - Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event. Signed-off-by: Anand Moon --- .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi index 412a0bb4b988..9b9b2bdfb522 100644 --- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi @@ -59,6 +59,13 @@ cpu0: cpu@100 { reg = <0x100>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -72,6 +79,13 @@ cpu1: cpu@101 { reg = <0x101>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -85,6 +99,13 @@ cpu2: cpu@102 { reg = <0x102>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -98,6 +119,13 @@ cpu3: cpu@103 { reg = <0x103>; clocks = <&clock CLK_KFC_CLK>; clock-frequency = <1000000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a7>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -111,6 +139,13 @@ cpu4: cpu@0 { reg = <0x0>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -124,6 +159,13 @@ cpu5: cpu@1 { reg = <0x1>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -137,6 +179,13 @@ cpu6: cpu@2 { reg = <0x2>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ @@ -150,12 +199,37 @@ cpu7: cpu@3 { reg = <0x3>; clocks = <&clock CLK_ARM_CLK>; clock-frequency = <1800000000>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&L2_a15>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; #cooling-cells = <2>; /* min followed by max */ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <310>; }; + + L2_a7: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + L2_a15: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; /* L2, 2M */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; };