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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , John Stultz , Thomas Gleixner , "Anna-Maria Behnsen" , Frederic Weisbecker , , Bjorn Helgaas , , Ingo Molnar , Borislav Petkov , Dave Hansen , , Carolina Jubran , Bar Shapira , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next V3 1/3] net/mlx5: Add support for MTPTM and MTCTR registers Date: Tue, 30 Jul 2024 16:40:52 +0300 Message-ID: <20240730134055.1835261-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730134055.1835261-1-tariqt@nvidia.com> References: <20240730134055.1835261-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|SJ2PR12MB8133:EE_ X-MS-Office365-Filtering-Correlation-Id: c200e9ab-ed22-4540-0435-08dcb09d8c19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: /PzYTmE4nebYJJ8BRezdYHcdUs0wudZK1A2vZErZOUA/9inNF0Yehf4FJ8chn/zNHnerT/BhQ6ffSZubnc6Fup4TowIoaNM7oJn1yMeOt/2926swWZK5VzsKSBZgf94dAIhmUl3+4rmsv8imfo1d8/fDpZ/1YWCfjqN4/T4006aTAcc5U9sLP9fJXFOvqbIFsAa8TC482vtW4pLdGLEZIG3yLtfZCZkb9A/QBcspq1cVyhaTpl/RN8nJFDmh+TMlB7odj3L1Cd64xKmRp7lt8UXy21TnrMNinp7gbwpdM6xCgmaRM5RFL48vZVOsSSxeIjgQG+Yk4GmS6cY9r9XR88rbwqpxIZcta09CZX6RmMJr69+M2qRFA0e/f6Ix2/U9lXrgEAXOl9qJVBI/V4PzdvovmB0bLCmDGBkfSWYzODDJpDnRoliV60LlfPKaydzgR73xlq9C1n3T5kse+hN1PQtyERB4BGHESYqqITLE4yrnAkC7Luf/wObPIZe/XxI1dhk5ILOfnYtBOWonHMxg3fvEaXUVOQSOs7z/NbCAylCbkSOIrdj8nU+Ki6xjg3a3Og8sNeJHmIvRtCNhVV7vl9fUeV2m5vhhvtnafrjIRW9UhA1XYyzbYzqUvjLbtnf4nfo8iv1zuJdXIu2x3s6gU6EJa/MW+MbxzkMZ3FsonRNb1z+M74aCBK0Yq9snENdeIRP87cy4LhSzPrEEeCg2cHIxpIkHObGNnzyAaclp1s07V3zKkjJ1pR4oQBZ2Z095adguvej/jZRHs6q7bUueZ7GwToCJHU8Ub1QEM3kn8QQNqsjse6WzdX8bTgd8fxDxJ5SE2rIv/S5+ux8Ke/faX4ESAmp4JYO3CyRzDISG9R5Gt7/49CFR9MJSlxUvd6PNEvrxWfkMH1PYsCRMjYorvyaSZcgOqcA5d5iIWmzh05HQHTTXGT5Bn1U2FZIJRokjWEhjLvTbJ6WKV0u1H4MwpYXR927f8GY+icQcCjVsUngQofc5QZa9erKw2hZwZdLy4wMWMBBZ38lffwz1D9ffPNrPj1IDyLGcf9tXoYBPOg+rkos8Un+FMYRuzFfD/5qXBZ8rCcD7Y6s0+sU2jJmPJM2pngVIBeA7IpymkoSUEdFfia/oXhQPhNspt87YdLRh46mcBfTquhsvkYIXXZ3o9c+NHaeR3Rn6WGnQHZi55AqGd8DXH8/7eOLcjPrZUY3yJtiE9/IvsqfK9J4Z9fkfdJSckRamVbj/9bGv4IFGXCJmSznz7RXOaG7RwrPd8FO4GP9Q/BSLXRH0/qBHznB2dgaefYOG6i+MsjHKuAEqGYMNZG4DXf4uJ5Cyc8OMGa8wgK8jCx1I45s/EDhEsV6CAWPgNLfEzFgUvsPswh8Xy7Y96xWo+8PC3KH3mkv3d1bYgyOZ6Dx0W5Xd619nEnM+4/2ZpfPTiHuTbnlUOj39SLoaurQC8d1MIVjZRGyAJBlT X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 13:43:08.5321 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c200e9ab-ed22-4540-0435-08dcb09d8c19 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8133 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Make Management Precision Time Measurement (MTPTM) register and Management Cross Timestamp (MTCTR) register usable in mlx5 driver. Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + include/linux/mlx5/device.h | 7 +++- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 43 ++++++++++++++++++++ 4 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index b61b7d966114..76ad46bf477d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -224,6 +224,7 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) if (MLX5_CAP_GEN(dev, mcam_reg)) { mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF); } if (MLX5_CAP_GEN(dev, qcam_reg)) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index ba875a619b97..a94bc9e3af96 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1243,7 +1243,8 @@ enum mlx5_pcam_feature_groups { enum mlx5_mcam_reg_groups { MLX5_MCAM_REGS_FIRST_128 = 0x0, MLX5_MCAM_REGS_0x9100_0x917F = 0x2, - MLX5_MCAM_REGS_NUM = 0x3, + MLX5_MCAM_REGS_0x9180_0x91FF = 0x3, + MLX5_MCAM_REGS_NUM = 0x4, }; enum mlx5_mcam_feature_groups { @@ -1392,6 +1393,10 @@ enum mlx5_qcam_feature_groups { MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ mng_access_reg_cap_mask.access_regs2.reg) +#define MLX5_CAP_MCAM_REG3(mdev, reg) \ + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \ + mng_access_reg_cap_mask.access_regs3.reg) + #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index a96438ded15f..9f42834f57c5 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -159,6 +159,8 @@ enum { MLX5_REG_MSECQ = 0x9155, MLX5_REG_MSEES = 0x9156, MLX5_REG_MIRC = 0x9162, + MLX5_REG_MTPTM = 0x9180, + MLX5_REG_MTCTR = 0x9181, MLX5_REG_SBCAM = 0xB01F, MLX5_REG_RESOURCE_DUMP = 0xC000, MLX5_REG_DTOR = 0xC00E, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cab228cf51c6..234ad6f16e92 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10401,6 +10401,18 @@ struct mlx5_ifc_mcam_access_reg_bits2 { u8 regs_31_to_0[0x20]; }; +struct mlx5_ifc_mcam_access_reg_bits3 { + u8 regs_127_to_96[0x20]; + + u8 regs_95_to_64[0x20]; + + u8 regs_63_to_32[0x20]; + + u8 regs_31_to_2[0x1e]; + u8 mtctr[0x1]; + u8 mtptm[0x1]; +}; + struct mlx5_ifc_mcam_reg_bits { u8 reserved_at_0[0x8]; u8 feature_group[0x8]; @@ -10413,6 +10425,7 @@ struct mlx5_ifc_mcam_reg_bits { struct mlx5_ifc_mcam_access_reg_bits access_regs; struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; + struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; u8 reserved_at_0[0x80]; } mng_access_reg_cap_mask; @@ -11166,6 +11179,34 @@ struct mlx5_ifc_mtmp_reg_bits { u8 sensor_name_lo[0x20]; }; +struct mlx5_ifc_mtptm_reg_bits { + u8 reserved_at_0[0x10]; + u8 psta[0x1]; + u8 reserved_at_11[0xf]; + + u8 reserved_at_20[0x60]; +}; + +enum { + MLX5_MTCTR_REQUEST_NOP = 0x0, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, + MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, +}; + +struct mlx5_ifc_mtctr_reg_bits { + u8 first_clock_timestamp_request[0x8]; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , John Stultz , Thomas Gleixner , "Anna-Maria Behnsen" , Frederic Weisbecker , , Bjorn Helgaas , , Ingo Molnar , Borislav Petkov , Dave Hansen , , Carolina Jubran , Bar Shapira , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next V3 2/3] net/mlx5: Add support for enabling PTM PCI capability Date: Tue, 30 Jul 2024 16:40:53 +0300 Message-ID: <20240730134055.1835261-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730134055.1835261-1-tariqt@nvidia.com> References: <20240730134055.1835261-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449D:EE_|SA1PR12MB8698:EE_ X-MS-Office365-Filtering-Correlation-Id: e8ffa870-c863-416b-9ca5-08dcb09d8f08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: xsel0lcwgrL7icyLyHUtQDU/1p/zFy8UZJvtuPFdin6SjHQSOllVzP2mLy1GE2SF5OWw3pB/6c446WMvch1YBFVJSdZlGgMLBMpV0dxvnis8DNhTCu6xFG/42SjlmqpLS1tYRO3QNcdxWNQxLxJj66RZA/2aaCGqSZYziv0KSKcA5F/8TPnCUxY6EZj+/izJ5EqBYC2M+BAamqoBzGBk1NsncpahEiRv2PHfb20zqizciKjR+MUZnqzz20d+fBuHrbsuJYI5QIuY5ReEzF/b6oQQzXgY1WEq3sSzAamm7Dx5bQiT6gc+5O70pFYFHZDsvrwonXi18JcD0Wo2cgI67zReJ1EvikQQPfapdyeA4oofEgXU9N0DO5xSUUPXQtwGonN/U3o++0QaYGAzUPzz/KiSLJcS3Tb3Qk6b4xCGHQTkp/Nio+BTmPFkEiITSsAwmK5GgWnQlcQp3K8oZ+LA9CcHbX+yDbp1C3YsTW41Phiw1evETbbds6SkbE9yFAzMV91qiOYFiNptMYyrec7SErdzgA1TYW+Y4JOQsizpJftQepaaDkDnd/mPq5tbbugSUOyID7hGzpZVG2/f4Mr4C8D3QM+8k6KCEvoHFOrONiiYsUvpslEDggM+W5Y33+CV2jpeIjs2zZC2Mle5HAcgBnUn9gdZs4TNRYriI2hHDFH0gzxKGy3Sgvdx5/HDeuN4auLkgg17vQOSp2XICUZMw8H7ErqWehSeRHeo6KB3os55TSGtFpqFNawziD9HCr4h0ne6B7Z/RZSznChLkE1bS9wItGLoixt3fZVo7HTdzagzZSQSwlmBUI30qQW9iMSrkE+pBC0V9jIltL8ee2YbaFFiRHRDrsm6BSRASBQuAhA48qDZhguuyiOMOqurZ1rjqLDcidtqrazdaDSPA/FyC9OmJXQbdHfQLGfvw4aiSNwHKDw5zZEt09olMPYVKNqhXdgc+Hk3pELHrbRBUyOmguGwYaVvhiVURrwiFHI//v7FX9XCbx9/iRCANkz9S2ennYOP4N8re0jOe8VS2LRha3pLgkN8wlBhHMefG1whuDZKrz0SgfbxtTI0NXwVEwG+2jLH2cGfui2c2uqeyN2/1VYpVfdhpPxLCAD01lQ66Mjw59NR/zT+gZ7BKv59SU1/JGH4WVn7AN9Lh/1q3aci4UkcHm+ZYaaTZVwM94Zt68IZoq/XYL852bFdDulKpZkrxFxoqcY65/xfYAH+fknLZMcqvFRuAellSW5xShXlhqA1AL7OeR6CPQZeVFEveeMhvNzADfKbKQQxBjtvWN5dMFuk9qwnNpEp8UsdOuDsXVK28u1JryDXlHNNMyigzLG98S7S/8pUpzS4EnAdhGftek3RZQkQs8onIgMoKffNPy3Gs6qs3dM1XPLK3AcGE1lyIcECY68jNZsB4I1s1w5wettLofcnGBgctRlIPqujexDUkGmZlgYADpDN8B9MJK8m X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 13:43:13.3796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8ffa870-c863-416b-9ca5-08dcb09d8f08 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8698 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Since the kernel doesn't support enabling Precision Time Measurement for an endpoint device, enable the PTM PCI capability in the driver. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 527da58c7953..780078bd5b8c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -923,6 +923,11 @@ static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, } mlx5_pci_vsc_init(dev); + + err = pci_enable_ptm(pdev, NULL); + if (err) + mlx5_core_info(dev, "PTM is not supported by PCIe\n"); + return 0; err_clr_master: @@ -939,6 +944,7 @@ static void mlx5_pci_close(struct mlx5_core_dev *dev) * before removing the pci bars */ mlx5_drain_health_wq(dev); + pci_disable_ptm(dev->pdev); iounmap(dev->iseg); release_bar(dev->pdev); mlx5_pci_disable_device(dev); From patchwork Tue Jul 30 13:40:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13747423 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2071.outbound.protection.outlook.com [40.107.236.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DA6E1A0737; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , John Stultz , Thomas Gleixner , "Anna-Maria Behnsen" , Frederic Weisbecker , , Bjorn Helgaas , , Ingo Molnar , Borislav Petkov , Dave Hansen , , Carolina Jubran , Bar Shapira , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next V3 3/3] net/mlx5: Implement PTM cross timestamping support Date: Tue, 30 Jul 2024 16:40:54 +0300 Message-ID: <20240730134055.1835261-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730134055.1835261-1-tariqt@nvidia.com> References: <20240730134055.1835261-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|CY5PR12MB6429:EE_ X-MS-Office365-Filtering-Correlation-Id: b8241b21-0d47-42d7-bdca-08dcb09d9129 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: gFMKzkNxudx9s8aDItwr+mER42SJb1YKXoPSNHETyBUH9Kv17gP7Zg6Ng2j5zXt6Rp8OYLTPrzZ/q1XeoGYhONObJfoH9FdeJK8UalJVUQ9thy1I5tvujMT7YEnWotkOMv143rbq4aa09ZwdHfIl4594snTQGC/u3VUkO0ks7IgniCMa5wAWd7b2FaEwisaMvkO1zio2RN1CDQAzSv1+jfM/utO3i39CRUUERgQuCIkzBOhmHY8MY66FfKndkKmM/dfQTcEDQh4+ITp2+tsBqvcNt9CZgW8gw9N1fEXBzlPS4nKxRo8GQpvwXaHDRKl78q0RIIZvdSyZod/d/mIP7eP5rXb5rNK+HF8SB18EEIzfr26PHFO4Kn2PfYfbhGFl+DCVAhFUB0WicQhP6rjrUPAQ3K7mzcBqSSCJ/oqzLbK4Mh5AIGtb3so04Umqhqa1s+P6aXT9oNe441qQgGjFmMFQJzLG/szwjKnOgS6pTSy7fNgUy8VtH8+vkFFhnq58dc/SnYE8I39mV2BRgd9JVh9n9gBLi8208waT6wNyWYBSm2RNFKITTrOrT+8S7DCXMabxnf7LmULCtW7yLZrvZ8lQRkJZXiDbeLw75IrS9mY3oqkfdBEf1jkTMo7vG0KP81iOh7wY5XlkYrYQsKXWkTYSG1XJjlys+3jQ5/KWZU/H7H+43VERaNBuk5SNhsXZ8Z41Y9dqpfXEoHr226xjEB2Tqmi5LK0fIZMx+WgUDxTEDXNqJIvXawuHY/9W8SmWfia0/1qBoKXKM8XgQ7vks7wv78LikBKD4vADKi9hTYO6y0A64fwwbBdabcDjkTZHVWpXCBrE0BnOwO5YaYjZ0IlLJ//qrGqF6YuOCOapj+0qd1BVyTvSIBZLeeeoEnjo42sPKu2q4OnX19IBMmxk5dQEo6V6xzuLF6lC+vlGkdU/OHpMaqmO2VdrhmYV5NHzx/GCMTSvG9r/A60QWgJHQCYA3H7YWv1FUlfVK8P/Gw5wEDkIeO9GGkhcrcMbKMcGI++P6/qzsZZy7pVK8waDU8N5l2Ipmz8xzdnDTJiUGTC0dtDCu4dz010IgLRGQaxEUQYlg+Yq/9eApMyq6wfjL/Vu9NXEMzQ/+/TZZs4Z7VLLC0qaT0rmAUinJI5ff+RHzK/jeDMyQb9lowj6VVwbgRWbqpOOau2saISanhwnOLwUiTWrRVPz7XMkAcsCdNs+A2CqFbg+F54fgm2St3WjSgtm/+4lv1jSzMGosaBMN7srefZtCthNcG1uUTgN5TRoSl/NjkDYdvM+sjdZUZqzmc5eq23NtSM21sHFGub3rKGO1YP28CxCHbVP0fRKEXlKm9bNyaRw/W92YynU1uP3ixi7AbvaNKtpvnneQP/5xM716QjRjORlSkIZmWexREJBUlBCTJGElfwGu/xGYpyPb+2aa5nLq2ByzUjvpAzpsaW1cRLlpvj9AjuZ2cn93Z0u X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 13:43:17.0459 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8241b21-0d47-42d7-bdca-08dcb09d9129 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6429 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Expose Precision Time Measurement support through related PTP ioctl. The performance of PTM on ConnectX-7 was evaluated using both real-time (RTC) and free-running (FRC) clocks under traffic and no traffic conditions. Tests with phc2sys measured the maximum offset values at a 50Hz rate, with and without PTM. Results: 1. No traffic +-----+--------+--------+ | | No-PTM | PTM | +-----+--------+--------+ | FRC | 125 ns | <29 ns | +-----+--------+--------+ | RTC | 248 ns | <34 ns | +-----+--------+--------+ 2. With traffic +-----+--------+--------+ | | No-PTM | PTM | +-----+--------+--------+ | FRC | 254 ns | <40 ns | +-----+--------+--------+ | RTC | 255 ns | <45 ns | +-----+--------+--------+ Signed-off-by: Rahul Rameshbabu Co-developed-by: Carolina Jubran Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 0361741632a6..b306ae79bf97 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -38,6 +38,10 @@ #include "lib/eq.h" #include "en.h" #include "clock.h" +#ifdef CONFIG_X86 +#include +#include +#endif /* CONFIG_X86 */ enum { MLX5_PIN_MODE_IN = 0x0, @@ -148,6 +152,87 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } +#ifdef CONFIG_X86 +static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) +{ + u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + int err; + + if (!MLX5_CAP_MCAM_REG3(dev, mtptm)) + return false; + + err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTPTM, + 0, 0); + if (err) + return false; + + return !!MLX5_GET(mtptm_reg, out, psta); +} + +static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + u32 out[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + struct mlx5_core_dev *mdev = ctx; + bool real_time_mode; + u64 host, device; + int err; + + real_time_mode = mlx5_real_time_mode(mdev); + + MLX5_SET(mtctr_reg, in, first_clock_timestamp_request, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK); + MLX5_SET(mtctr_reg, in, second_clock_timestamp_request, + real_time_mode ? MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK : + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER); + + err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTCTR, + 0, 0); + if (err) + return err; + + if (!MLX5_GET(mtctr_reg, out, first_clock_valid) || + !MLX5_GET(mtctr_reg, out, second_clock_valid)) + return -EINVAL; + + host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); + *sys_counterval = (struct system_counterval_t) { + .cycles = host, + .cs_id = CSID_X86_ART, + .use_nsecs = true, + }; + + device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); + if (real_time_mode) + *device_time = ns_to_ktime(REAL_TIME_TO_NS(device >> 32, device & U32_MAX)); + else + *device_time = mlx5_timecounter_cyc2time(&mdev->clock, device); + + return 0; +} + +static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, + struct system_device_crosststamp *cts) +{ + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + struct system_time_snapshot history_begin = {0}; + struct mlx5_core_dev *mdev; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + + if (!mlx5_is_ptm_source_time_available(mdev)) + return -EBUSY; + + ktime_get_snapshot(&history_begin); + + return get_device_system_crosststamp(mlx5_mtctr_syncdevicetime, mdev, + &history_begin, cts); +} +#endif /* CONFIG_X86 */ + static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, bool real_time) @@ -1034,6 +1119,12 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) if (MLX5_CAP_MCAM_REG(mdev, mtutc)) mlx5_init_timer_max_freq_adjustment(mdev); +#ifdef CONFIG_X86 + if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && + MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) + clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; +#endif /* CONFIG_X86 */ + mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); mlx5_init_overflow_period(clock);