From patchwork Wed Jul 31 10:50:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748477 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A81131AAE37; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; cv=none; b=NkBzatWAqsK6xts5CW6viaP2jMS7OfW573E+6zZW8A4Oavw3yYzg9I7F/5MH2BFOxyoH3ZKNKgXgrVbZKS68kxOqH9tDx3MuiNoi8+UGBbw7+HI1Dd3s4as06yD1zx7bQwMi7vnLdswKL+VjHtSYsui6p6NdrKS1SZbi3ONssSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; c=relaxed/simple; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=edhzqvW/V12LPUcjuHm935fVTCmuxj8WO+uJH0Om+xi1xMDOlHV4abCzbOxesFBumwymzjnJfEVnI2k/2xg8PQURooca6ga329beVoKkDsyskuILaevd86rKaV/zE9FkL8E7PwW2L+758qpSoAM97Exj3ljdUfBdCRH+u9J9oDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WaXQ9pdO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WaXQ9pdO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D4CAC4AF09; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=wkgVf0vCUGHv6W2n+sOka0AmnpoDk4tVlRsVgJuMb+Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WaXQ9pdOA5dUYhf7fgC5BakRIJILVN8+72ARYAzlS0x4MsZuI8aGY889KUY/wIS0v nmCbQLJkz8wwxPv1Vk0E6FDSO8dIXkRlnTqlLmJPjizGQ4ynFyJv46egnwNiKV47WE oW6TojRaEWrM2P6zn0fAlNsyTjDbYoOvImWNJGbsd7TkeJ+Pto7S6a2+Kje7fdVjTz hh9MNCOjJ4OaZ04649MhY+45OIEux7KeBfwIvIszIcGmSnBRB9XsHV7bksFOA6+Ahq hGgRmNJIQr5buaHEVsLY4C2rmzAjreVYoNdzRIS/FZtip/cmFHxkuQiLWy9XwpeWRB nrIYYa0Y9f/8g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F9DC3DA64; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:04 +0530 Subject: [PATCH v3 01/13] PCI: qcom-ep: Drop the redundant masking of global IRQ events Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-1-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1288; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=dIwxxT9MwJPav4RVeIZrg0i1F93yyMgBj6gEWSQjRyU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbisXcowvl/yG0UW4O6AGRXi2FMF4gMgakJi Oqhrka2mjuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9TojB/9Rli4WbMlwzg/A9I87MfnXnx6Br1DPfLivGfiGV1jhEMpq76njTF0/nqTmcc/2e8Ocn1I GhKu7ntyec3zfuTjdHmGS85MyK7PMzaApR88hDZfcWUlK/vZn7QfnwLvN0+UoMF95+EHVChlnzW vGRfraBVnLgmhzNI9zSwrMkSLwpiLBXvGfRRIplPwismAf7tzM2y4cDleSPWS/RD8N5UE3MD0Kn cO/taDDMu3CnzhAnqRa+PdY6RDQRQ34jDgk0MK3ryFAZC6M2J1QW1Km4SlL909hrPjuxRzlnQm1 QgRuHMFUTG3/GBiv/8p2AJ8I16Cl75v6rQPVB2YZ49WZ9JcQ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Once the events are disabled in PARF_INT_ALL_MASK register, only the enabled events will generate global IRQ. So there is no need to do the masking again in the IRQ handler, drop it. If there are any spurious IRQs getting generated, they will be reported using the existing dev_err() in the handler. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..972a90eba494 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -647,11 +647,9 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct dw_pcie *pci = &pcie_ep->pci; struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); - u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); - status &= mask; if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); From patchwork Wed Jul 31 10:50:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748476 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80C41A7F79; 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a=openpgp-sha256; l=1256; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=B8RUdvVv9QEg4h2fDtSWIh3luhRVOKTDULQMHpO/Rk0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbiPvlBYFkyQTm0FUkbIjHMH/+/ZAg11HCjV xz5OPlMCDyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9fAkB/9WOZ4Pm2vf1vP5hHdw6Ggj3kP1To3Upq1DZPNUvBuxAfX3SX7dC3Ec1cwU48Ig/RWN8fR 4mB7xUJOFQa+XKdRaAp4nH/I39Pfnze4V4UZuoPuTMvZ6186dX4gm3alkr3ElT1RbwkKXLmUfMt Ml7vht4ZW7OgGLMCWTsNQDRUaddRLqmlrmyhniidJYOYFV/mzfO8HSXDkgwLh23sgVmLoqQ+zWI 5ttBWDYgVU55MHsvjIbhRaG3VJaSRo3CtuxjytmhZu5yJ7EoSDLBQSPzQNVXsPOcj0jLcqVD9uJ 2XmiqdsNSDOyUwy8/85yTfrnuvIoN1yGMptRMN+npS3NWfdc X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Current error message just prints the contents of PARF_INT_ALL_STATUS register as if like the IRQ event number. It could mislead the users. Reword it to make it clear that the error message is actually showing the interrupt status register to help debug spurious IRQ events. While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ storm won't flood the kernel log buffer. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 972a90eba494..0bb0a056dd8f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -679,7 +679,8 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dw_pcie_ep_linkup(&pci->ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP; } else { - dev_err(dev, "Received unknown event: %d\n", status); + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); } return IRQ_HANDLED; From patchwork Wed Jul 31 10:50:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748474 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E382190473; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; cv=none; b=Xg8SZQCZ9PNDdW8HNu7mLh2ybTMlDm781jP05/OyNFJNe5eXFlonGOq1XJkH3lJzRpoSRO9pWpoyU9ZXh9ZeouDCuwfFDIv40grROCx/O1fezsXbqcbEIFgvXHXZz14UTxUf85ycdKbiPeRMv5EVj/xqcOfW5h/k9f9k0AYr5eQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; c=relaxed/simple; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bDmPSL68vKnTyEnn5C+n7K3JjjBibeuKdkWwQ6SiUsDwoYAnMMNqk61Eg1wWBhOi1UIo1eKo3j5j4I/BH4ZSs04vj1H2I7WZHBd0sJf+g3BWUw5vNgOIOAMHkT2c8UCBwksyfYoGPJMbW7jfYWVtBP6tUKv9VVC9p/lLuwZobOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qt823roh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qt823roh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5A06DC4AF15; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=Dynz9QHhPHZXKKO8GD6i2AnmK4GVgprdx9YpUpdCd88=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qt823rohYmRVJijVk2TGpSwApHT+m0YcM75pemMkauB0JNyiYj20EAfYS8nR35U2h gd7x9Z7e76PiKGeKfZ83l3gxRaZtIFuZIGXk9QE6B0pEjGifHbE4giw1bCgUH3ZUnr t7XndlamRYoE3VcZz0O7vgn2uszx1Gwk2O8Dszfeu0fOFXtPhhPZXoXxmAUG2MzF+x +U6fOqCSMAYW1KCz/jUnCFZnZLiXpBdSSDEux0D8LAqOAvCLa/i3UlBEeXduaFutQf BYOLjoSqV8hvWiDGTRjuX2q8rrRV0h8NSxyhhDuQjuF849VmBNifEeTZNJaYA+Aoom u6YIwEBRFsQ7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49116C52D54; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:06 +0530 Subject: [PATCH v3 03/13] dt-bindings: PCI: pci-ep: Update Maintainers Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-3-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1035; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5QyilnsJ9fmtdU7GTZXO3WdPGs0Omyndpvk9fplsO9U=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbiWXLtJTjlNETMDM7azE6UNNZ/+BSyYNgB2 PM0PCX5slWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9ZD7B/4nj0MZlzCQQDaBTKeZ+pE483Fs54t3lKiHBZlOYBnvaoG7FuJfxfVfXauKlHN4Hy/npdo C+bGJAHJxyKGX7wqRJN9HybGr9xeTy7MK7y+yXdifFP3w1hWy8IWWJIoWKsE7YHOBLKrZ1XfHhU iSDMnAbaBPrncZn2M8ZgcteoQUPCXfZpv8s5UfeNi+KncWpMN284N1our24zdgfTKg7UTI226+9 5C8yM2dvlNaMR17hhohIeoKD5f0jtmiU65SOiyLtu2RkTSrXedIwOY2/Hp/fCPHPc2U2NyCxzR2 6OmbqIoxFr1LqLmFQ490KkfbFmwXYWgYnZR9mpm8R2ex0Gbm X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Kishon's TI email ID is not active anymore, so use his korg ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the Co-maintainer. Acked-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index d1eef4825207..0b5456ee21eb 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -10,7 +10,8 @@ description: | Common properties for PCI Endpoint Controller Nodes. maintainers: - - Kishon Vijay Abraham I + - Kishon Vijay Abraham I + - Manivannan Sadhasivam properties: $nodename: From patchwork Wed Jul 31 10:50:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748480 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D17F81AC44F; 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a=openpgp-sha256; l=2076; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=gFM57NfjI22HI5zO2G4ZyvVdTIrBmxWoCkDYpg/zh4Q=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbiAb7YQ78WmQL+3pg/asHYaUv2cb/2l//Pm jyYj96EdqiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4gAKCRBVnxHm/pHO 9WmQB/9si9S+OmgvS+y51lNqf3cu9EerZUXmpMp9BQPH2G/MbNfuM5P1TnLhFhuNHIDsykyo6kf TSKZDjpNjKUtwUKI8/6fVP4laVkYCwd11+WzWiAigELfLKB+3whUNPxIcqxeRXWNFIkGvAHhuW5 oNTVEpq1kZdGX3LVsVX5QLw+c19f8RLzW3/vOnHzernLgouZFW/RT/Pt+ZAm3APCnE34rMIP4a5 2qErJkVovUD40tPkIjPs8tm/Xmj0mVhF4rzufUqkbgiVqSedMqVddEeo+Ro3TCNBK3uO+jD7qsp YbvEvOq0n3LUQ1jVGxkBdTrrxEwOG5Qy1pC3128GwI+Bk4Td X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 11 +++++++++++ Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 1 + 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index 0b5456ee21eb..f75000e3093d 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -42,6 +42,17 @@ properties: default: 1 maximum: 16 + linux,pci-domain: + description: + If present this property assigns a fixed PCI domain number to a PCI + Endpoint Controller, otherwise an unstable (across boots) unique number + will be assigned. It is required to either not set this property at all + or set it for all PCI endpoint controllers in the system, otherwise + potentially conflicting domain numbers may be assigned to endpoint + controllers. The domain number for each endpoint controller in the system + must be unique. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 46802f7d9482..1226ee5d08d1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -280,4 +280,5 @@ examples: phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; }; From patchwork Wed Jul 31 10:50:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748478 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6861AC445; 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a=openpgp-sha256; l=3122; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=BXlRyKpeAPBU8ApmxhAZXpUk0i5orzI+41B2wRNrGCg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbj9FdHKeMCxiD6G+1UyU2wfxZDNc1+O60hg UqJHGlCGfSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4wAKCRBVnxHm/pHO 9X2gCACZgss/FJLmYhOVw+0ui+PzU1lRzLDuP2fHErx+EO93s96RXAHuIPaULsNTNALVWhIA/wU p6NkTxdxXJm6kfyxguZJhDwr0Q827ich5cAe8EuzmDXpBeNkcFUMQRwb7IaFWHoGXMWrvPuOQJY 1q6BkTJszMKY0X0X3FenG4hCR+yPDm4+DaWlv0NHwV4EI7+/W5gCSeI3WL9LB/P4uwKRFglsILY getQlF56PEHwWvscNkOBZTQgPZRQOIyj6LElZZtkBupF7bFunvwsDP75GgQxRWKwZ5SXpXej7pi Zzww/QnQ6bmkLazwx5ijTSqVNH8l4mp1HXMerPdx5EgCFeKO X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Right now, PCI endpoint subsystem doesn't assign PCI domain number for the PCI endpoint controllers. But this domain number could be useful to the EPC drivers to uniquely identify each controller based on the hardware instance when there are multiple ones present in an SoC (even multiple RC/EP). So let's make use of the existing pci_bus_find_domain_nr() API to allocate domain numbers based on either Devicetree (linux,pci-domain) property or dynamic domain number allocation scheme. It should be noted that the domain number allocated by this API will be based on both RC and EP controllers in a SoC. If the 'linux,pci-domain' DT property is present, then the domain number represents the actual hardware instance of the PCI endpoint controller. If not, then the domain number will be allocated based on the PCI EP/RC controller probe order. If the architecture doesn't support CONFIG_PCI_DOMAINS_GENERIC (rare), then currently a warning is thrown to indicate that the architecture specific implementation is needed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 14 ++++++++++++++ include/linux/pci-epc.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 84309dfe0c68..178765e2cb03 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -838,6 +838,10 @@ void pci_epc_destroy(struct pci_epc *epc) { pci_ep_cfs_remove_epc_group(epc->group); device_unregister(&epc->dev); + + #ifdef CONFIG_PCI_DOMAINS_GENERIC + pci_bus_release_domain_nr(NULL, &epc->dev); + #endif } EXPORT_SYMBOL_GPL(pci_epc_destroy); @@ -900,6 +904,16 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, epc->dev.release = pci_epc_release; epc->ops = ops; + #ifdef CONFIG_PCI_DOMAINS_GENERIC + epc->domain_nr = pci_bus_find_domain_nr(NULL, dev); + #else + /* + * TODO: If the architecture doesn't support generic PCI + * domains, then a custom implementation has to be used. + */ + WARN_ONCE(1, "This architecture doesn't support generic PCI domains\n"); + #endif + ret = dev_set_name(&epc->dev, "%s", dev_name(dev)); if (ret) goto put_dev; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 85bdf2adb760..8e3dcac55dcd 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,7 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @domain_nr: PCI domain number of the endpoint controller * @init_complete: flag to indicate whether the EPC initialization is complete * or not */ @@ -145,6 +146,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + int domain_nr; bool init_complete; }; From patchwork Wed Jul 31 10:50:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748481 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F20E11AD3FD; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tADzGTzL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7E618C4AF55; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=Q0K9d834m1CQs7L6nrAh8i7+sVcfqEywtcVG4UQJkH8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tADzGTzL2PY4PO3jGpgBwqKvvBdwToY/m496qAKPpASdKugGWKnPsmuMx/qEZbs8M zwCF4w9vUjYhdFtReNXpuwCqheBi1ufHeQMaIFn1R2TdTPsrfa9c/m/fWTW3Jr2wYQ GqqrPx7c77RglLXsY63t+ZLSLLfLOPL/AjpiG4gOrWmuBT/W/uhNNluibjXlhcEWah hkJlqw2JwUZgtRTnR4BGNY6WPzBrZKw6a3DRyBvXdIC28/SzCTaK+17fiVswOfEsZ0 YaGwbwWIhDcF6mp6vPU7S2T1uMaBYv6bBJF+VP0sJ6cX4G7olkNVQVMKt3EfuBrhxJ PZ52/zg+7v0Uw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B07C52D6D; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:09 +0530 Subject: [PATCH v3 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-6-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2506; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=XIcVOnjgniiauSeztC2lx8OOqKBgQWPfU4mlz79I8zw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbjGGaJwKyTvqkljnvL/tqJQd7uQOxHG/eYT WrBEXYQUN2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4wAKCRBVnxHm/pHO 9WXwB/9aBNdScpakeH3ElJt0m4uB42SoSv/w09HA2ygZJIMQokLZ/4NylCvJKLQZXESG8sTXEwy ITY1NFLtltXxVWFExWLPkHqS5fr9r3ImF5/s6M0mRF/+gQYDytgWia3UkiHsBAYPvinFYU9010r aTYBuGk40rxSFqQie513l6Oc/fwGtDg5lGLHoMM8CtnLyeLOxYZihW3gBWBgVvaBrUxMxDcS2+e Vxaga9S1XfQ+ZuWn6xJKICujexiTeNyN6w2Cq/YNvnDJgARFPWW0TNXUsF5si7ANp8I+ETlzqpW +T5r6DvqlEXJiIbsvW9L2TdEJyNFSb3MKJfQjFTdHDtkdIk+ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Currently, the IRQ device name for both of these IRQs doesn't have Qcom specific prefix and PCIe domain number. This causes 2 issues: 1. Pollutes the global IRQ namespace since 'global' is a common name. 2. When more than one EP controller instance is present in the SoC, naming conflict will occur. Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ names to uniquely identify the IRQs and also to fix the above mentioned issues. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0bb0a056dd8f..d0a27fa6fdc8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data) static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, struct qcom_pcie_ep *pcie_ep) { + struct device *dev = pcie_ep->pci.dev; + char *name; int ret; + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->global_irq = platform_get_irq_byname(pdev, "global"); if (pcie_ep->global_irq < 0) return pcie_ep->global_irq; @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev, ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL, qcom_pcie_ep_global_irq_thread, IRQF_ONESHOT, - "global_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request Global IRQ\n"); return ret; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d", + pcie_ep->pci.ep.epc->domain_nr); + if (!name) + return -ENOMEM; + pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset); irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL, qcom_pcie_ep_perst_irq_thread, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "perst_irq", pcie_ep); + name, pcie_ep); if (ret) { dev_err(&pdev->dev, "Failed to request PERST IRQ\n"); disable_irq(pcie_ep->global_irq); From patchwork Wed Jul 31 10:50:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748482 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0B961AD3FC; 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a=openpgp-sha256; l=986; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=+Lb2vcF7RPFdOyct+N0+V3AMTmLDYS+SRQY7Fw3HIuE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbjkTiApJTNTSUBKI9q0eAZ0la4yNkAKIvRj ljKbglV8RWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4wAKCRBVnxHm/pHO 9QfVCACjGPb3cSXofPXXA+xQOK5VyTm0JsWjYGlVhpBRR3i9m8pYPFc1wJeOTKGJCfgCkj1oRc1 Xadvp5Uc3OD6RDssrwDZ8B1rbpqb0Zqr4ok5k/1/BEtqKVl9UgtRlQ7yqlMV33Z6E/EhAbE34NJ EPL8Y/A6JerH7OLUlAPOrqlk34iLQkyFGH2g3iE+0qp70ZH693eUFTLdR4DM+LYADeyxJSjfolu VqcFT6b8IoSRFoemRQMBZfkoC1UZCo6NkHpBI71o10uV3ibDH5skWSykTBrru9jvbQ0DOf1P1mc d0f6RohT1YZdLtjKWAmZEWPzEQNGQ08Mg/EZQaGugxxFdbwP X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 31 10:50:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748479 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D32A11AC450; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; cv=none; b=A1/F+m8ULJMG3yIAk3zNKrTZKv5dDVSDeH3hTMdGfLo8A9QkkfWUilYHn8fdfhBNol/1ryykpgrL3TIBGgvgI6V30c4YR9xawof2hvIeNeTVGhRFPGb0eDeFoJi4nWJbHI5u859UItNJroTNjVvrU1Cd5F4z2U3dTOjx99leAow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423018; c=relaxed/simple; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H0VxboazysybTT3FrUd5s1nAzY2lSx5JaHPtD5lIY0Icy6RyCiBOwpcqF8e5wfK639MlMveBF9r503BHDeM3WxTJvHr5mEnMYiQjjNvgkFOXSepODp2sTy4IEuh1kaptdf1Ar0MADpUtTkP63VmuO6r7ujleIwFJjn2l2l4YvDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YRGmKUko; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YRGmKUko" Received: by smtp.kernel.org (Postfix) with ESMTPS id 999E2C4DDE5; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=I2wSRHaYDVrxwX11GGk6+ukp4VyqQ6OrIa6J7s/t3jQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YRGmKUkohGUwSCohzekyye3hQf8+259YSxxDyTV+ef4cHWfxt1+sUcVwfL3u9cZl1 wUUQWwEMCgRcSor0wNMKQLGna7yGOkWdgrTphT5Vpr612T4/hNMdOrJ7Fl65irqin/ gOsKJcCOjysE2yqRqjHFUrVa9vqy2p0I1vr6c3JMcWzoxZhdSbw1bkugy/oDcdP37u QFAl1BrCoPnEQwQU1qfBYD5lcXvXMmfwLNXOuiXkJEh44uKdttryROHkrM8/ZJP0nq WjzZ7y3QUG3eXtWUND6yEveY0WbnToY2uQH7Rf6R25ul+apyVRHizRFSBuLIuJmfPF Qu5He5V/je2Aw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90934C52D54; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:11 +0530 Subject: [PATCH v3 08/13] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-8-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=961; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=4ksb8gQi6XxtqZHvRIfOuO8m7D/GXep6HzglfrtwSCA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbj6AuR19gVgM6SXGBTiRSNQwqVP0FlXbfOh dH/EI7xJimJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW4wAKCRBVnxHm/pHO 9VW8B/9MUtYiNGVpuIfJAqYCVOzwF+YamFjxtReGIZzZB/h1zfMILBFtGv/iiAQf0SsENP/AmQK 7lQtHhyCTi+jSGUT8HlUMLN8k7Oreavy/lwt6D1/qZ0BVzRpdI0G+vYAuCn/X3R6K7N5NPkequ9 cbIT30CZawkFf+Y8LqSQNhvS441+zuQQlEzXg3MLqf9kuBtyQhmWKHHTmEyhH683xm0I5nTTXMS cGfl+gtCrRqjAfmyIE+lw3eOgGUY5kYoVm50maTvndVm4gC8ofnbApX9Prw15Euh4b4dxT8gdEE /JcYse9jgoAz2xBLPT8t6UEtXmmpB8OuWg7t2PfesumKpaMr X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..fcfec4228670 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From patchwork Wed Jul 31 10:50:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748486 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195C31AD9C8; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423019; cv=none; b=GFq/6Q9p6SFkZG/AN8JEwTwPB/GYVf+j3kW60lE4k2FyAtxdumpE0wNrHKgQgAG9K5+y+8jJZjukJ2wdz4+kqubrkke+GtFQptPJZc/kVC29+S8oOUDpvqTvCprE0H2hBOmQQ8omi2RsUTkFqWgRw61MXGUEt9ZlkgwlvMLHhFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423019; c=relaxed/simple; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BZ7jMTU4piFWl71rRvrRYfUVMqfvuo5Y/qCaPyvadN/THlLFCQVT/g9kqKwILXERz2/fD8OFiSs15CJOCeuiaV+mgLj9jjgDEDvqMnXqCuF0sAZPERPd7SHNsLZpMhIQ5ntpvz7SQKuZBU5HoJ4m46157D59gTiFeou2bMI1M7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DjizwBrK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DjizwBrK" Received: by smtp.kernel.org (Postfix) with ESMTPS id ADF4AC4DDF8; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=9SpPkeVArnB3rJ4nPZ0WPdvcC8ctAG/YXTHNpaqeYTk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DjizwBrK7cTEZVihDNocrp8MBBartldGNOXR8giX5ZWDA3VtFYju0r/tBf6E9ELcK nGiF5hZ3g5Br0GUE2zOnZBDiJzJLIJ8F6snkGFifwyiktTnDFQdsBoX7bfrdwiAZQs HW/Gyers3LWZdABTiTS6peUbv9L530BINZLpeEStt7OTsH7u+aD83ItazL9Gl1I47x jTlx6aQD1JgM5da0ZIdIZztu6B3YsIGHLiw1j6eLeUMBYaNHIDXmbFonMqZSp8/Ns6 EQJCcvDzEfwsVetijCHR8mf/uAMmVZSIsd/N3FdPwb0Uj6xofO2GQ6Cdq6BME1IZLL iSY5Qy8aebaiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A017BC52D6D; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:12 +0530 Subject: [PATCH v3 09/13] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-9-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1289; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=YKSy5vPklQvLJA99UbdPy4mFyoiPQChYvArhByAGkpA=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbkM82d8e+WMgMaI3vqUmCsTncdYX2eiPFOn D6P6KY6mfCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5AAKCRBVnxHm/pHO 9YEMB/96o/GgxfmiCVskdaEk9lPriojnKoJwUFGZq0mTGD5vspGq5yt7OLqRTc/vStU7UIJY+a9 3yHXH8lmdrhtjcvwvOlWDCzgwgxFOgh6MvqlWoyYVnJrXyOFy+F0eNMsiC0BoqfZOJsem28kgWT hP2l+54I7J/ulzCMjKc+rrRE3ffQq6YyPEheNyKoG3bZ/jWNpoHqodHXUqXXvLA5BUzWBjG0KRZ sWb9TNcPiz3rjPG53KFicTsoUTDDKbNS7CKp7kimQV8lwYrVqYRU66gVPePhCAn6ncejK+a4d1G cjpR1PG1aN2a1ISPBJYeZO3F/zor/dTi4OMRp/uLoEy4S+dS X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SA8775P SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..198b39abde97 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4618,6 +4618,7 @@ pcie0_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; @@ -4775,6 +4776,7 @@ pcie1_ep: pcie-ep@1c10000 { phy-names = "pciephy"; max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; + linux,pci-domain = <1>; status = "disabled"; }; From patchwork Wed Jul 31 10:50:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748483 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17A7A1AD9C7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P+5qO3sb" Received: by smtp.kernel.org (Postfix) with ESMTPS id B8AFAC4AF10; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=gpFkVvbXM7bCqPYW+aDVZ3Ody8SHFkjq1FkAoOcZ9yQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=P+5qO3sb79fLAyF9fvmvcKTmA4B6eYk+6h7wUyLOghCGPZ8xOhU6O6z+cAzde5urP 1fTEMlKet00g7wQa1IKwB0gC3jPrTlLdkDAfAg7Z/O1xhNGEX7Qn+2yKSYr9yzpqyp rq6fCxukuOcJ9vNMNzJ0f9M0xaDGt7Bmx4doFwFeiQAPz/de5jZ40vjL2F47h7fZQo 1Hj35w/YhebBrHJLB72l96oU/GOTgNsp6Ua37ee+8RmpVp38VJa5BSGOFliwXQ9fAh yx5CFRAJPo8Y9QQX+Aur57XYJy5la/6VnFu4+p6Hf3fUvTKWQkHDHtIePqt1wD6cKi OliPpdwCunzTA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFC74C3DA64; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:13 +0530 Subject: [PATCH v3 10/13] dt-bindings: PCI: qcom: Add 'global' interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-10-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1044; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=UnqChimHBG0jtzlN6KxFR0yebxEqg1erfRRq9qEP0p0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbkB/cWBxZAuW9kvnCZmyNplxRrctsF4Cguu 0gi2zs5h9mJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5AAKCRBVnxHm/pHO 9V6YCACMPaLpig/X0T0VKYUbdat2nq1pdJKlbyHurTfL4nDpP54WIHkmka0L/wiJ52wjEtze+2q pcRhyrMPNtZbc8D6/fW7rF12kfYbPwD4oosxWbXYEfO3h/ffv7FYf1wHY7JAG2PRYXXWpkDWzlI DoKRA+xjS9KOfUEis3kCTQ7Kt2L/yq9n4rhSq9njHL+FvcYOiOvZEPWwXVCfwgo9/tOSFGp88Db GuI5usUM3Eh1R9RQ/AdZ8ssCEwjLXrp0YzsYLhBA6rPWwxjcPmeUubKnKDf7YyLhWtS+6HilwIH ptrgYF4ULjjhUHpJs52fUqawGxmJUecGq4pW5xGsPgiJem68 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0a39bbfcb28b..704c0f58eea5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -21,11 +21,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 From patchwork Wed Jul 31 10:50:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748485 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 005371AD3FE; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gFW3TRwL" Received: by smtp.kernel.org (Postfix) with ESMTPS id C5A46C4DE03; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722423018; bh=FDAyuVhiZfadF2+raswbfNBa/0aOcWVYQKsBdgtWLgs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gFW3TRwLRi6dvDK10BKiOU9WO6I3foMmtFaUvMylpGyhbBdU8XHCG5sLfuDxVXxRL GXPXojC9e0xvu2xyUIE83Of/VXU4Aa5mjD9upw9ON4gHGNvstKdWJPAzaQB4sqGyTd 6SHqn/WSCvF6tufSYzDojmW8ymloB+lUPkHjFFzRAgzZC1thP4SKfU7dmC0E3F0aHz ZSNIQRFIxRvxiJwArMmbb+1pkXM/mKPwdVdB56GxuEkVK8nWHaD20w3fnz+Vc/OveE RBq8QX/ckrky5R562BHXgDD3XFbWhNWF1JyTFS/JoZXVQ/R6KkhNbkwsY4qWrraiFU GRSo2YJrsvzAg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD052C52D54; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:14 +0530 Subject: [PATCH v3 11/13] dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-11-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2096; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=w4cY5FEuD1vubOFd7Zhbt7y5H9yLj0yvZBQOIyWPebc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbkakmaRXQMThiXty5wzJtqGzDoKQJJtmLBw VRycaPEeJeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5AAKCRBVnxHm/pHO 9dngB/kBPbwnipqgE9LYCyvM7tsqZnqrzPBVSl+ShZO4DBdntLhupwJWwoBGIOLNCS4UPNmNkI5 aEu/3uV3MI7G6IiUxXbDsnbH9bTKYNrmM9hLySVzr+rvvTbZJV2YeHCya65WOQCpWIfDwt9cVaC RZgwv3x9vnXEc2lF+YIRgzogwadwbn+iYCYh4Ykrze5gut+mjGsxdNiJa2euaF+d7r4g22h8HJG lA2aPMhzwKrDj5zjG8dMTpiyGlAWVnq9gBRRVvFQaHLjj+oKAK53jWHuPaM/NzlmkQveKEYVxY0 hD4RHBZxKOQjKG2lASxkAkCTX9Ec8SPNSiw9H7LApYxU9gM1 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index d8c0afaa4b19..46bd59eefadb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -55,8 +55,8 @@ properties: - const: aggre1 # Aggre NoC PCIe1 AXI clock interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 interrupt-names: items: @@ -68,6 +68,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global operating-points-v2: true opp-table: @@ -149,9 +150,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Wed Jul 31 10:50:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748484 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 146551AD9C1; Wed, 31 Jul 2024 10:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423019; cv=none; b=FbWI2Ufsr57y4Y3msfwLp8ajPvp9MskU4SxASIgO+zkrS4qLj5WbsU1vcfJbZSfuBDvno6gTxffz+X0uV/eTafxdPDFqKX3qlgPVbsDhNSKV8lK413nhcyUdotfYCBrrw1oPEDDIVqpoV7iBpuBcXJUlZAK7Hs935tpMs2wGVgo= ARC-Message-Signature: i=1; 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b=TzLK+2k+6W5NDPMWtmybMxenGvTwpHw2JPvNP6/9UdOiIrOGxqgw/5hnVZORHXwW9 WYe268cORm7oPpNP+abI16Ud2CbfdnFNVopE6B4xm7nXOk27S+rXlmMQZDs1TmoM0N 4pSiUh4EWqKDaw7is6Qeu4wcD41Bp2FtbAIAXnTvRadW4IQg0uzRzaWd9+BXcbpRLz X+MeHdPEuFnrvADfD+2VMRm8/UoFHI75/gmJxBIHsGeOjCanlTQctKqkMf3c9iaC/9 gmWzDgpLKmA1sE0OyBBKpOPY2G7pCCwvShGNNAtXE4n83A3bKurmAQ5idcjVv1zHvz B6R0YNPBqu93Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA45CC52D6F; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:15 +0530 Subject: [PATCH v3 12/13] PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-12-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4505; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=rrwYXBkV1hJCf8Vji/wBdBUFZOTu6YfGKfdoZ3owUQ0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhbkReygRn/p2uDcQG1HzkywBXSXv30bcCccD oaOZNmA5keJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5AAKCRBVnxHm/pHO 9bhrCACI29SAnOLtxLxWWVL8j80mGZVCbgslq9UHUXvgfm7ugC8obni8/WITptobsysnLhqmrfG NitRxdc8yWegl4GBuPTuGnMoLIyhvW5+mKURSkwHeMkouF3Xhxj+TC10ndPG8cNYisdRx+Dclqp hTEWTw22H2VGVvGgGjQTkJ5ig1kA2V7zlsa8slQDsVhCrahNqcxNUF3UbVImEh1lRrKd+69TFci ZLDav8k1DjIh1SkV3he28WQQSymqm7sS7AsvCSy1Gf6X+CmVNqYBc4k4a7Mtf7X4p8t7c4V+JKS A3esGtlXrV7+CwpBeQgSLeAu8AdKMJCUjMWngE5aXDm/yWRs X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Historically, Qcom PCIe RC controllers lacked standard hotplug support. So when an endpoint is attached to the SoC, users have to rescan the bus manually to enumerate the device. But this can be avoided by using the Link up event exposed by the Qcom specific 'global_irq' interrupt. Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt to the host CPUs. The device driver can use this interrupt to identify events such as PCIe link specific events, safety events etc... One such event is the PCIe Link up event generated when an endpoint is detected on the bus and the Link is 'up'. This event can be used to enumerate the PCIe endpoint devices without user intervention. So add support for capturing the PCIe Link up event using the 'global' interrupt in the driver. Once the Link up event is received, the bus underneath the host bridge is scanned to enumerate PCIe endpoint devices. All of the Qcom SoCs have only one rootport per controller instance. So only a single 'Link up' event is generated for the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0180edf3310e..a1d678fe7fa5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -50,6 +50,9 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_INT_ALL_STATUS 0x224 +#define PARF_INT_ALL_CLEAR 0x228 +#define PARF_INT_ALL_MASK 0x22c #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 @@ -121,6 +124,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) +/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ +#define PARF_INT_ALL_LINK_UP BIT(13) + /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) #define RD_NO_SNOOP_OVERIDE_EN BIT(3) @@ -1488,6 +1494,29 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) qcom_pcie_link_transition_count); } +static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) +{ + struct qcom_pcie *pcie = data; + struct dw_pcie_rp *pp = &pcie->pci->pp; + struct device *dev = pcie->pci->dev; + u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); + + writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); + + if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { + dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } else { + dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", + status); + } + + return IRQ_HANDLED; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1498,7 +1527,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; - int ret; + int ret, irq; + char *name; pcie_cfg = of_device_get_match_data(dev); if (!pcie_cfg || !pcie_cfg->ops) { @@ -1617,6 +1647,27 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } + name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", + pci_domain_nr(pp->bridge->bus)); + if (!name) { + ret = -ENOMEM; + goto err_host_deinit; + } + + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + qcom_pcie_global_irq_thread, + IRQF_ONESHOT, name, pcie); + if (ret) { + dev_err_probe(&pdev->dev, ret, + "Failed to request Global IRQ\n"); + goto err_host_deinit; + } + + writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + } + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) @@ -1624,6 +1675,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) return 0; +err_host_deinit: + dw_pcie_host_deinit(pp); err_phy_exit: phy_exit(pcie->phy); err_pm_runtime_put: From patchwork Wed Jul 31 10:50:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam via B4 Relay X-Patchwork-Id: 13748487 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65AA51AE85B; Wed, 31 Jul 2024 10:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722423019; cv=none; b=AXb0U5e7zkUFsv+p5IThoP7FOeXsRw6F0PWv8K3R8ka+9uZP0wnBzIjesEcbqWkqA0QN+jkghL4PTQedTfGKQBdExfUqUogQ86XVF4ujDyQQB5dYdbcLoGZKGLtC9+lHCq4wiaunwFERcCQF7pynjPadrEkF3nhw5OK/ZwblJg4= ARC-Message-Signature: i=1; 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b=OAjXf2G4LCOEymiGO7ORtgF+gakvZV8CJv1ilww9RybwroRbNcQIaAP9TngOs6Ns7 I1Q455f1Ij6NFwTa2tYeS6MV5qpzLbgro3BbnbH8quMteDHyZsjHqn+SXwvKBxnZ5Q D/Lm7L4xEuVzTx3jJr2xt/hzLPHzjqT3aDuyehvx3kpHr5F+5ZEsIuoWCfCP12/I/c e1/DVUBLWro2Gw9BgNyblG1T9lDKWqpUQLvegUAJDbGyV2HMkTLl4zy43OnG/dQfNy mIH9s32EOD8BPkmHK25Bq7tMpBv6JDTllqs91Hzi1KlHjacjwyosQEI2Fmk9q2hBKE 4lDH9ldsGfxaw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB020C3DA64; Wed, 31 Jul 2024 10:50:18 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 31 Jul 2024 16:20:16 +0530 Subject: [PATCH v3 13/13] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240731-pci-qcom-hotplug-v3-13-a1426afdee3b@linaro.org> References: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> In-Reply-To: <20240731-pci-qcom-hotplug-v3-0-a1426afdee3b@linaro.org> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2085; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=VT44obotCPUBbxvMUSiK7oaxSibx2Iio+dz6SHI7KhE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmqhblNzaaeYw8B23DDeqkEmh17nbj4nLf1+plB bbD5W/MaxCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZqoW5QAKCRBVnxHm/pHO 9edLB/wJfinRqT1ZaIEqmwdeCglsOvXrZYFwynjzpwkrwDnq/VJXpKxc1EYNUYndw2kJsnQnkjz MJy1k9utlvQI1HfHcGl3AjAL+iS0uVExZabdGUpQaKEFJCf1hr/UiiHh486UCOfE0wCJhni1TvP EuXNGESFIBsIcAf4XzYP3OfIIafC6g5fLA5r/6A322EVxMdCy+/kLv2gczMfVf/5ZyZQOGBiW9F nir8hA84oZdJsCf8xy50ulrMxrgwXDT3phbIQ2cbduZ1s3ltdLNosD2JIUuU4H/xwRcLh5ZxG3/ WrTAx9Z1hH/oQQ2lIK73Bi73atywSQtqCQvEs0hvAS+0TUtk X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@linaro.org/default with auth_id=185 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@linaro.org From: Manivannan Sadhasivam Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9bafb3b350ff..564b071eb77c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1787,7 +1787,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1795,7 +1796,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1949,7 +1951,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1957,7 +1960,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */