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Peter Anvin" , Thomas Gleixner , "Kishon Vijay Abraham I" , Kim Phillips Subject: [PATCH 1/2] x86/cpufeatures: Add "Allowed SEV Features" Feature Date: Thu, 1 Aug 2024 20:57:31 -0500 Message-ID: <20240802015732.3192877-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240802015732.3192877-1-kim.phillips@amd.com> References: <20240802015732.3192877-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B371:EE_|DS0PR12MB7900:EE_ X-MS-Office365-Filtering-Correlation-Id: ab30985c-0758-44e5-a52c-08dcb2969f8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: mPZtESdfMfkCOqtRLAHYCWuhQ8QJmlYRmE0USEhfyg0u5albmDZqwXZ8dmzi/U3rY3Ys/GB2X8bhJgjJfRXamcE62MKW3ofRekUSMefe46Fyd2pmBo78brqsXxJwIABVZ7zIHg+lTq3zQSpCsm+F8c3nJtPLJ/5sinpf5Ag7BLw8H1P2US6YzNZtPY3W23SJ6xEjWaQMYyBQ6hVEGRiI59jBCGGdQmVKWm8M3ZOiqDAsEjj90e99LYYLEbdeBcG6Sk7b4WtL2nfIMbj3L37IuFcCDZXjxDbjok0FTfSGBOqZqe89T62wBk0RP1rG1yAGlb1pLTNVhlFJVVEyEwnvDmUeAtXRYdL+9oI6UEfHUDRQN+9MpetnUlwrzUlrrKqU7EakTiw6CizM9z5VM/63NVyMXn2fE1/TKPham5yBp7DYWO1GbKtzfS2h1OVzSPqBAgfN11BosjcxIOW2RNmOtHDJhHkheQkZGRoGdJsmdwwQZft+6wTbYmiA6uXFTVxlJYGOX0fxtFc+meJTEgFovSgN13CJqU28W3xXizt4HNr0THuct/oLLvhu7TWm+5e6pj1u3TvATEkTvXnErcnO3MnsLIkxe+fqNWOZ+amLb5zqG7YHbyUSyJxMW9WMl9HbTEokBUi8/XKH6sutnw34VnLFV5dcIqAweCpe3Q1QNDTv8qOnwx2LdftUSQ8Ww2848lnxw82I3K62AultpXHyiuBPpS7zbkVaL6hMkLGFipG72+1jKWP5u3mQl8P3kDkhQUXBMQo8JHnuchNNxgqjuS9XC2A2xkPMObPySPNs9U4hlc+faMZH53VwFDK2znonmfdPMrbC+vs+dNDI3C4dJCmNT9jpx6TROQKuSWhsMG+H0daKJf8xl3AMsNKV7TGzJzV41iJbIWhDbPChpnMkX+MzW5uiMdF2+lDfLxvLkywsY0bwjZTxQIorZzo/ERVfJblAoLK+m3ztFjoIHZG8YEl0JTfzar3BmQjicNOA7TbgkIDj2Jnx542c7s10B918BMzU6Mg5zz87WKhJTWAHckZqzUWo31cvu6Hll2Ns6EHNHPr6LNh5WNWI4xB25FKQRJgKk47Xl0fGYwaIrv+f02uOf9bIu3XoatnoM1vAXgeWPlS8/8W/3ucPOPUEsjJauYWwo984/6nbZCStER+QgwWPXuV2kE+MJhvmj0NFHvKP13qvweW9iQ82yjyQivlixqbbzmWKIhVws5Oi9JgbtoY6OcDw4PAvYF30zk8yohFCL0dNNZL9AjaCdwHI0Sokdi/rSNhCywtEDN8FIZGaEEL1MezvItyI/ma5DTMbNdoJkRRGqFw0tvPSdOrb1Y6vb65gIaiNKMvEErlGICD6AVz/67XGs81OrsjRv0WfVR7CEmxtncNXbfhDDn6jKNRnS72s0f8U0+Pvu0ApuK/bukQHbDjCE6pmTy/dV/iMvzlSbyEt3vZC3nsMzUCfMRE4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2024 01:58:36.9904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab30985c-0758-44e5-a52c-08dcb2969f8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B371.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7900 From: Kishon Vijay Abraham I Add CPU feature detection for "Allowed SEV Features" to allow the Hypervisor to enforce that SEV-ES and SEV-SNP guest VMs cannot enable features (via SEV_FEATURES) that the Hypervisor does not support or wish to be enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dd4682857c12..0c73da91a041 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -447,6 +447,7 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */ +#define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* AMD Allowed SEV Features */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ From patchwork Fri Aug 2 01:57:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13751010 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2066.outbound.protection.outlook.com [40.107.101.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6520EEEBB; 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Thu, 1 Aug 2024 20:59:03 -0500 From: Kim Phillips To: , , CC: Tom Lendacky , Michael Roth , Ashish Kalra , "Nikunj A Dadhania" , Borislav Petkov , Dave Hansen , Sean Christopherson , "Paolo Bonzini" , Ingo Molnar , "H. Peter Anvin" , Thomas Gleixner , "Kishon Vijay Abraham I" , Kim Phillips Subject: [PATCH 2/2] KVM: SEV: Configure "ALLOWED_SEV_FEATURES" VMCB Field Date: Thu, 1 Aug 2024 20:57:32 -0500 Message-ID: <20240802015732.3192877-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240802015732.3192877-1-kim.phillips@amd.com> References: <20240802015732.3192877-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B371:EE_|LV8PR12MB9418:EE_ X-MS-Office365-Filtering-Correlation-Id: 079b120a-6d8f-4b8e-0d3d-08dcb296dab6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: UDjGmz9KnMSyK3e2W/nY/H1aaUkk8q8uZO/+suutWGCCmnk3FpWzyz3g77JoJAqCkCf6l6gDm6kmZvaVz3bOpSxqOZxjUM0Ibo3KQfW2hPA3iPsuT1B8/nJMWLAFTQqpets28+feS8gW785cvBfSrpHNl6FlAtgcL0LEv/Nj+Qikmbrzdg22yWmcQSXuxzjlyrS/NzSOuU3cdsNbU6wpdexyrNxpamCoBRuSVMQrTlXfD4VKwPRybttzv4UlyPj7aMCMCH9qOSEZj90Zj/FfRwfGqlRrmWWVZdHefkbtFYdkr7dUExgMmFSpDu6iSv7/n+vnhPdER7jk+0k6mRIEE8GkL6yGYYxCD4Nat2zSi45vf0kb9ijRxPbYvlNFB++IXU+rSxlfdPEqLhQ2zUsAG88SQyeXjUBT28KaTlzToBk1fHVgmM+2o06bFT6CwsImHsc8FN1NYa5DciIlFE+FrK4hZuLifl5xfscBzT7NNcG7EyZRoHywoRqJl88rcRZVQ/xfBaRN/Uo8pwvI58wZKxfPV4qaXl/AF7dnUZvBEvMoT6EB8V4NmXu74+TM/7skBBM/xH0/VA0+6+vt4rO2Kkd5UqhAOmTITsmXV4nChr+JBMCu7DHY5XA+0AyqgtDtEyShPaLadw+Pdm/uTZrTNm4mHCukFy1M7CUHSaxfiqZupgKuRtiY1G2BPqrVoI1K6xSRHlLt48FJJA18ImLeAvq9/g5yZY/0HJZKA7c7z3v05OxC8cc4AgP1p9OpCug86mvEIIIoXFqVxMneNED2vZoPLaqcBhYVYUat8epaBZwXMwu166yufXgn8VHhtvPBORnWzqWKac8FPYBTX0NBsJMEeREF7+aL2baapYd/pfUoGNvaFSDhk+F3Z6UyCiOj3DbqBvHQA/wCMY8vkHFHCKH4gFA+12Br4LHMdJTa+s8RNZq5Z88QAPKqdoZxTTnNCsOaU2ALhlTahJ2aHC6YSsyogvP3IwDcJvsUgMnr36+BtnYEjNRjjEPmou3TxB8Javhe8g/uLjOxi2I+BP/OiM+kKt3pH5h8I2S9hkyeinE892UOr9aToGzJyCkkfhevsTIgKC6iSFnhkj9p5zASKCLowdmwA9vM8qFreqhoaOUenn6/ISKL0owSHOl8WUIdGdJM2OFXSr1GgntFMu6kDnPkp1I/ey0Cx+YK8yF+rTU54P838SbGHgxL+2KfPBRVlZxeIfDnahPuEfcptXuBZzU4PvBila1skhTr2cVT1ftEP9gUVVuA3mgM6w5XYGsw1sOM8LEZFA9AYUwIx1lzTBh9Nj0dHvz4m8s6vIpA3AizBh6/UE7fXEwV/yXMUyVcbar4t8EKf9dgEzakPKMUa+x6SnI88U/32jSvsuWxHTfxRGLqisY46AAK6wzEG0qU X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2024 02:00:16.2720 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 079b120a-6d8f-4b8e-0d3d-08dcb296dab6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B371.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9418 From: Kishon Vijay Abraham I AMD EPYC 5th generation processors have introduced a feature that allows the hypervisor to control the SEV_FEATURES that are set for or by a guest [1]. The ALLOWED_SEV_FEATURES feature can be used by the hypervisor to enforce that SEV-ES and SEV-SNP guests cannot enable features that the hypervisor does not want to be enabled. When ALLOWED_SEV_FEATURES is enabled, a VMRUN will fail if any non-reserved bits are 1 in SEV_FEATURES but are 0 in ALLOWED_SEV_FEATURES. [1] Section 15.36.20 "Allowed SEV Features", AMD64 Architecture Programmer's Manual, Pub. 24593 Rev. 3.42 - March 2024: https://bugzilla.kernel.org/attachment.cgi?id=306250 Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Kim Phillips Reviewed-by: Nikunj A. Dadhania --- arch/x86/include/asm/svm.h | 6 +++++- arch/x86/kvm/svm/sev.c | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index f0dea3750ca9..59516ad2028b 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -158,7 +158,9 @@ struct __attribute__ ((__packed__)) vmcb_control_area { u64 avic_physical_id; /* Offset 0xf8 */ u8 reserved_7[8]; u64 vmsa_pa; /* Used for an SEV-ES guest */ - u8 reserved_8[720]; + u8 reserved_8[40]; + u64 allowed_sev_features; /* Offset 0x138 */ + u8 reserved_9[672]; /* * Offset 0x3e0, 32 bytes reserved * for use by hypervisor/software. @@ -294,6 +296,8 @@ static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_ (SVM_SEV_FEAT_RESTRICTED_INJECTION | \ SVM_SEV_FEAT_ALTERNATE_INJECTION) +#define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) + struct vmcb_seg { u16 selector; u16 attrib; diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index a16c873b3232..d12b4d615b32 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -899,6 +899,7 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) static int __sev_launch_update_vmsa(struct kvm *kvm, struct kvm_vcpu *vcpu, int *error) { + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; struct sev_data_launch_update_vmsa vmsa; struct vcpu_svm *svm = to_svm(vcpu); int ret; @@ -908,6 +909,10 @@ static int __sev_launch_update_vmsa(struct kvm *kvm, struct kvm_vcpu *vcpu, return -EINVAL; } + if (cpu_feature_enabled(X86_FEATURE_ALLOWED_SEV_FEATURES)) + svm->vmcb->control.allowed_sev_features = VMCB_ALLOWED_SEV_FEATURES_VALID | + sev->vmsa_features; + /* Perform some pre-encryption checks against the VMSA */ ret = sev_es_sync_vmsa(svm); if (ret)