From patchwork Fri Aug 2 21:27:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 13752008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD9F3C3DA4A for ; Fri, 2 Aug 2024 21:27:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Bjd2Z3JManhntUqc1Oo4FhLNvn0xZqe3OfAIMPEAOhI=; b=ikfjAdy5nuhZZpRw/+crXHiU5j 1YcATTCAOkKL5uAjJBosTiPTcOOseE2Azzp1BcwAyIcRzzSUa0iMMaiMqoOeh/kD2ocXyVR6lMIDx yu/SXttWLJNlyeHSPtm4lQE8RW8Mhek0u2tabbceJmFiTSkPJKKp2t+XkwgJm8CRo8ToWVt4lAlB9 IbvXZdK41MeCYiyrK/97zN+9Rb48WNnaWm7lOKyn59g1eqnochQt+EEWbgRr+5UEhhG3w3Tp32aI9 GWul2qh8pOt74U9gXsd57ZhhTQmD1jKUbdjnbLEgm/CXEu1fHCOQmf/WN5ZyiEzr60djBfvQc5y0w /9MC6C8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZzoG-0000000A76f-0eqy; Fri, 02 Aug 2024 21:27:36 +0000 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZznk-0000000A71W-2xsZ for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 21:27:06 +0000 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-7ae3d7222d4so4961954a12.3 for ; Fri, 02 Aug 2024 14:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722634024; x=1723238824; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Bjd2Z3JManhntUqc1Oo4FhLNvn0xZqe3OfAIMPEAOhI=; b=r3tJbiw5+6H5aw0799xcpAnxepnoPrSyLkwKTq21ImWK/D4HCiN+xV/aIQCDj53q+m M90+69C0iPAqPuqn6p1aL6/y2mNIyOCH1pp3Cvw9PoU45QA038yHSOK9dmLW9Ied/+Zv zmLPi7TqXwmr2AkOah/8WVPwfAFWoR/GYk6F66JScSTWgukmjj5TJez48gJCTCs3r5eD G7b/okSfKt3yE6ZDAM4QEQJZx0riLBVrjH9pxLx5Rxd3QMEWzC1iTIIkkGapEId9QTC2 XQqT3UMjH3BogdN+QqUaPsiKUE8QXVzH5I6wVDhR/mCZcpsy4gsr0Q4SX+6o9b8slUkh ex7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722634024; x=1723238824; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Bjd2Z3JManhntUqc1Oo4FhLNvn0xZqe3OfAIMPEAOhI=; b=X+7dpLkzGNOgDm7TZkHm9afdmPT4v9BuWy58ryhOdSjonEHP1xrTo9y2g60aJZgXk8 +DcVKvP7DNwuvL+r7fLSMHO87kkUzZw3pICs1Xziv1tdGu6GUPzavt0+pYJRQG0sdLwx 6KmrvJdx3pCAEwCs44eBIAR+2OuCr5sm2T5HeDZ9mrslUtr7s/Pwi/genV8xcLJNoy5r fyP0XyjM0xAUeBzWcvqawfYYhnHq2+7Ff/yFoOi/thDpCct9HXp7OLQwj2f6XMGNl+XL NZhTtcfFh7Jx4Mc5G3aa4/sVmU7KM0Y/ks3aLgaYhdfv4quuKV8X4MUIai9pKBjDcxEh biuA== X-Gm-Message-State: AOJu0YzPzpuKW05CSt0UUqOfmJQFrmbaRURqiOOjvMf2B9WZT9UgkMSw BRsGooex8AcrSgwokHD5P6uFVv/U2q7/M54Jz8h51Oc5g9ibpFg0ebUgHu8ANjY= X-Google-Smtp-Source: AGHT+IGNN0qRhHKclgcVNV7yOORGn4jJKrOIgaiVYQTCSA/yBx4CoN2NULxXVWodrCnPR87v8AcTTA== X-Received: by 2002:a05:6a21:99aa:b0:1c1:31d0:c7a7 with SMTP id adf61e73a8af0-1c699580b18mr5852797637.16.1722634023687; Fri, 02 Aug 2024 14:27:03 -0700 (PDT) Received: from localhost ([71.212.170.185]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7106ec5878asm1751640b3a.76.2024.08.02.14.27.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Aug 2024 14:27:03 -0700 (PDT) From: Kevin Hilman To: Nishanth Menon , Tero Kristo , Santosh Shilimkar Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Akashdeep Kaur , Markus Schneider-Pargmann , Vibhore Vardhan , Dhruva Gole Subject: [PATCH v2] firmware: ti_sci: add CPU latency constraint management Date: Fri, 2 Aug 2024 14:27:02 -0700 Message-ID: <20240802212702.3424132-1-khilman@baylibre.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_142704_767190_FEE3E271 X-CRM114-Status: GOOD ( 15.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org During system-wide suspend, check if any of the CPUs have PM QoS resume latency constraints set. If so, set TI SCI constraint. TI SCI has a single system-wide latency constraint, so use the max of any of the CPU latencies as the system-wide value. Note: DM firmware clears all constraints at resume time, so constraints need to be checked/updated/sent at each system suspend. Co-developed-by: Vibhore Vardhan Signed-off-by: Vibhore Vardhan Signed-off-by: Kevin Hilman Reviewed-by: Dhruva Gole Signed-off-by: Dhruva Gole --- Depends on the TI SCI series where support for the constraints APIs are added: https://lore.kernel.org/r/20240801195422.2296347-1-msp@baylibre.com v1->v2: fixed silly compile error drivers/firmware/ti_sci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index c6544cc12417..a141e07e7864 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "%s: " fmt, __func__ #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -3640,8 +3642,26 @@ static int ti_sci_prepare_system_suspend(struct ti_sci_info *info) static int ti_sci_suspend(struct device *dev) { struct ti_sci_info *info = dev_get_drvdata(dev); + struct device *cpu_dev; + s32 val, cpu_lat = 0; int ret; + if (info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED) { + for_each_possible_cpu(i) { + cpu_dev = get_cpu_device(i); + val = dev_pm_qos_read_value(cpu_dev, DEV_PM_QOS_RESUME_LATENCY); + if (val != PM_QOS_RESUME_LATENCY_NO_CONSTRAINT) + cpu_lat = max(cpu_lat, val); + } + if (cpu_lat && (cpu_lat != PM_QOS_RESUME_LATENCY_NO_CONSTRAINT)) { + dev_dbg(cpu_dev, "%s: sending max CPU latency=%u\n", __func__, cpu_lat); + ret = ti_sci_cmd_set_latency_constraint(&info->handle, + cpu_lat, TISCI_MSG_CONSTRAINT_SET); + if (ret) + return ret; + } + } + ret = ti_sci_prepare_system_suspend(info); if (ret) return ret;