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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net 1/5] net/mlx5: SD, Do not query MPIR register if no sd_group Date: Thu, 8 Aug 2024 17:41:02 +0300 Message-ID: <20240808144107.2095424-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240808144107.2095424-1-tariqt@nvidia.com> References: <20240808144107.2095424-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|PH8PR12MB7133:EE_ X-MS-Office365-Filtering-Correlation-Id: 43e61beb-b0d2-4c2b-41a8-08dcb7b8628c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: P4x4BDrl4TY+FLvU59OrgH4VC/KjmWv9ZjxzBTohdOcpDpDYuTutHnN0rCk2Qg6d+mUNSogVxABlIUqoxTK4ABQ/gZeoYO4GGC8PrdvQ5wsWX+440reB/ib+ypIDcPqbsqz/DZxaK154mGih/f7ZW3MXlJtNwsYLIhUbBhRw4+XU+3seiIaICX/oAKQk4mz6cEyd6lhVAUMY3lgTBnH3FkQN2zJbwlrKO6AgF718fVwoPC9EeyXQXsK4hGyyhs0B86F0DheqBentywTR7S1Ny/sEHm2qErLT1u611VxasDAcUa5xPFlcp8ltsKKGnWf8In6aYrnHa20o2LCsp8rV2Vv0DgbckCl2GpphO741sVZLXSb33LF7fzzj8lq3o1ZlZ5a20dssoG6SPnVN687so7e5GIabTn1S0nQ/JUTrtoJ0fIxRfkzx/pippzU7/jRfg1wXZxCBMLAJ0U0h9bMxzQh0x0kBnkzJnZda91JfiTT2mIP2zEKLj1Dv+u9tgjDQZXsMwLI2Ey/R86oY6JoC8jbVgQ+Vau5pmrm2vUJ16xGcpRlr+b5UrjTHYxK0wx8Y6q85p8jx6jBXBn02TXHP98qwYrhLcC2yEKg3ppTeetefiqnNXIhTM2+iTzQW6FLlp28xQgIl5CjKvtacstEyTtb9MZJqBh22gzP3vM8fRLKflQuON+UWV4zSm/MFhxKPptvaLQvrz9LXUwsHUfsM6MNwCBLEh0LAx7GHi1KSKuXUb0iBEm8XlryqbUJcvwC9eMqhmVLo6onaRL62HZTAgOAJm1rexmgq6oNb3JTGC9Pdtrx5MzY6SVJgVG6GiqGhq9FJyUqYaWd7g96f2lQ6sLYGFceMWTf+icCLiUgIkgufvwZJUv/6VE1P+xyEyFQQlAidhkdY/vQXQyT3hYYn5ghTGaiUZ0LKztdA0dpjiLZBFFGOLN7EXqxw4sR/vFWvkxhxmPMNc4t+qNjMRbR1jTYf6OTWLQM0zWGaovgeLnTZIDIOrNny3eAES24VQJwofWAXCHE5HI2X+DG6wXJGufm+Ntb7MMFbtJycknofRHDx54ZME0T4eEJIYq9+yjWppN/P4ZgNM76MROI2QOc3nsG13XXNo+lmhgLpnCjl1DMXIOYj16GiGldYKZEHfX2BPsZ8A/KF/kYjjqJ4xwT5Cbp0N6iq9ZbvhQnpAUNs+/uF0yUiT89GAL+v5owz3Qhp2VQno921asFtxUz71WM/NN9j8t3KNN5WzON4CtRTFfmcShmw+2RLZ4N1oSKaOGtiRgithXvnmNtN6AxSNaQPF21nswP4/8lIUjDHlxuudarmsOP7GxwrrTuivKRwnT3iZETOKxtSseoa6eyyJZFJ/+ltKhY1ZntSI3vjmYOUIdDQo6uE/h+TXQIomFc97UQ4A3e3vH/iU3VTvbjdmc3/QJH3gZW6/2ztvTRnGLcD3ZTqXsVlHmziCd9ZCbXopat6 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 14:42:53.3586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43e61beb-b0d2-4c2b-41a8-08dcb7b8628c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7133 X-Patchwork-Delegate: kuba@kernel.org Unconditionally calling the MPIR query on BF separate mode yields the FW syndrome below [1]. Do not call it unless admin clearly specified the SD group, i.e. expressing the intention of using the multi-PF netdev feature. This fix covers cases not covered in commit fca3b4791850 ("net/mlx5: Do not query MPIR on embedded CPU function"). [1] mlx5_cmd_out_err:808:(pid 8267): ACCESS_REG(0x805) op_mod(0x1) failed, status bad system state(0x4), syndrome (0x685f19), err(-5) Fixes: 678eb448055a ("net/mlx5: SD, Implement basic query and instantiation") Signed-off-by: Tariq Toukan Reviewed-by: Gal Pressman --- .../net/ethernet/mellanox/mlx5/core/lib/sd.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c index f6deb5a3f820..eeb0b7ea05f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -126,7 +126,7 @@ static bool mlx5_sd_is_supported(struct mlx5_core_dev *dev, u8 host_buses) } static int mlx5_query_sd(struct mlx5_core_dev *dev, bool *sdm, - u8 *host_buses, u8 *sd_group) + u8 *host_buses) { u32 out[MLX5_ST_SZ_DW(mpir_reg)]; int err; @@ -135,10 +135,6 @@ static int mlx5_query_sd(struct mlx5_core_dev *dev, bool *sdm, if (err) return err; - err = mlx5_query_nic_vport_sd_group(dev, sd_group); - if (err) - return err; - *sdm = MLX5_GET(mpir_reg, out, sdm); *host_buses = MLX5_GET(mpir_reg, out, host_buses); @@ -166,19 +162,23 @@ static int sd_init(struct mlx5_core_dev *dev) if (mlx5_core_is_ecpf(dev)) return 0; + err = mlx5_query_nic_vport_sd_group(dev, &sd_group); + if (err) + return err; + + if (!sd_group) + return 0; + if (!MLX5_CAP_MCAM_REG(dev, mpir)) return 0; - err = mlx5_query_sd(dev, &sdm, &host_buses, &sd_group); + err = mlx5_query_sd(dev, &sdm, &host_buses); if (err) return err; if (!sdm) return 0; - if (!sd_group) - return 0; - group_id = mlx5_sd_group_id(dev, sd_group); if (!mlx5_sd_is_supported(dev, host_buses)) { From patchwork Thu Aug 8 14:41:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13757663 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2087.outbound.protection.outlook.com [40.107.94.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C1F19408B for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 2/5] net/mlx5e: SHAMPO, Increase timeout to improve latency Date: Thu, 8 Aug 2024 17:41:03 +0300 Message-ID: <20240808144107.2095424-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240808144107.2095424-1-tariqt@nvidia.com> References: <20240808144107.2095424-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|MW4PR12MB7165:EE_ X-MS-Office365-Filtering-Correlation-Id: d3b8716a-405f-45bd-e663-08dcb7b86563 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: s8mza7akTtJQAHCdPgZBsRgO/g9pAhZwzZ0+zYg01F4XTW2O6hGwUMmnYpuaEGek0iA42OjDx/eXFR4HeFYTDZ1wFj6kE/QP5/d/Q1/hNp491v65t+YEtHOl9xkGv0kF33Q4Mf/GiXIoGLqjmpm/JvAKcTMEfWzZ38uqWgmbWfsBA121tFCJfcdIz4Bozzt++1Kger6MxUuPgc2BixNRa3mvcLqbc4sDL8h2THCgUwZnE61ixYpHo7QBQvUsSjgPmkkES4w+hAlK3gVtgzvsYYMIF3IGO/LqNjpvjE5cJYcMyF0BrgAgvUdg4gZokDDsrdNukOs7HyFbHD9B+Tqg4hWWWGllC9/+Lu5peZH2as0W4J3F0dMRV/E/+M9sBPkGamduPdutkKl10u75zAK9yXiKVUUkE89/X8BfL2eyL6/20WrWcBbL9eohxcLT+haPYSj/1AG7PLYIcII42L8yWqHYXy0BgK+Za+Fp6ACDsJGQcvzKzTKCSHCcOb9Sb9zyCp0L+Lwsb7awlOQHBYwIA5L9668ZFuMikRm0hkT9Mp+jKC8lccCaZNp3rbbQgaJtDjTHEawd9nrnSNZwgk6VdQBtOnSpVGQooCz0yXm5z76MCSkVKm+6v3leoDX5CLVwXCL2Nk1AGQVUcht99/lX2NcVdFsF5CvQm71aOWwYYbDT5l80Hr9lDPo0XH57qCnpozTuaicYGGpGd5OtVvVcwIAFyMFaOtf1pCzLZMEKKA9OvVw3OnYC9GB7KRvOnfMY+nBwTAsQcCQg17S468HNGGTxlL14jeY7QUo9XLtriTbZIzxt2xyTkZn7VzwlX9gwaQWURqzCUWJfci4I/E8X1fxhRQ0YOch64S2uQxylvv8dwldVJI2V4WvRgdHthKI+4CqwdQY4at+SGjvlbhCgGONlc6XZa5j6Y2gG/1i2uQXhkUon58egaNr/ObjIjoyqY+syBKUXdxTE77KJfDmcXfvnUENbZ64E4TWjVQbAZmY6vQiciM/M+LmVgXBeiX4S/RflGuIUMtUDUwfKxONrcvwYSiYHUQ1JPIBfBnAndKbpRwx8lO1cNths8iKk8+04NrIYro1fbvF94TXm7zHgxY37BO4gx0KWbCpXAgo/9sB17Yt2wJcWRRBWL/k4PQ12jshDx5L3vGYwM8GztRQnU7Sk7J2MpEzADpLs/Q9YvDQehjVPq6B03ffgwpSSuDvFYAOM3T++DlpGWWq+nmjiiDF5OTp0yxSaxuWNIE9e7/jYCn6HmrtkbxUQRyZEUs6XNUo/JLjBLV1A4OL7GINR9CyQiue4g42yhbyd8j3XKi9lPpM0oSkQmHL65VAQ/GaL//psGz7dpCvxJezXtWhY1FwfPjo0l9d5Z7BHW1PTSJFlFEWRrA6mu01M6rUaTcR81W+F9inIgmZ4J7BduTIeXlWtMSRHUl+YiHFxX73zPS1q07GAEUEAHgkb9UgyBelH X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 14:42:58.1116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d3b8716a-405f-45bd-e663-08dcb7b86563 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7165 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea During latency tests (netperf TCP_RR) a 30% degradation of HW GRO vs SW GRO was observed. This is due to SHAMPO triggering timeout filler CQEs instead of delivering the CQE for the packet. Having a short timeout for SHAMPO doesn't bring any benefits as it is the driver that does the merging, not the hardware. On the contrary, it can have a negative impact: additional filler CQEs are generated due to the timeout. As there is no way to disable this timeout, this change sets it to the maximum value. Instead of using the packet_merge.timeout parameter which is also used for LRO, set the value directly when filling in the rest of the SHAMPO parameters in mlx5e_build_rq_param(). Fixes: 99be56171fa9 ("net/mlx5e: SHAMPO, Re-enable HW-GRO") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en/params.c | 16 +++++++++++++++- .../net/ethernet/mellanox/mlx5/core/en/params.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 12 ------------ 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index 5fd82c67b6ab..bb5da42edc23 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -130,7 +130,7 @@ struct page_pool; #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 -#define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 +#define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index 6c9ccccca81e..64b62ed17b07 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -928,7 +928,7 @@ int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, MLX5_SET(wq, wq, log_headers_entry_size, mlx5e_shampo_get_log_hd_entry_size(mdev, params)); MLX5_SET(rqc, rqc, reservation_timeout, - params->packet_merge.timeout); + mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_SHAMPO_TIMEOUT)); MLX5_SET(rqc, rqc, shampo_match_criteria_type, params->packet_merge.shampo.match_criteria_type); MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, @@ -1087,6 +1087,20 @@ static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev, return wqebbs; } +#define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 + +u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) +{ + int i; + + /* The supported periods are organized in ascending order */ + for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) + if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) + break; + + return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); +} + static u32 mlx5e_mpwrq_total_umr_wqebbs(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h index 749b2ec0436e..3f8986f9d862 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.h @@ -108,6 +108,7 @@ u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_rq_param *rq_param); +u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, struct mlx5e_params *params, struct mlx5e_xsk_param *xsk); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 6f686fabed44..f04decca39f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5167,18 +5167,6 @@ const struct net_device_ops mlx5e_netdev_ops = { #endif }; -static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) -{ - int i; - - /* The supported periods are organized in ascending order */ - for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) - if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) - break; - - return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); -} - void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) { struct mlx5e_params *params = &priv->channels.params; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Breno Leitao , Moshe Shemesh , Tariq Toukan Subject: [PATCH net 3/5] net/mlx5e: Take state lock during tx timeout reporter Date: Thu, 8 Aug 2024 17:41:04 +0300 Message-ID: <20240808144107.2095424-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240808144107.2095424-1-tariqt@nvidia.com> References: <20240808144107.2095424-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|MN2PR12MB4375:EE_ X-MS-Office365-Filtering-Correlation-Id: 95dda196-1483-4304-bc8e-08dcb7b8675f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 0yB3xuxKYfJ/3ufJgXYtTjxvlda/uaVNnep9JRzgSvGq/A0Yt63d3yP2C/HefsT/g1Mv1PIadj6iH2+xeeMIJmrT16RtSL0XOIyFNIjpIAfknzcDlPlC3VJ/LnKLlNSQ9jiIBuznw31g4B1uNH7btY1ab67OSL/+7UDwDrg0v7VJ/jsW38dO8XtblIrliV8f+ZZUskh9TCuMcKyHydIJOvKlVSGmYUCvGeZUWXtojJ06XlBW5J8IjMhPTS6Wv4d/+U8Nud5QS96eYi1e69cHrsRujyGxe2R4b+f1R20BPTaDQ55XRYSmbrroTIEFANutjkcgY9+XR6DtMuTXTX4VFgJJPN8jhI7CHDpqG8wQWkfc0WNC8HW1OVXm9EkIjOcdTmCqx9e7iJpdRs/9EJSZczsHTG2+5H6BwLKAGceMf6D7c2yuM8JQDNCBZPqmt6Bh1hqbXWeXG4oz9iXqa4OcEC8NgMfBDbVIVdpO/b7CXOXckHbv0aqfGv0cRM1qATbb/BgBhr/3LyI/D39zqD58fTKXn+ZQKa0Dvz+sue+KQt3iOeOtgfeLpYajFEHX6SWt3XUrEEZny3oCo7eiLOyLXr+HWiMkts6Oa42LqVt5kAcRhyUQiog/JeY/HCCO1nPTkPoKS+b5GqKU2M/3teO4jNWusVKVbmWsIlWznA08JXtaFQ2gfIE9FmPWln+ei02M+1yiQElAbWWSwiF+thLlLohpLkacP9kaSYLHzITCbHK1wJccj3tbbxJZxR/LEepPIRKIGt0Q5rtGaJSP/AfjCx/sVA47uI1Lb8N9v/JtfQujYgC0xQ5J+wJtTYDbiayJUnOaGvyQTPg3JYZT69MoD6BLNUD5DgfPlCXm7dVNSqnxvBNeoTxEAjzDyD3f7LUEuNDiNV2NhBxgByLd62P678DcmT/xd/gL+knJTV69rwKosdgtjKUS8jDPaocD/CKrTWgg2wUUVvcy9ISMuNcYfbxC4PJO0OS7S6r99GrAPWvqNWNS00xxHg3hOlrjlfiErLEvUzSjqePIGAeUdCZoAAHr5As4ngVdD50SwgIL3Oi73AoIlms/cKWN6WobmLp+etv/Y3xwLTWNcVrETMd6A0qaijrvJGwVV/SB3T7is2rCBLv1Ebe7hqgiO/l2wpnsZVRTmUWVzqta9xWKERcreZzHSWOpdzJcHSP8Od264Nt3Xb4PC5R+aSo5JGUtJW5TOVujw/mLsJw6mnHPXPGBQMK95ZVdXl2SWeZuLv4ZLYuKUxSWmbzLqT8FOytz7V5JaMZvUUyq3DshMimAYL6RUcVNIjh3Cv+zLhG7QFWOV2bDx74vcluEBCehA+MXd95ZDh9AXt3w2TO5VPxVR7xUB0SHara6oSkkj+JHcSjV2Hyg0sr0SPcJcqoz2J4+ea5Rvs6jPp8Cjl790RtcQeo7tdCdosPfG2hLo/G/4f/N9nUTudihEB6OB7MHV42PBDyX X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 14:43:01.4241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95dda196-1483-4304-bc8e-08dcb7b8675f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4375 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea mlx5e_safe_reopen_channels() requires the state lock taken. The referenced changed in the Fixes tag removed the lock to fix another issue. This patch adds it back but at a later point (when calling mlx5e_safe_reopen_channels()) to avoid the deadlock referenced in the Fixes tag. Fixes: eab0da38912e ("net/mlx5e: Fix possible deadlock on mlx5e_tx_timeout_work") Signed-off-by: Dragos Tatulea Link: https://lore.kernel.org/all/ZplpKq8FKi3vwfxv@gmail.com/T/ Reviewed-by: Breno Leitao Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index 22918b2ef7f1..09433b91be17 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -146,7 +146,9 @@ static int mlx5e_tx_reporter_timeout_recover(void *ctx) return err; } + mutex_lock(&priv->state_lock); err = mlx5e_safe_reopen_channels(priv); + mutex_unlock(&priv->state_lock); if (!err) { to_ctx->status = 1; /* all channels recovered */ return err; From patchwork Thu Aug 8 14:41:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13757664 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2082.outbound.protection.outlook.com [40.107.100.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80A23194C93 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 4/5] net/mlx5e: Correctly report errors for ethtool rx flows Date: Thu, 8 Aug 2024 17:41:05 +0300 Message-ID: <20240808144107.2095424-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240808144107.2095424-1-tariqt@nvidia.com> References: <20240808144107.2095424-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|MW4PR12MB6706:EE_ X-MS-Office365-Filtering-Correlation-Id: e96054b1-1069-4125-791d-08dcb7b86862 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: J4VJc/t+fkbn9ZnXGElnK7DGaEYUay1gCG0+/3Aqz51+XAkMByGdtSng5lWamB24qcRCVMuuKW6SKGLBdS02oG9EUNqOqqw2p1c7jM9flEcbbXCvs8MBLyRV5V6/Oj0m/vv5XWiidQQ7WQo3Q+4ujFOit5aD78CkjOo4SWQSL2cAYZFS18VTLrtOWKIcmOlS2S6Tb8JT321ELHstRFlob1yUgNQlbPhk8/ptHCidgaMYXm0WvAg/NOuc0tqzUlyuOtaD59O3PzgyBQCjvV8G74e4IwJ/aNTxt8TkOFMGo0jrL1E4uDezqy7i01GSBsPnIufNdlXZOoiHDOOH9h2CFSFe22viYsHjdcSNpG/T0u81WMqwBLwOUFCwL2PCATIoTHVgIOgvcq700YPSdnWguMk8Cf7bkK/DHVGTopylLNu5EurHNLrSi5yrn/RDCioMu/UANCLD65fn1BwJQ2HKUfI7WLLhepQkT4CCfYtgkABAKbK+7+ucHPXLZJAd28U/Ch+RCfLg47D+NRezUg90l+9L9WdY1S7svoe4x77G26ak8F4bMpY5c+4yp7jFfi7SgE18XgZjhLZdf4HhxI3vnbuvqTAUaLupLvjSG4Ag/SmndXZmDdFGNWrwdmW7BQ3xLoxCVjGlp3+cASuujOwPrJpg+UPe0ne36mPlQZeNhBfV+3MrehRCMSZa0yIWxkR1ROBfUe0NugNZIeOQMKh5DSZqSXsrIALoMmqO03Ucv4D8yjw8jSrqLdU1wXM5ChYG6n0tiYnxQvL+AcjH4iwGi/vUwYtHgTK4GsQ24/Mbi5J3v9/eNxOrfWC/bGygFiYOuSVki53tSJ0GKI71IXbdm1t854C5qt7lCu2gIWsrfS5EQpa69Elx7Gb3XVdvB/3SAFKbpqgKp2tXgx8bNlFIiQi0KiC1jxtDxxH3u3NF7LmM8GhgGJLLdTSoRkE6B/rREhfi3D1+E1yXGIu+RwlAFrukF53qQMqlPrVYa6UgLgHxSFFGa/SC9LDZbPYkUL8EMZr55YPUK6Rj8Pp0jwZTUiOEvTssPjvsn8rfTc0+zKSd5YuIHXgg3uWK8FjtjE08lSJxc7T5oZboqGvR1r0/ONm4bxw3lL6ZoZadQKXbYnw27jCY62xEfbk9vsnnbVKXhhU7ZveFEPO1P9/scfnAL2OHDlwEAUZsNTqqDCR2TkA/ZIpviYPSzxEHuaf416ZV7aKqUoEbS7ccD0zwsoSVN/7LRTsCBgmoMVgVPN84h30Be0PF46uR+QfOrORHsW/YVaAhwhZ2PTmV9hP6YbAqsggl5HMXPF/xJRN5SAyzerIB260yUGI43A7GTZXceSXMviMlYQXo5Fmx6wKVgt69WHreutCNgCdmhqVhDA1CUUb7RgPQVhpiI5sWIxCiU29G5tvXraSeANIiGYuNMcvP6XKI8sW6wmD087a1X/BaGN/R+4FcJqIBJBGFagy2I9vA X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 14:43:03.0886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e96054b1-1069-4125-791d-08dcb7b86862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6706 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu Previously, an ethtool rx flow with no attrs would not be added to the NIC as it has no rules to configure the hw with, but it would be reported as successful to the caller (return code 0). This is confusing for the user as ethtool then reports "Added rule $num", but no rule was actually added. This change corrects that by instead reporting these wrong rules as -EINVAL. Fixes: b29c61dac3a2 ("net/mlx5e: Ethtool steering flow validation refactoring") Signed-off-by: Cosmin Ratiu Reviewed-by: Saeed Mahameed Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c index 3eccdadc0357..773624bb2c5d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c @@ -734,7 +734,7 @@ mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, if (num_tuples <= 0) { netdev_warn(priv->netdev, "%s: flow is not valid %d\n", __func__, num_tuples); - return num_tuples; + return num_tuples < 0 ? num_tuples : -EINVAL; } eth_ft = get_flow_table(priv, fs, num_tuples); From patchwork Thu Aug 8 14:41:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13757665 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2081.outbound.protection.outlook.com [40.107.212.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65888190477 for ; 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Thu, 8 Aug 2024 07:42:55 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 8 Aug 2024 07:42:55 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 8 Aug 2024 07:42:52 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Joe Damato , Tariq Toukan Subject: [PATCH net 5/5] net/mlx5e: Fix queue stats access to non-existing channels splat Date: Thu, 8 Aug 2024 17:41:06 +0300 Message-ID: <20240808144107.2095424-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240808144107.2095424-1-tariqt@nvidia.com> References: <20240808144107.2095424-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009D:EE_|SA1PR12MB7224:EE_ X-MS-Office365-Filtering-Correlation-Id: 1db62fc2-5529-4df1-1f55-08dcb7b8694c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 8YiIPvoek5ZF3nJvc5vLTmhNRyHYwEsfHPAkaxOJc4ffkAmWgF+2hucFEdrr6xsVsInzrz1sHDLYFEkPhM3Mu+j6YwCpE9aRb0WUCeRYn0DvcEDl5bhqodEBoIaYK9AzboJpkIXbSPY8RvChhWqdL5ovAgu7X07ljNCW4Lt/c3yYNrVKp01zRLJ/OF0AJeavX/LMPuPHjtP9gHEFzrSe4JsT2yxQHguB+0jtVeuzp8BPtQWUNLpnryQ7HqHfOBUoBCWZ6hK0V0E8RFrVIgoTn6etMLjoMTn7yFqq+7SUWv+28oo/7lXGM/UOY8lxPJcHqst9zdElDUF4GALNU0Oa0doEYWf0ZEQfuq5b4vaawE7z1OsP2+u4mp5ypOeRFHUgi2U6xjZSydL7Imb4qDqRI884JLg8mLuI9sIkBScUXAKEVkchvplIGwwjCcD6NgrT2jg0zl6k9eSUdrJ0N/1I6yQXLKt9D4pMhPxaYaKK8mZHGPEueUQKp83OQ843sa+Lhhl31LCgGWo7qEIF8/0yIsl4U0XhSNOzpdpWv1gfAwwR8QX5O/ued6UcqZgw43hD/xzGez97j7fcy1D2q7h3wVZnTpvgeuOdpOooT70nFhiekR/k5cjTyazo1GpUtTEKNRSR4QbFAJYT1l23nuf8zlKOz3LBWZfbeWc2Xe+ymERw1aDjXkOmr++P+EgJnUC27gIv4z+5LSIiDb1yhPwVYRy5HD/dOAhlE62JWKve9uUAeeiVoI9fca3/31zB5qJ8fkh4RCRGguGqFK8vYi2PSfKGFJ559RcSW2V2zqTx4mY7jRQxkSf9dDzk1+2B8lYtYvhcd6KlthDGAo9nRiNidB0kA/tR4/+URZ8qhl3DiYH23cLO/X8nfanjiHmiLgAYqhXx7qD3vdsc3zUVwFOlyF8LaUpIrrwoTCFqiojHzG76q9stmZso6aBd1JddqJQbGaTypTdXpzAU4680noznDkbezL0kbXiTmvjrMlWOSLjo6K9d8gTA3H8PvrIA88cbevEsjo2CRt3Ny6WhJP/hB4aNg1w5WGX+sM2aaY5BM9yVMestl4/pph8GOKlS8bl83NvameHZCHEjug/2SYh1pSv+H2e2milKdwxuei00sQgXSNuUI/7t/91WnZkNNZ0QRy6EWwjR9fsA+nwlZ8WmiqMnl4Ku+y5bPoQH+8aiPWgCouJixTn1yespS7yAq3Xgt0WanknFV6ySigVxgYiohQdpkS15YhMmCHCEgHMECezN3NY3G3F+KSnbGZ03YBh2QlnJmEEarRL/VgQUrl6qD0cYdOtWtqXkDECr+rQOv7bYxN1Xx7eSCjOCKn8SAcBVXXIO89LL3Xj1SWx/8cf815KVBel893lEOUuVAZ7GoFBMctYzS16r0FCkOXIAwwqKHy7qIk9N0NHdZJYtKAJvo/PFf90VFJ0HV4yk/XpzJ7SM6i4q2S1GNpP27qiVU+XM X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2024 14:43:04.6979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1db62fc2-5529-4df1-1f55-08dcb7b8694c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7224 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman The queue stats API queries the queues according to the real_num_[tr]x_queues, in case the device is down and channels were not yet created, don't try to query their statistics. To trigger the panic, run this command before the interface is brought up: ./cli.py --spec ../../../Documentation/netlink/specs/netdev.yaml --dump qstats-get --json '{"ifindex": 4}' BUG: kernel NULL pointer dereference, address: 0000000000000c00 PGD 0 P4D 0 Oops: Oops: 0000 [#1] SMP PTI CPU: 3 UID: 0 PID: 977 Comm: python3 Not tainted 6.10.0+ #40 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014 RIP: 0010:mlx5e_get_queue_stats_rx+0x3c/0xb0 [mlx5_core] Code: fc 55 48 63 ee 53 48 89 d3 e8 40 3d 70 e1 85 c0 74 58 4c 89 ef e8 d4 07 04 00 84 c0 75 41 49 8b 84 24 f8 39 00 00 48 8b 04 e8 <48> 8b 90 00 0c 00 00 48 03 90 40 0a 00 00 48 89 53 08 48 8b 90 08 RSP: 0018:ffff888116be37d0 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff888116be3868 RCX: 0000000000000004 RDX: ffff88810ada4000 RSI: 0000000000000000 RDI: ffff888109df09c0 RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000004 R10: ffff88813461901c R11: ffffffffffffffff R12: ffff888109df0000 R13: ffff888109df09c0 R14: ffff888116be38d0 R15: 0000000000000000 FS: 00007f4375d5c740(0000) GS:ffff88852c980000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000c00 CR3: 0000000106ada006 CR4: 0000000000370eb0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: ? __die+0x1f/0x60 ? page_fault_oops+0x14e/0x3d0 ? exc_page_fault+0x73/0x130 ? asm_exc_page_fault+0x22/0x30 ? mlx5e_get_queue_stats_rx+0x3c/0xb0 [mlx5_core] netdev_nl_stats_by_netdev+0x2a6/0x4c0 ? __rmqueue_pcplist+0x351/0x6f0 netdev_nl_qstats_get_dumpit+0xc4/0x1b0 genl_dumpit+0x2d/0x80 netlink_dump+0x199/0x410 __netlink_dump_start+0x1aa/0x2c0 genl_family_rcv_msg_dumpit+0x94/0xf0 ? __pfx_genl_start+0x10/0x10 ? __pfx_genl_dumpit+0x10/0x10 ? __pfx_genl_done+0x10/0x10 genl_rcv_msg+0x116/0x2b0 ? __pfx_netdev_nl_qstats_get_dumpit+0x10/0x10 ? __pfx_genl_rcv_msg+0x10/0x10 netlink_rcv_skb+0x54/0x100 genl_rcv+0x24/0x40 netlink_unicast+0x21a/0x340 netlink_sendmsg+0x1f4/0x440 __sys_sendto+0x1b6/0x1c0 ? do_sock_setsockopt+0xc3/0x180 ? __sys_setsockopt+0x60/0xb0 __x64_sys_sendto+0x20/0x30 do_syscall_64+0x50/0x110 entry_SYSCALL_64_after_hwframe+0x76/0x7e RIP: 0033:0x7f43757132b0 Code: c0 ff ff ff ff eb b8 0f 1f 00 f3 0f 1e fa 41 89 ca 64 8b 04 25 18 00 00 00 85 c0 75 1d 45 31 c9 45 31 c0 b8 2c 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 68 c3 0f 1f 80 00 00 00 00 41 54 48 83 ec 20 RSP: 002b:00007ffd258da048 EFLAGS: 00000246 ORIG_RAX: 000000000000002c RAX: ffffffffffffffda RBX: 00007ffd258da0f8 RCX: 00007f43757132b0 RDX: 000000000000001c RSI: 00007f437464b850 RDI: 0000000000000003 RBP: 00007f4375085de0 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: ffffffffc4653600 R14: 0000000000000001 R15: 00007f43751a6147 Modules linked in: netconsole xt_conntrack xt_MASQUERADE nf_conntrack_netlink nfnetlink xt_addrtype iptable_nat nf_nat br_netfilter rpcsec_gss_krb5 auth_rpcgss oid_registry overlay rpcrdma rdma_ucm ib_iser libiscsi scsi_transport_iscsi ib_umad rdma_cm ib_ipoib iw_cm ib_cm mlx5_ib ib_uverbs ib_core zram zsmalloc mlx5_core fuse [last unloaded: netconsole] CR2: 0000000000000c00 ---[ end trace 0000000000000000 ]--- RIP: 0010:mlx5e_get_queue_stats_rx+0x3c/0xb0 [mlx5_core] Code: fc 55 48 63 ee 53 48 89 d3 e8 40 3d 70 e1 85 c0 74 58 4c 89 ef e8 d4 07 04 00 84 c0 75 41 49 8b 84 24 f8 39 00 00 48 8b 04 e8 <48> 8b 90 00 0c 00 00 48 03 90 40 0a 00 00 48 89 53 08 48 8b 90 08 RSP: 0018:ffff888116be37d0 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff888116be3868 RCX: 0000000000000004 RDX: ffff88810ada4000 RSI: 0000000000000000 RDI: ffff888109df09c0 RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000004 R10: ffff88813461901c R11: ffffffffffffffff R12: ffff888109df0000 R13: ffff888109df09c0 R14: ffff888116be38d0 R15: 0000000000000000 FS: 00007f4375d5c740(0000) GS:ffff88852c980000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000c00 CR3: 0000000106ada006 CR4: 0000000000370eb0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Fixes: 7b66ae536a78 ("net/mlx5e: Add per queue netdev-genl stats") Cc: Joe Damato Signed-off-by: Gal Pressman Signed-off-by: Tariq Toukan Reviewed-by: Joe Damato --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index f04decca39f2..5df904639b0c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -5296,7 +5296,7 @@ static void mlx5e_get_queue_stats_rx(struct net_device *dev, int i, struct mlx5e_rq_stats *rq_stats; ASSERT_RTNL(); - if (mlx5e_is_uplink_rep(priv)) + if (mlx5e_is_uplink_rep(priv) || !priv->stats_nch) return; channel_stats = priv->channel_stats[i]; @@ -5316,6 +5316,9 @@ static void mlx5e_get_queue_stats_tx(struct net_device *dev, int i, struct mlx5e_sq_stats *sq_stats; ASSERT_RTNL(); + if (!priv->stats_nch) + return; + /* no special case needed for ptp htb etc since txq2sq_stats is kept up * to date for active sq_stats, otherwise get_base_stats takes care of * inactive sqs.