From patchwork Tue Aug 13 11:05:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanfei Xu X-Patchwork-Id: 13761816 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8917E60EC4 for ; Tue, 13 Aug 2024 11:13:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723547588; cv=none; b=e8+WrK6ub026WrAfQ9P3eohqq3vRyPovNFRlmY//dl5pMyQDV3PyV+wDIByAiK5alJiu96tPXRDuTTVkE6jdi4FvyH5GqXmPQ6/OdzPYBTzMC8SWeD6Eny193xgrW+Kv+BH9CTn1Nr2E8DahLuQUbr9EExtuStsPnTbuKR0wggw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723547588; c=relaxed/simple; bh=gZwhe97f+wILNfWjc23vBK22qTvjp4eHrxhYf9C7Gj8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p78NgkxNr6z8Un7laTnSKG4C4jWAPvYMC4HVCDcpiFAziluZUO2s1R/qwKD4A4ZfsohhfKPexP1zjfylFBTvDbfnMXf8q6o8+C7YZDqZQXETwHvl4i/Rsc/vVU81FdePRFUj80yELOeov4rtoCgZcl3CaXqXa3VoXmBnM4n8tek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FF/DGmb1; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FF/DGmb1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723547586; x=1755083586; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gZwhe97f+wILNfWjc23vBK22qTvjp4eHrxhYf9C7Gj8=; b=FF/DGmb1J1YwOcxcRPT6v252YoTzxtl44ymgmYj5NMWCukXxXiczDdUR MwZY10qgi1c6k15RV+jAKzTQhGL4QTBPagt15aXfktKcZLiF/T3Q5Den7 vS4G7M517pB1pjWqvfSDFvx2F/MO09TygQkQk08hR1i08lkIwAMzLKiJh uHGpJTEw/5DcTibT6QWO9xn4Mf+/E6tZExiV40BHQ+yYZitL2Mr0nkmMo 3VlwAsKXoIg3e7oISgFaREuQZmPabb/SytIuk+oXiNrTgB9Slsci77Rmn LY+Zi0yjSznM8SjFHJaMn/FAIVqRCNvvkKtbVPMQrIDyq3TVKpWuwXCWw w==; X-CSE-ConnectionGUID: iYbGQHkIQJiBAbzUeEmfkQ== X-CSE-MsgGUID: Jec62hZ/RQyTlT1n7C8B+g== X-IronPort-AV: E=McAfee;i="6700,10204,11162"; a="21262277" X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="21262277" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:06 -0700 X-CSE-ConnectionGUID: NNgYINwTQWuEMf0DlnorpA== X-CSE-MsgGUID: mQ63OAixSz2oPScArVQ5JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="58568752" Received: from tower.bj.intel.com ([10.238.157.70]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:04 -0700 From: Yanfei Xu To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, ming4.li@intel.com, yanfei.xu@intel.com Subject: [v3 1/4] cxl/pci: Fix to record only non-zero ranges Date: Tue, 13 Aug 2024 19:05:29 +0800 Message-Id: <20240813110532.870869-2-yanfei.xu@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813110532.870869-1-yanfei.xu@intel.com> References: <20240813110532.870869-1-yanfei.xu@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The function cxl_dvsec_rr_decode() retrieves and records DVSEC ranges into info->dvsec_range[], regardless of whether it is non-zero range, and the variable info->ranges indicates the number of non-zero ranges. However, in cxl_hdm_decode_init(), the validation for info->dvsec_range[] occurs in a for loop that iterates based on info->ranges. It may result in zero range to be validated but non-zero range not be validated, in turn, the number of allowed ranges is to be 0. Address it by only record non-zero ranges. This fix is not urgent as it requires a configuration that zeroes out the first dvsec range while populating the second. This has not been observed, but it is theoretically possible. If this gets picked up for -stable, no harm done, but there is no urgency to backport. Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info") Signed-off-by: Yanfei Xu Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a663e7566c48..2d69340134da 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -390,10 +390,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; if (!size) { - info->dvsec_range[i] = (struct range) { - .start = 0, - .end = CXL_RESOURCE_NONE, - }; continue; } @@ -411,12 +407,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK; - info->dvsec_range[i] = (struct range) { + info->dvsec_range[ranges++] = (struct range) { .start = base, .end = base + size - 1 }; - - ranges++; } info->ranges = ranges; From patchwork Tue Aug 13 11:05:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanfei Xu X-Patchwork-Id: 13761817 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B191960EC4 for ; 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a="21262318" X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="21262318" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:09 -0700 X-CSE-ConnectionGUID: moZFYLtfQ0GLwM5gpyMMow== X-CSE-MsgGUID: OTrRLb4sR2Gu6k7D1KgEpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="58568783" Received: from tower.bj.intel.com ([10.238.157.70]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:07 -0700 From: Yanfei Xu To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, ming4.li@intel.com, yanfei.xu@intel.com Subject: [v3 2/4] cxl/pci: Remove duplicated implementation of waiting for memory_info_valid Date: Tue, 13 Aug 2024 19:05:30 +0800 Message-Id: <20240813110532.870869-3-yanfei.xu@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813110532.870869-1-yanfei.xu@intel.com> References: <20240813110532.870869-1-yanfei.xu@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 commit ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory related info") added another implementation of waiting for memory_info_valid without realizing it duplicated wait_for_valid() Suggested-by: Dan Williams Signed-off-by: Yanfei Xu Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 41 +++++------------------------------ drivers/cxl/cxl.h | 2 +- drivers/cxl/port.c | 2 +- tools/testing/cxl/test/mock.c | 4 ++-- 4 files changed, 9 insertions(+), 40 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 2d69340134da..38c567727dbb 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -211,37 +211,6 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) } EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL); -static int wait_for_valid(struct pci_dev *pdev, int d) -{ - u32 val; - int rc; - - /* - * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high - * and Size Low registers are valid. Must be set within 1 second of - * deassertion of reset to CXL device. Likely it is already set by the - * time this runs, but otherwise give a 1.5 second timeout in case of - * clock skew. - */ - rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val); - if (rc) - return rc; - - if (val & CXL_DVSEC_MEM_INFO_VALID) - return 0; - - msleep(1500); - - rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val); - if (rc) - return rc; - - if (val & CXL_DVSEC_MEM_INFO_VALID) - return 0; - - return -ETIMEDOUT; -} - static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val) { struct pci_dev *pdev = to_pci_dev(cxlds->dev); @@ -322,11 +291,13 @@ static int devm_cxl_enable_hdm(struct device *host, struct cxl_hdm *cxlhdm) return devm_add_action_or_reset(host, disable_hdm, cxlhdm); } -int cxl_dvsec_rr_decode(struct device *dev, int d, +int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, struct cxl_endpoint_dvsec_info *info) { struct pci_dev *pdev = to_pci_dev(dev); + struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); int hdm_count, rc, i, ranges = 0; + int d = cxlds->cxl_dvsec; u16 cap, ctrl; if (!d) { @@ -353,11 +324,9 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, if (!hdm_count || hdm_count > 2) return -EINVAL; - rc = wait_for_valid(pdev, d); - if (rc) { - dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc); + rc = cxl_dvsec_mem_range_valid(cxlds, 0); + if (rc) return rc; - } /* * The current DVSEC values are moot if the memory capability is diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9afb407d438f..e2e277463794 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -809,7 +809,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port, int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_endpoint_dvsec_info *info); int devm_cxl_add_passthrough_decoder(struct cxl_port *port); -int cxl_dvsec_rr_decode(struct device *dev, int dvsec, +int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, struct cxl_endpoint_dvsec_info *info); bool is_cxl_region(struct device *dev); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index d7d5d982ce69..861dde65768f 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -98,7 +98,7 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) struct cxl_port *root; int rc; - rc = cxl_dvsec_rr_decode(cxlds->dev, cxlds->cxl_dvsec, &info); + rc = cxl_dvsec_rr_decode(cxlds->dev, port, &info); if (rc < 0) return rc; diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 6f737941dc0e..79fdfaad49e8 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -228,7 +228,7 @@ int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds, } EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL); -int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec, +int __wrap_cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, struct cxl_endpoint_dvsec_info *info) { int rc = 0, index; @@ -237,7 +237,7 @@ int __wrap_cxl_dvsec_rr_decode(struct device *dev, int dvsec, if (ops && ops->is_mock_dev(dev)) rc = 0; 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d="scan'208";a="58568797" Received: from tower.bj.intel.com ([10.238.157.70]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:10 -0700 From: Yanfei Xu To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, ming4.li@intel.com, yanfei.xu@intel.com Subject: [v3 3/4] cxl/pci: Check Mem_info_valid bit for each applicable DVSEC Date: Tue, 13 Aug 2024 19:05:31 +0800 Message-Id: <20240813110532.870869-4-yanfei.xu@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813110532.870869-1-yanfei.xu@intel.com> References: <20240813110532.870869-1-yanfei.xu@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The right way is to checking Mem_info_valid bit for each applicable DVSEC range against HDM_COUNT, not only for the DVSEC range 1, hence let's move the check into the "for loop" of handling each DVSEC range. Signed-off-by: Yanfei Xu Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 38c567727dbb..519989ada48e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -324,10 +324,6 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, if (!hdm_count || hdm_count > 2) return -EINVAL; - rc = cxl_dvsec_mem_range_valid(cxlds, 0); - if (rc) - return rc; - /* * The current DVSEC values are moot if the memory capability is * disabled, and they will remain moot after the HDM Decoder @@ -345,6 +341,10 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, u64 base, size; u32 temp; + rc = cxl_dvsec_mem_range_valid(cxlds, i); + if (rc) + return rc; + rc = pci_read_config_dword( pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); if (rc) From patchwork Tue Aug 13 11:05:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yanfei Xu X-Patchwork-Id: 13761819 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0617D60EC4 for ; Tue, 13 Aug 2024 11:13:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723547596; cv=none; b=EJGFVnI7eFZxBAGj28HkePsRSe8L+Eg6ePmRfovlVwXxUVAkaQJPhuF3FQWKVAFSJwNrTF7TlmJPig7xW3Vl4gCptgGHcKmwGcqQ7o9szXdcXStnYt8cOenjVeykKp9L+jvukAwuoQPH5NcL4QkmE3wJjh9VWCTrMDBeoW/QTqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723547596; c=relaxed/simple; bh=kMjqxcvsJPTaZkKSSakL6w6VOlcnSVu80kSsAT0yGoY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bwFOD5DIB2aR6wiE26bazfeA13wobz/4ss5uaTKDxljXE5Yx9Qt6DHBeLcISTBSkge8jhTXHSm5ZR0nhPOCTVojNbXKMcrXK8sz/SzRFZABrlgKURbCQy3kuFUj//y9240KeWdXLFDOmA9V1PqOITjHVd6iaYwAWVz56uNblvEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a7894Puk; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a7894Puk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723547595; x=1755083595; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kMjqxcvsJPTaZkKSSakL6w6VOlcnSVu80kSsAT0yGoY=; b=a7894PukFtkZdiG5e0UWKFalvrZlVdWpgWgYwJ8VQ/Gk/aXNcRn3Tt2m BWSJXLXewqXU5+sZW37kyxbNYI6ija4rHZlIf7HMH/yGgXh4PqucBE/Zv VNDG6EhtfFoXZaZsBI2vrQToGxGC2Et6+GuwjTVWw4ywBkYnDc7M0WZGk xz/uexeby9yKKgO8OAuuxWprXVFQsU5j/OL3FfcZ6lWSVfST7wl+kd5he ZuSvAY7oXXfB0kRDIcBWBcnoPvCxHJ+oztxvTlUZ5qknghvADssq/Rm2L gMKtx38VZbKTYZAadO7GMHEsDUn8GLEVDyPjRBotek+XqjDwHhCASLmy0 w==; X-CSE-ConnectionGUID: WwygHzvMTu6DrGanDCCD5A== X-CSE-MsgGUID: jtYZoDPBSJSzTrmn1bIIxQ== X-IronPort-AV: E=McAfee;i="6700,10204,11162"; a="21262357" X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="21262357" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:14 -0700 X-CSE-ConnectionGUID: ymDDzEDESySXB8R4SqK64w== X-CSE-MsgGUID: Hz0H4BaqSEeu+LJy+xQm5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,285,1716274800"; d="scan'208";a="58568812" Received: from tower.bj.intel.com ([10.238.157.70]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2024 04:13:13 -0700 From: Yanfei Xu To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, ming4.li@intel.com, yanfei.xu@intel.com Subject: [v3 4/4] cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init() Date: Tue, 13 Aug 2024 19:05:32 +0800 Message-Id: <20240813110532.870869-5-yanfei.xu@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813110532.870869-1-yanfei.xu@intel.com> References: <20240813110532.870869-1-yanfei.xu@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Cases can be divided into two categories which are DVSEC range enabled and not enabled when HDM decoders exist but is not enabled. To avoid checking info->mem_enabled, which indicates the enablement of DVSEC range, every time, we can check !info->mem_enabled once in advance. This simplification can make the code clearer. No functional change intended. Signed-off-by: Yanfei Xu Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 519989ada48e..be00266c8907 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -426,7 +426,15 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, return -ENODEV; } - for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) { + if (!info->mem_enabled) { + rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); + if (rc) + return rc; + + return devm_cxl_enable_mem(&port->dev, cxlds); + } + + for (i = 0, allowed = 0; i < info->ranges; i++) { struct device *cxld_dev; cxld_dev = device_find_child(&root->dev, &info->dvsec_range[i], @@ -440,7 +448,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, allowed++; } - if (!allowed && info->mem_enabled) { + if (!allowed) { dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n"); return -ENXIO; } @@ -454,14 +462,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, * match. If at least one DVSEC range is enabled and allowed, skip HDM * Decoder Capability Enable. */ - if (info->mem_enabled) - return 0; - - rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); - if (rc) - return rc; - - return devm_cxl_enable_mem(&port->dev, cxlds); + return 0; } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);