From patchwork Tue Aug 13 14:47:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762154 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8811D68F; Tue, 13 Aug 2024 14:47:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560477; cv=none; b=svlva5izgerxkztL/NXQTMcLao1DjKOsBwVCOAK1RkzfF4V9vE6PeJ50UzGZNDBpFSvonZoh0BBYyT3F/tdO4fkzD08GQd9OZhRh6KX3CYFf2Sxpmq+R88IG8WmnlJrS23Vs/vhkM75RYH73OE+3+jH8M4oqb9z96Bph0JWa+98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560477; c=relaxed/simple; bh=tQhs6sQmLRKSXnFl/3yZscrAIYRb7Tz89+/QXGEXSMs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d2jKcF7ccjFYmK3FBmXDzPet/fdqSMgZ54PG+1kbVlY/upRZDqm1fOJ6ygrWsIgut2s7BVy9lzzxH2dxfwcJXkQa3G9BI1nySC/MIg3DkykqzDm2kd4D8MW76emxRkAW+yX9p3XYt0Mh0SjQbd9wXN430xT2B3eBeBb0CDlflk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mua16IWe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mua16IWe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39227C4AF0F; Tue, 13 Aug 2024 14:47:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560477; bh=tQhs6sQmLRKSXnFl/3yZscrAIYRb7Tz89+/QXGEXSMs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mua16IWe6C4QYn718rOjMLNbcblOr9rsWmY/KNFHaN/rzsgwnJ2FYozg3S0ZXHdn3 XQqvSKUmzsFM35dhx/cX4M+iQX6oPUYRLzg5SEHAiotV6yp8PnENggPN7wRFON2QZq WT1vZ/oVaslkagtXHsZPDncrFnM69Log5qb2FwBXSKKldd+FZdgwQJbXZLMhAB3+Sm GjBnQF7BchOLmTtemcYGleEXt49v8BPK0ce0BtIDO1bA2ftTGiNFaXhypcghIv/kVH GsvtmU3jrhUoJvlpf2ds+ZBh1YkfHP4iiy4SrPisFAecIV+fdL6J8wfYDGLGtsdqQv /xUCotHq+So0g== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoV-003O27-D7; Tue, 13 Aug 2024 15:47:55 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 01/10] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Date: Tue, 13 Aug 2024 15:47:29 +0100 Message-Id: <20240813144738.2048302-2-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Accessing CNTHCTL_EL2 is fraught with danger if running with HCR_EL2.E2H=1: half of the bits are held in CNTKCTL_EL1, and thus can be changed behind our back, while the rest lives in the CNTHCTL_EL2 shadow copy that is memory-based. Yes, this is a lot of fun! Make sure that we merge the two on read access, while we can write to CNTKCTL_EL1 in a more straightforward manner. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 28 ++++++++++++++++++++++++++++ include/kvm/arm_arch_timer.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c90324060436..95832881fd66 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -140,6 +140,21 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) if (!is_hyp_ctxt(vcpu)) goto memory_read; + /* + * CNTHCTL_EL2 requires some special treatment to + * account for the bits that can be set via CNTKCTL_EL1. + */ + switch (reg) { + case CNTHCTL_EL2: + if (vcpu_el2_e2h_is_set(vcpu)) { + val = read_sysreg_el1(SYS_CNTKCTL); + val &= CNTKCTL_VALID_BITS; + val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS; + return val; + } + break; + } + /* * If this register does not have an EL1 counterpart, * then read the stored EL2 version. @@ -190,6 +205,19 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) */ __vcpu_sys_reg(vcpu, reg) = val; + switch (reg) { + case CNTHCTL_EL2: + /* + * If E2H=0, CNHTCTL_EL2 is a pure shadow register. + * Otherwise, some of the bits are backed by + * CNTKCTL_EL1, while the rest is kept in memory. + * Yes, this is fun stuff. + */ + if (vcpu_el2_e2h_is_set(vcpu)) + write_sysreg_el1(val, SYS_CNTKCTL); + return; + } + /* No EL1 counterpart? We're done here.? */ if (reg == el1r) return; diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index c819c5d16613..fd650a8789b9 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -147,6 +147,9 @@ u64 timer_get_cval(struct arch_timer_context *ctxt); void kvm_timer_cpu_up(void); void kvm_timer_cpu_down(void); +/* CNTKCTL_EL1 valid bits as of DDI0487J.a */ +#define CNTKCTL_VALID_BITS (BIT(17) | GENMASK_ULL(9, 0)) + static inline bool has_cntpoff(void) { return (has_vhe() && cpus_have_final_cap(ARM64_HAS_ECV_CNTPOFF)); From patchwork Tue Aug 13 14:47:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762156 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C6419FA8A; Tue, 13 Aug 2024 14:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=fw2LG/23uycEaERuJBT6wzRAZ3dR++RTQdoN9SJaXowsLnOpcJbrtrC5RjyeSa5jQVkLkK25tiiSyyx4WTwhO8RnqH3EWZX5Fu4/gXlPMlWEjIfeeZytRvi0OMTH/RhubRlNqLqrq30dfyIC3qWbxup6UY+AvVhCFF9xTrZm/Cc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=38G/HWi8wcBRl5YO/Y32Kqhg8KYAnYo3gA4UsZj0qjE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U/INxgWCCxJhDGGiYIvsEW7cNlLVWmCeHyFVfLID8IqaCt0zD5SA42qXXuoB8x0fU/BiBTCJqb8S1RIkVRBd208XMVmrU9CXg54d+qRbE/zkA2BHNIihITDmud443jPKuj3+hZygr0fylJqDqnrmYvra/qTk8MY7246WhfpDM0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=go0FWEf7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="go0FWEf7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2E25C4AF11; Tue, 13 Aug 2024 14:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560478; bh=38G/HWi8wcBRl5YO/Y32Kqhg8KYAnYo3gA4UsZj0qjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=go0FWEf7PwrN6nLHezhEUUScwaRuGg+s1Ss6mEUbE2f7GJB+QUDpW8SXVSslh4FBo gr/AxT0Pue01ICbXGcjUWPLS4GaNFSWF5CDkITHVrykDzPGtE6TzXnCJ94djqtqf9i rZLolaFVa9Tzlc/P8hFON1/vWlZUO8aav2s9DEbCA0EIOAo8T/itONPMCerLNdZfrK CRtwZxUkZAPL+mdp1cilB9iBhQFnNlDa0bUNT1THfeE8OBqP+1B3k/EwTax25F05uB xlbaNr7a9gF78MBk6RSGhFE6dA3NehGI38SpS4iZstYMUFuydt3oXHHZF48OnIJrZh RcLjb8fTNk9bg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoV-003O27-JD; Tue, 13 Aug 2024 15:47:56 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 02/10] KVM: arm64: nv: Save/Restore vEL2 sysregs Date: Tue, 13 Aug 2024 15:47:30 +0100 Message-Id: <20240813144738.2048302-3-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Whenever we need to restore the guest's system registers to the CPU, we now need to take care of the EL2 system registers as well. Most of them are accessed via traps only, but some have an immediate effect and also a guest running in VHE mode would expect them to be accessible via their EL1 encoding, which we do not trap. For vEL2 we write the virtual EL2 registers with an identical format directly into their EL1 counterpart, and translate the few registers that have a different format for the same effect on the execution when running a non-VHE guest guest hypervisor. Based on an initial patch from Andre Przywara, rewritten many times since. Reviewed-by: Alexandru Elisei Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 5 +- arch/arm64/kvm/hyp/nvhe/sysreg-sr.c | 2 +- arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 137 ++++++++++++++++++++- 3 files changed, 139 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h index 4c0fdabaf8ae..dfbc0159bf0b 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -128,9 +128,10 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt) write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); } -static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) +static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, + u64 mpidr) { - write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); + write_sysreg(mpidr, vmpidr_el2); if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { diff --git a/arch/arm64/kvm/hyp/nvhe/sysreg-sr.c b/arch/arm64/kvm/hyp/nvhe/sysreg-sr.c index 29305022bc04..dba101565de3 100644 --- a/arch/arm64/kvm/hyp/nvhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/sysreg-sr.c @@ -28,7 +28,7 @@ void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt) void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt) { - __sysreg_restore_el1_state(ctxt); + __sysreg_restore_el1_state(ctxt, ctxt_sys_reg(ctxt, MPIDR_EL1)); __sysreg_restore_common_state(ctxt); __sysreg_restore_user_state(ctxt); __sysreg_restore_el2_return_state(ctxt); diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c index e12bd7d6d2dc..6db5b4d0f3a4 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -15,6 +15,108 @@ #include #include +static void __sysreg_save_vel2_state(struct kvm_cpu_context *ctxt) +{ + /* These registers are common with EL1 */ + ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg(par_el1); + ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1); + + ctxt_sys_reg(ctxt, ESR_EL2) = read_sysreg_el1(SYS_ESR); + ctxt_sys_reg(ctxt, AFSR0_EL2) = read_sysreg_el1(SYS_AFSR0); + ctxt_sys_reg(ctxt, AFSR1_EL2) = read_sysreg_el1(SYS_AFSR1); + ctxt_sys_reg(ctxt, FAR_EL2) = read_sysreg_el1(SYS_FAR); + ctxt_sys_reg(ctxt, MAIR_EL2) = read_sysreg_el1(SYS_MAIR); + ctxt_sys_reg(ctxt, VBAR_EL2) = read_sysreg_el1(SYS_VBAR); + ctxt_sys_reg(ctxt, CONTEXTIDR_EL2) = read_sysreg_el1(SYS_CONTEXTIDR); + ctxt_sys_reg(ctxt, AMAIR_EL2) = read_sysreg_el1(SYS_AMAIR); + + /* + * In VHE mode those registers are compatible between EL1 and EL2, + * and the guest uses the _EL1 versions on the CPU naturally. + * So we save them into their _EL2 versions here. + * For nVHE mode we trap accesses to those registers, so our + * _EL2 copy in sys_regs[] is always up-to-date and we don't need + * to save anything here. + */ + if (__vcpu_el2_e2h_is_set(ctxt)) { + u64 val; + + /* + * We don't save CPTR_EL2, as accesses to CPACR_EL1 + * are always trapped, ensuring that the in-memory + * copy is always up-to-date. A small blessing... + */ + ctxt_sys_reg(ctxt, SCTLR_EL2) = read_sysreg_el1(SYS_SCTLR); + ctxt_sys_reg(ctxt, TTBR0_EL2) = read_sysreg_el1(SYS_TTBR0); + ctxt_sys_reg(ctxt, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1); + ctxt_sys_reg(ctxt, TCR_EL2) = read_sysreg_el1(SYS_TCR); + + /* + * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where + * the interesting CNTHCTL_EL2 bits live. So preserve these + * bits when reading back the guest-visible value. + */ + val = read_sysreg_el1(SYS_CNTKCTL); + val &= CNTKCTL_VALID_BITS; + ctxt_sys_reg(ctxt, CNTHCTL_EL2) &= ~CNTKCTL_VALID_BITS; + ctxt_sys_reg(ctxt, CNTHCTL_EL2) |= val; + } + + ctxt_sys_reg(ctxt, SP_EL2) = read_sysreg(sp_el1); + ctxt_sys_reg(ctxt, ELR_EL2) = read_sysreg_el1(SYS_ELR); + ctxt_sys_reg(ctxt, SPSR_EL2) = read_sysreg_el1(SYS_SPSR); +} + +static void __sysreg_restore_vel2_state(struct kvm_cpu_context *ctxt) +{ + u64 val; + + /* These registers are common with EL1 */ + write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1); + write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1); + + write_sysreg(read_cpuid_id(), vpidr_el2); + write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); + write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL2), SYS_MAIR); + write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL2), SYS_VBAR); + write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL2),SYS_CONTEXTIDR); + write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL2), SYS_AMAIR); + + if (__vcpu_el2_e2h_is_set(ctxt)) { + /* + * In VHE mode those registers are compatible between + * EL1 and EL2. + */ + write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL2), SYS_SCTLR); + write_sysreg_el1(ctxt_sys_reg(ctxt, CPTR_EL2), SYS_CPACR); + write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL2), SYS_TTBR0); + write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL2), SYS_TTBR1); + write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL2), SYS_TCR); + write_sysreg_el1(ctxt_sys_reg(ctxt, CNTHCTL_EL2), SYS_CNTKCTL); + } else { + /* + * CNTHCTL_EL2 only affects EL1 when running nVHE, so + * no need to restore it. + */ + val = translate_sctlr_el2_to_sctlr_el1(ctxt_sys_reg(ctxt, SCTLR_EL2)); + write_sysreg_el1(val, SYS_SCTLR); + val = translate_cptr_el2_to_cpacr_el1(ctxt_sys_reg(ctxt, CPTR_EL2)); + write_sysreg_el1(val, SYS_CPACR); + val = translate_ttbr0_el2_to_ttbr0_el1(ctxt_sys_reg(ctxt, TTBR0_EL2)); + write_sysreg_el1(val, SYS_TTBR0); + val = translate_tcr_el2_to_tcr_el1(ctxt_sys_reg(ctxt, TCR_EL2)); + write_sysreg_el1(val, SYS_TCR); + } + + write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL2), SYS_ESR); + write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL2), SYS_AFSR0); + write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL2), SYS_AFSR1); + write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL2), SYS_FAR); + write_sysreg(ctxt_sys_reg(ctxt, SP_EL2), sp_el1); + write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL2), SYS_ELR); + write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL2), SYS_SPSR); +} + /* * VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and * pstate, which are handled as part of the el2 return state) on every @@ -66,6 +168,7 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *guest_ctxt = &vcpu->arch.ctxt; struct kvm_cpu_context *host_ctxt; + u64 mpidr; host_ctxt = host_data_ptr(host_ctxt); __sysreg_save_user_state(host_ctxt); @@ -89,7 +192,29 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) */ __sysreg32_restore_state(vcpu); __sysreg_restore_user_state(guest_ctxt); - __sysreg_restore_el1_state(guest_ctxt); + + if (unlikely(__is_hyp_ctxt(guest_ctxt))) { + __sysreg_restore_vel2_state(guest_ctxt); + } else { + if (vcpu_has_nv(vcpu)) { + /* + * Only set VPIDR_EL2 for nested VMs, as this is the + * only time it changes. We'll restore the MIDR_EL1 + * view on put. + */ + write_sysreg(ctxt_sys_reg(guest_ctxt, VPIDR_EL2), vpidr_el2); + + /* + * As we're restoring a nested guest, set the value + * provided by the guest hypervisor. + */ + mpidr = ctxt_sys_reg(guest_ctxt, VMPIDR_EL2); + } else { + mpidr = ctxt_sys_reg(guest_ctxt, MPIDR_EL1); + } + + __sysreg_restore_el1_state(guest_ctxt, mpidr); + } vcpu_set_flag(vcpu, SYSREGS_ON_CPU); } @@ -112,12 +237,20 @@ void __vcpu_put_switch_sysregs(struct kvm_vcpu *vcpu) host_ctxt = host_data_ptr(host_ctxt); - __sysreg_save_el1_state(guest_ctxt); + if (unlikely(__is_hyp_ctxt(guest_ctxt))) + __sysreg_save_vel2_state(guest_ctxt); + else + __sysreg_save_el1_state(guest_ctxt); + __sysreg_save_user_state(guest_ctxt); __sysreg32_save_state(vcpu); /* Restore host user state */ __sysreg_restore_user_state(host_ctxt); + /* If leaving a nesting guest, restore MPIDR_EL1 default view */ + if (vcpu_has_nv(vcpu)) + write_sysreg(read_cpuid_id(), vpidr_el2); + vcpu_clear_flag(vcpu, SYSREGS_ON_CPU); } From patchwork Tue Aug 13 14:47:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762155 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 182381D68F; Tue, 13 Aug 2024 14:47:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=HM7FqfXjHS7hDuOwFv9Tg8psgXXQ15RYLJiRWwd0DD7+tKAj8nDtf/FoMQE7IM4ccTlL/Y8oWQwSuOmvGpdxnTcPkCQvHm1oopxGJmK/HKwUPNY1zo28mFdgG7elNbsLHj62y2N9H8vVOJOJd8Vhl1y4aYtI+7nXP26XOj9rETA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=/44hNubfAJPoo02XSxaPr9+x1CFGhuefxVXsc2EW9QQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ut1arZXJI8eFw8CdjT1gA1/fHIKgmzy+rjSiEhh23TVv2srm1ir1fO0Ptri6fZnuS9JNVmN0jPd2MJl1amblMo4kig+8mUZKMFKCQDn+HwkV0FBpnpOJFdVU8J0YlGWto15IzvnmIYZ1bsa84KF0SNv0dXs3AfKQMBYago9X7KI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Lm42YvMY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Lm42YvMY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A890EC4AF0F; Tue, 13 Aug 2024 14:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560478; bh=/44hNubfAJPoo02XSxaPr9+x1CFGhuefxVXsc2EW9QQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lm42YvMY/V/0fQfMmYVV8Edn24AkcsvAv93AsDpQCZc5R2j9H0gcw5BxxJqODy1Rb nQRvbz86dE2sOTZnhbLtUyUNp437A++RSXsgaNMaq1sW67fOGaeMVQUBPDH/3wFEsP cMFQc4ZP0OhuzPyBBv7h/MBmv0CKrI/2FQAwzP078qO9kmiE7kqUNgjLtqG4dkNhEL +u3MaEg9RVNfOPxJegv3H2mpZ0mAQnb9MqYucc4EHIMAsOmBLw30VRTKw2JtuT87Nv FRDFJzFiJs73PS/+0Nwc0ZW0/KOnU0Y05pQpTcfUKs6tkyKdmpH/rLzQecuQCR2d7Q v6ikXH9ku7HTw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoW-003O27-P4; Tue, 13 Aug 2024 15:47:56 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 03/10] KVM: arm64: Add TCR2_EL2 to the sysreg arrays Date: Tue, 13 Aug 2024 15:47:31 +0100 Message-Id: <20240813144738.2048302-4-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the TCR2_EL2 register to the per-vcpu sysreg register array, as well as the sysreg descriptor array. Access to this register is conditionned on ID_AA64MMFR3_EL1.TCRX being advertised. Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/sys_regs.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a33f5996ca9f..5a9e0ad35580 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -462,6 +462,7 @@ enum vcpu_sysreg { TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */ TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ + TCR2_EL2, /* Extended Translation Control Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 95832881fd66..52250db3c122 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -436,6 +436,18 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, return true; } +static bool access_tcr2_el2(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) { + kvm_inject_undefined(vcpu); + return false; + } + + return access_rw(vcpu, p, r); +} + static bool access_actlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -2783,6 +2795,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), + EL2_REG(TCR2_EL2, access_tcr2_el2, reset_val, TCR2_EL2_RES1), EL2_REG_VNCR(VTTBR_EL2, reset_val, 0), EL2_REG_VNCR(VTCR_EL2, reset_val, 0), From patchwork Tue Aug 13 14:47:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762158 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4433119FA8E; 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SAEximRunCond expanded to false Like its EL1 equivalent, TCR2_EL2 gets context-switched. This is made conditional on FEAT_TCRX being adversised. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c index 6db5b4d0f3a4..7099775cd505 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -51,6 +51,9 @@ static void __sysreg_save_vel2_state(struct kvm_cpu_context *ctxt) ctxt_sys_reg(ctxt, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1); ctxt_sys_reg(ctxt, TCR_EL2) = read_sysreg_el1(SYS_TCR); + if (ctxt_has_tcrx(ctxt)) + ctxt_sys_reg(ctxt, TCR2_EL2) = read_sysreg_el1(SYS_TCR2); + /* * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where * the interesting CNTHCTL_EL2 bits live. So preserve these @@ -108,6 +111,9 @@ static void __sysreg_restore_vel2_state(struct kvm_cpu_context *ctxt) write_sysreg_el1(val, SYS_TCR); } + if (ctxt_has_tcrx(ctxt)) + write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL2), SYS_TCR2); + write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL2), SYS_ESR); write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL2), SYS_AFSR0); write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL2), SYS_AFSR1); From patchwork Tue Aug 13 14:47:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762157 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C1719FA6B; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=tgDi41Dwxpu9tlaNkUP0WojjoTL18xMh1i1ljRIyK6f7x4b18MqHCpOoabOknQVvO2PTj+4oZBhVo3w/F6FFRPnPr9PdfsLHykeRMpTVnSL+nAQl+hr6R+bF94aEF7ByOHQZuF8FcNQqYlUCb/YihTuiGY7+srFUnH0Y2+MRs/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=vT/5asr8l07sZbrUs7NSkiwidQ979neRK/s0Vwf6rPA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qjj0KXtaoEohni4nmea84XZTvT5uJqg8laGTsBlyvopml7zGpcbAjd1NhZnW3yM7t5UnX6/t5RTKLZzWxF/axrZJj5h8tJmW77cqEIvhvwIFZ72+8fJAUA0ZKZtlDjfOZ7JNnmIpRAZoAaUxVEvYZU7zGRk9ROIbzf05QgzdE6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qsGJ919E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qsGJ919E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA2E0C4AF17; Tue, 13 Aug 2024 14:47:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560478; bh=vT/5asr8l07sZbrUs7NSkiwidQ979neRK/s0Vwf6rPA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qsGJ919E5blg80Wg3QFLF39t16IkKhfRmKXBO3HXWSN64qjKCN6pkmJkSil044iCG 5WpqU6aMPlDfy2nzqqFc9TRjB73SBKfipXVyx5bUqc+ZEc9RWEG7XA9hklzDcRJed0 W6vdHrul5sPxWFI+pqPeZCwXBkLNVMRvVdRL1MbqWObz73tUH/MDN7prf0PKPC5KT+ oOGF+BYSNPOLRqUyFYPYn62LC/8+USaJvpr5tZGitxvM/2SlKQPfMhYXIvbMnau3k3 +LcNpU2Fn9zaPlHB+v64fXhwlERNBS2HSST4ZgXC986AHfnX8dIZ97JmpN+PmQSI+O TsYxs8FnByGWg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-4v; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 05/10] arm64: Add encoding for PIRE0_EL2 Date: Tue, 13 Aug 2024 15:47:33 +0100 Message-Id: <20240813144738.2048302-6-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false PIRE0_EL2 is the equivalent of PIRE0_EL1 for the EL2&0 translation regime, and it is sorely missing from the sysreg file. Add the sucker. Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7ceaa1e0b4bc..8e1aed548e93 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2853,6 +2853,10 @@ Sysreg PIRE0_EL12 3 5 10 2 2 Fields PIRx_ELx EndSysreg +Sysreg PIRE0_EL2 3 4 10 2 2 +Fields PIRx_ELx +EndSysreg + Sysreg PIR_EL1 3 0 10 2 3 Fields PIRx_ELx EndSysreg From patchwork Tue Aug 13 14:47:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762159 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 705D11A00D0; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=UGNq33MjOMEMp9dZKPfJdjoV86MZ/T21cE4Hl1cZhmO8uXtIqPYjaYJ8GcyT4bzPzwadekUMYgAqLsdo65LsoqPP6UY32XraunO97HM+aXUMQb2l8En8FyhKVX8wWy66tyzeUxlDOycSFOeQCDLYLCEvQZR6wGX1T8uKdTmau1Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=ffoZGFIxqM7xv66FGMTRLGczJEXgIqnAiwt3W1CgEKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pseuJgpr7ayB1ckvilGbBmlJa8MpfXNFaHuwjWqkyheXCvxJmoXtEa2sb0H2Eo1NqIV9n7PlWzVCGnXm5qytYOMpR5tetcOUaNcoXaP5LFxrp9evVOms/8tUtrTPpLqftBXoHqinvu/HChhNlP0M5+DhyxXYKC1IiD8F80oFZpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yf5Q24ZK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yf5Q24ZK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 13077C4AF0B; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=ffoZGFIxqM7xv66FGMTRLGczJEXgIqnAiwt3W1CgEKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yf5Q24ZK02j7lMO+tm5EQ320nqC4YCnMQreegy+3BhzJBpruYdeGwVnEg36lccXaq FokVoW2eO6crbLwId9e+grv5dxHFJoWvRuyA9YvtIt9v3SQJY+lXM1kDphLOYKLMFx z8aOj8kXSD3r5mr9DPQ3z9QYBOW0YntMKTUC2lVwYU/rihAjDJKiOeDDnR3XKk35/C bCI2dA4jJ0xAxTiTsPhKNfR5nDHjeIxC4OfIDnXV+nyOeYUxteQKme3w23Cqcjpbz6 Zj6ojUdyaFTxU/eXNi/LFsETSygosjbr8kQQkNkf5EY8vN99CYhli90SMDTljM/oIn 4eER39So1t51A== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-Aj; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 06/10] arm64: Remove VNCR definition for PIRE0_EL2 Date: Tue, 13 Aug 2024 15:47:34 +0100 Message-Id: <20240813144738.2048302-7-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false As of the ARM ARM Known Issues document 102105_K.a_04_en, D22677 fixes a problem with the PIRE0_EL2 register, resulting in its removal from the VNCR page (it had no purpose being there the first place). Follow the architecture update by removing this offset. Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly --- arch/arm64/include/asm/vncr_mapping.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h index df2c47c55972..9e593bb60975 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -50,7 +50,6 @@ #define VNCR_VBAR_EL1 0x250 #define VNCR_TCR2_EL1 0x270 #define VNCR_PIRE0_EL1 0x290 -#define VNCR_PIRE0_EL2 0x298 #define VNCR_PIR_EL1 0x2A0 #define VNCR_ICH_LR0_EL2 0x400 #define VNCR_ICH_LR1_EL2 0x408 From patchwork Tue Aug 13 14:47:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762160 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC9A31A01A6; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=JIeKJGd/rG5avjwFugsYRJjA6+xA7REwnwSj27AMsFhF54FNOO8TQLTngjHyNN+DLcCbIglCc9A7rpufm/i36eM901hp6oKylrbsq8uh3aezGisTVsMhV3gZ5CxIVja2FPbmTw2+S3ZP7Zr+0wz3k54qQkr1rW9nJH0ftD/nDsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=gWUfxT4H7N3nyM/fDaVuQppiX/holJhsvKWB8A/mp8M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VqWn9dMGO0UBtDSN+uqzw3bUj7pXX0zFlVJcmwLuV4E7wRNIYboXaRpbK/QxmwE8bcSzzGZZlNZ/S3YYuJaWCTprESMBZgxjLXZCHhOBwyk1EHnptBwm+9S9UyhBmXc60dPn+ODx2DlIEGoLWbtGyYXy/TiZiElOWHDjb/L/QE4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZOXWQ/uu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZOXWQ/uu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45CB3C4AF09; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=gWUfxT4H7N3nyM/fDaVuQppiX/holJhsvKWB8A/mp8M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZOXWQ/uuhtreZiZYd+UdimB/6W8H0FkqRHy+e17ixlOYrRx5S495mnibSOOPkUeVW cnubOdxT81UtKCI4DFQcdcUt8+TFrX3/L0GfpY/a555YKGadJH4lnsS3357TZ3icpd 3duwoc/mArirUwLADcl+Xa0y9PsP8qtv5Fpgqo5mRzjYNDLp0Bf39dcJfb4J+EmSJs sG9XzUueNAMdHaYXljpj3Sy/3hw3xI3Q4+XbxddjFiNJXCkYfjfgDL4dpC/jFCAK3f geqC0f0ZDRtj+41E4wYAxGaRhz3P4Z8beM04uOexmnMC+yq/3L/l/kHVlxjs0EifVI Z1GMF4yag9jlg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-HY; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 07/10] KVM: arm64: Add PIR{,E0}_EL2 to the sysreg arrays Date: Tue, 13 Aug 2024 15:47:35 +0100 Message-Id: <20240813144738.2048302-8-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the FEAT_S1PIE EL2 registers to the per-vcpu sysreg register array. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 5a9e0ad35580..ab4c675b491d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -463,6 +463,8 @@ enum vcpu_sysreg { TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */ TCR_EL2, /* Translation Control Register (EL2) */ TCR2_EL2, /* Extended Translation Control Register (EL2) */ + PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ + PIR_EL2, /* Permission Indirection Register 1 (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ From patchwork Tue Aug 13 14:47:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762161 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC9581A01A1; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; cv=none; b=V7vttAef7vGd2je33U8JY3vbga/aTE5++ohip69FAjHGGOsK2wwqH525J5NM6lHvm1vVAUylwrd4QRZxMyJXpqwCx60Jg2H223Y0DtozB1Ke7pPrSZs9q3CMa6goKLa5zyA0P3GhaYgskkEyCDoQvmrezginDN9OSxT+YRCbwPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560479; c=relaxed/simple; bh=ATetRkoABuojbU2sqycPOK9TZdZKTrv3E7DRvX/cAj8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LX9wzXde6voNxdZCWMbjvQnwGd1b6xyly5BmTU0C0i0Tg04SQNQz56lUlEU6zvjbKolRb4fx+hH3dRRZ5/InHUoKC97DVsHX3r1C/Mmw7fkI1rBlCOkLAl/QUGL17QQ0rTJ8Ee6Ran0w7Wod/FTL/8Vd7Kzk/zY4Tsct3+ilR2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fgxd1MgI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fgxd1MgI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73010C4AF0F; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=ATetRkoABuojbU2sqycPOK9TZdZKTrv3E7DRvX/cAj8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fgxd1MgIcHC7pfYy3t1acnCQ3Rb5NNnrhh4pqmVn6mAsAs7JxenbuBj4Dxsuj81Nu MOSY0WZUg4uwYl+IfhXBK9l0rUGhdKSOviCqT2Gl/RR3jwXa8CMxxmlQ1GMW76qD+c 8pJj5qwYfhAZAgwFMl3wzEMGw1T9CJEkvxyJhcw9op14TY0d+9EQ1iG9hySygk/OzP pzbsmcPN18zwhPJbioaOn/R70+zV5yS75cIKFT6Jn2ZIBBC23nPt6h0Zf4zIkAV7wO HKENbmvgiItcEJNMCsS5kgBeN9D52G340FhXO8zMO1mgkQ4enUED9gZc5lvVji0XaE lAiZQzYuFt0Ng== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-NR; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 08/10] KVM: arm64: Add save/restore for PIR{,E0}_EL2 Date: Tue, 13 Aug 2024 15:47:36 +0100 Message-Id: <20240813144738.2048302-9-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Like their EL1 equivalent, the EL2-specific FEAT_S1PIE registers are context-switched. This is made conditional on both FEAT_TCRX and FEAT_S1PIE being adversised. Note that this change only makes sense if read together with the issue D22677 contained in 102105_K.a_04_en. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c index 7099775cd505..01551037df08 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -51,9 +51,15 @@ static void __sysreg_save_vel2_state(struct kvm_cpu_context *ctxt) ctxt_sys_reg(ctxt, TTBR1_EL2) = read_sysreg_el1(SYS_TTBR1); ctxt_sys_reg(ctxt, TCR_EL2) = read_sysreg_el1(SYS_TCR); - if (ctxt_has_tcrx(ctxt)) + if (ctxt_has_tcrx(ctxt)) { ctxt_sys_reg(ctxt, TCR2_EL2) = read_sysreg_el1(SYS_TCR2); + if (ctxt_has_s1pie(ctxt)) { + ctxt_sys_reg(ctxt, PIRE0_EL2) = read_sysreg_el1(SYS_PIRE0); + ctxt_sys_reg(ctxt, PIR_EL2) = read_sysreg_el1(SYS_PIR); + } + } + /* * The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where * the interesting CNTHCTL_EL2 bits live. So preserve these @@ -111,9 +117,15 @@ static void __sysreg_restore_vel2_state(struct kvm_cpu_context *ctxt) write_sysreg_el1(val, SYS_TCR); } - if (ctxt_has_tcrx(ctxt)) + if (ctxt_has_tcrx(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL2), SYS_TCR2); + if (ctxt_has_s1pie(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL2), SYS_PIR); + write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL2), SYS_PIRE0); + } + } + write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL2), SYS_ESR); write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL2), SYS_AFSR0); write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL2), SYS_AFSR1); From patchwork Tue Aug 13 14:47:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762163 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F1701A0706; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; cv=none; b=r5tF4yWKUOqUAtH9j0jeld8SY/97gg5wA+ppkNsN1aFEa49NFlc4GnUKbZwN5dQmYIJZJdOwkDMVK35id6cG3r+hYYlxtKBu1dxEzHLSYxhr6vC0kW9Czfhpl3z2hQBWNvZ/PXk6sKkvqCc72DpM3uDsFZI1Bu9L9CfX2FrANzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; c=relaxed/simple; bh=KQvPl9jkOYcV8P9wWE6qdftXypsGkKyrUThzcFU4ltI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lCZJS1kr9+SONZgyA+46b647y4Xba+IYA31zCm7I5JFbuFKFaTV4Lt2s46h0NJpVb0ubGmJPbkORezWgpmokjtTpe9oASlIUEOy94bPDgresENwnH5IlHEnLxDMcs0JqjJPMW2vQwjL4rI0oWVUYXVg3MZPM0LN9b2QNcuooTe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FNgtxxsT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FNgtxxsT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEDC7C4AF09; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=KQvPl9jkOYcV8P9wWE6qdftXypsGkKyrUThzcFU4ltI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FNgtxxsTxMK/KISWsCyudIeBOfKdkd1O0ce2uB0wiWghdziy21ij6bUK6nSCvu0jv 78caEUd945rYdLXm+7BFotvBenAupm+DyU/zkHr45ty1miJcjfncOerun9PfI63iCf vMq5uOtVXjGKAN2jtQuiJeQoVo7PeHxL7ZQdbGyHvsWRkgp3uh8jd4i2ZKPoWLtnxx LBNJYVb2RkHafsAh01BQ9KVMfjUnzDPAc3o3FJJHQSC/GXRRA5OLx0FFHpkUdSYWwB 1aDlaqdXop7lM2ngI511ADeZbIfHvhk468hiIe71T1i2dXqW/px8NwC/tRR1MHueO6 VIRqxtRR8gWyA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoX-003O27-Tg; Tue, 13 Aug 2024 15:47:57 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 09/10] KVM: arm64: Handle PIR{,E0}_EL2 traps Date: Tue, 13 Aug 2024 15:47:37 +0100 Message-Id: <20240813144738.2048302-10-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the FEAT_S1PIE EL2 registers the sysreg descriptor array so that they can be handled as a trap. Access to these registers is conditionned on ID_AA64MMFR3_EL1.S1PIE being advertised. Similarly to other other changes, PIRE0_EL2 is guaranteed to trap thanks to the D22677 update to the architecture.. Signed-off-by: Marc Zyngier Reviewed-by: Joey Gouly --- arch/arm64/kvm/sys_regs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 52250db3c122..a5f604e24e05 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -346,6 +346,18 @@ static bool access_rw(struct kvm_vcpu *vcpu, return true; } +static bool check_s1pie_access_rw(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1PIE, IMP)) { + kvm_inject_undefined(vcpu); + return false; + } + + return access_rw(vcpu, p, r); +} + /* * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). */ @@ -2827,6 +2839,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { EL2_REG(HPFAR_EL2, access_rw, reset_val, 0), EL2_REG(MAIR_EL2, access_rw, reset_val, 0), + EL2_REG(PIRE0_EL2, check_s1pie_access_rw, reset_val, 0), + EL2_REG(PIR_EL2, check_s1pie_access_rw, reset_val, 0), EL2_REG(AMAIR_EL2, access_rw, reset_val, 0), EL2_REG(VBAR_EL2, access_rw, reset_val, 0), From patchwork Tue Aug 13 14:47:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13762162 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16ECF1A01D3; Tue, 13 Aug 2024 14:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; cv=none; b=FL9WjQJxN03eKD0jy7MQNNdRyi83H1aH8ekAi6+iEK58kUAJX+KwN+FfXlAUPCitAYplOg3G4iGd9vHF+So3mrMVtQ3UsIiihdcJmCysWQOpYMUJ7s92Hxt+pyZnIvHY1z+Fg6LFJkYos/2mgE4GBTiQ8a1xdz0x0lUtkqRZOMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723560480; c=relaxed/simple; bh=NGd3Mb3ENRIp6A9T4Pf1BLV4E8SBAeETl4uymIM47B8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qJ67SQTqFiv1ICYoYYW4mWFnjA2E34r3whTpUywr9EP9XGB0tmGkO9fA7NzP67Nke5KOHmZwJGsBeCvQ9R6WEYEmokdRoXDZLDBMZZftAyT3c3jKCtDlIsPtLQhtmbeEh+tZFqmHI9qIEFT1iwOryCzHDfVC8EonCyVZoc+6vTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZA/cF76l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZA/cF76l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E791AC4AF0B; Tue, 13 Aug 2024 14:47:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723560479; bh=NGd3Mb3ENRIp6A9T4Pf1BLV4E8SBAeETl4uymIM47B8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZA/cF76l6U156/7LIc2fvEMyZ/LqNWJOCvoHqGEcaRoIFBRHx34ofDm7JDFScY9Xa kvh3IFoiTQP5HA/Q0ZMoSz5Cm3gcG1YYFFSo3cHTERn7HBl0p2id9i83w+VH4VLmyj oNFKJNh3MnAUuck9qOE3sF/zTsOyfNkNIA7JMWwnYnosxSiSivHUqKXUaZGfCDTvY0 zTLPKn/fmy2V1SQc+IYbtdwhRC3kUYoRPEWDCgeOA4BcehfCopq/4K7mf/FuFgiz5i r8l3B92M+scQXu3f8sIPvkGQfVj6jEvzXqOt/XR08rwSYLdm1sKQqjWKlhccKlANyB GWAECsoxuJqdQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdsoY-003O27-3L; Tue, 13 Aug 2024 15:47:58 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Alexandru Elisei Subject: [PATCH 10/10] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Date: Tue, 13 Aug 2024 15:47:38 +0100 Message-Id: <20240813144738.2048302-11-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240813144738.2048302-1-maz@kernel.org> References: <20240813144738.2048302-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Add the missing sanitisation of ID_AA64MMFR3_EL1, making sure we solely expose S1PIE and TCRX (we currently don't support anything else). Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a5f604e24e05..d0b4509e59cb 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1608,6 +1608,9 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, case SYS_ID_AA64MMFR2_EL1: val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; break; + case SYS_ID_AA64MMFR3_EL1: + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1PIE; + break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); break; @@ -2470,7 +2473,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64MMFR2_EL1_IDS | ID_AA64MMFR2_EL1_NV | ID_AA64MMFR2_EL1_CCIDX)), - ID_SANITISED(ID_AA64MMFR3_EL1), + ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | + ID_AA64MMFR3_EL1_S1PIE)), ID_SANITISED(ID_AA64MMFR4_EL1), ID_UNALLOCATED(7,5), ID_UNALLOCATED(7,6),