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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 1/4] net/mlx5e: SHAMPO, Fix page leak Date: Thu, 15 Aug 2024 10:16:08 +0300 Message-ID: <20240815071611.2211873-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815071611.2211873-1-tariqt@nvidia.com> References: <20240815071611.2211873-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE6:EE_|SJ2PR12MB8011:EE_ X-MS-Office365-Filtering-Correlation-Id: 2432da12-e688-4ca1-2be0-08dcbcfa7199 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: NUaKqURTEFR00YaPJzW1UtgGBdYT0w/xbrNhBsXdb8ldVFV6O7EQLattXxJkC+RvtpMlyDnMvbrSdA4lLMNPoy2mfjZrOsYnlqCZ6SIqfZkLFMUIb014oSOg8gpf+PV61Jkm9Ext3B8Oi4ITLEMYt7Bw1WUkUaEm9KBg4foHt5YEda4Cz3npR0BxI9azSOfgKWTydmQG0d3s7myvNkQeyxAFb6ziw847qkZTBai4yc+VDaaYA/ONDXk44eWWbMO+2Nvv6i1i2O87+om1R0rf6tamR4qOxfsEOjKKvH8YqGXxBC+cLPL+0Fyov51e5IOOs+PVrHf95PLrWQQXOXQhntppnbT90z6ME+H1iUI8uzuPh9jrArstdyYwLDHITgXuEG62heUlvhOJIUaAmFe8IXmezq8ZC3uS9/xXYJ8tQEjAlyzUFP1VEEfU48xBqWOq92omu9/sCSzD/+O6EDN/t8DnP1RyE8WHXeaquElSrAkNbqJDHDJDH5zTxvEbnAqyWrxNEpZi4kXGTyY3blGqL5mtTLhu8yHFJ49uLQYDxysqM7f0jfUzg94k+UK+v0IsBHjZNb67K9Q32SVcJB9jeoN8jx7x7JQ0dKD51zhjTUHZo+Bk9SFSTCZ7sIQw5XDGFAMyBY+oz+ndlhtW5LkTVkerTNt6MtrOEHS2g+Ly+iaNADmMmw0km5J5YhUFmMVf4HpX+iienlR/eFx2eFuHRrpVgg85AW52dOFJpvpmFygQUi85+pPZZEq90hVLQq9ByrDUexq1mUYcRaj6rFU3F9zfDY/wuImPZwi2dT4gxsYUnZ1jHcdPCgKfGQvduQyfkAAnVBdYLTIhHsLN74RfHObWyS6pIDg9wbyRZ6wWz2WlCDtn+5dlzRnsV9m4CEigAJh4wcHjAzCNpf8/GTdSuGpumBOV9+ig9X9PmzEaHiOHu6usm8izuqLfaqQX+DTRnWmn/23VLWUAxRgYhnLY4EjgW1BypVSR4kEcJ7MyP9I7H7P6Jh4bm3bgG/QnTuJ/5aOpjp7+grLzkjDItOqzcR1oAUc0TYkIl35kCmWxw0hSQDKvNC/63COCYzfpo15aF0NPlT3Snu5jHxItKMoJJuGphCnac5oiB4/egMGDCyg9EdKfc93wEJrUVQwzmwDzX9GL+cMzcss49W1yRVCeK/nUN32sXxLFPrLCINoqgWXCFqHGCkGXBPUM12GPbPVSj6SucmbuSbEcIow4aGCjUWMjHw8aHk7bWeemXI8qB02um8Zh9+vPoHylm8wFH585gT4y8PoRZLvd+y0HydkJx6o2gXU3W1Lm1nN5XUYlts+JaDguds/0gEIxQdVvqMINVrnWZKKYJciTP6WTeVCHAuHXhiOBrXV2ddAIVsUyUyi4hbYJtJrKDMhr4a/NecTo1L1JH9fwEWTWcPaqkmbH71Yjh0f+TCRRVPVlxEIXV/XEJ4PDo9/QL58nswTUYdmv X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 07:18:21.2071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2432da12-e688-4ca1-2be0-08dcbcfa7199 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8011 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea When SHAMPO is used, a receive queue currently almost always leaks one page on shutdown. A page has MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (8) headers. These headers are tracked in the SHAMPO bitmap. Each page is released when the last header index in the group is processed. During header allocation, there can be leftovers from a page that will be used in a subsequent allocation. This is normally fine, except for the following scenario (simplified a bit): 1) Allocate N new page fragments, showing only the relevant last 4 fragments: 0: new page 1: new page 2: new page 3: new page 4: page from previous allocation 5: page from previous allocation 6: page from previous allocation 7: page from previous allocation 2) NAPI processes header indices 4-7 because they are the oldest allocated. Bit 7 will be set to 0. 3) Receive queue shutdown occurs. All the remaining bits are being iterated on to release the pages. But the page assigned to header indices 0-3 will not be freed due to what happened in step 2. This patch fixes the issue by making sure that on allocation, header fragments are always allocated in groups of MLX5E_SHAMPO_WQ_HEADER_PER_PAGE so that there is never a partial page left over between allocations. A more appropriate fix would be a refactoring of mlx5e_alloc_rx_hd_mpwqe() and mlx5e_build_shampo_hd_umr(). But this refactoring is too big for net. It will be targeted for net-next. Fixes: e839ac9a89cb ("net/mlx5e: SHAMPO, Simplify header page release in teardown") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 225da8d691fc..23aa555ca0ae 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -735,6 +735,7 @@ static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq) ksm_entries = bitmap_find_window(shampo->bitmap, shampo->hd_per_wqe, shampo->hd_per_wq, shampo->pi); + ksm_entries = ALIGN_DOWN(ksm_entries, MLX5E_SHAMPO_WQ_HEADER_PER_PAGE); if (!ksm_entries) return 0; From patchwork Thu Aug 15 07:16:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13764452 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2084.outbound.protection.outlook.com [40.107.236.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 170D215CD52 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 2/4] net/mlx5e: SHAMPO, Release in progress headers Date: Thu, 15 Aug 2024 10:16:09 +0300 Message-ID: <20240815071611.2211873-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815071611.2211873-1-tariqt@nvidia.com> References: <20240815071611.2211873-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992C:EE_|DM6PR12MB4154:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a67dbe1-1bda-4db2-1cf4-08dcbcfa7e84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: texUlLMeTL+CEI+RxbG90hgvBdoLy8uJqPD767zpWrmZGOIDQ5dlqH4UPida0eivacAyuDwUKPZwhi4fyyMAdrQjEJI702jBxntdEDWdCOEXRRG6PBaR85eiqvZ0eF6y2G4Ka8vl7OsBe8onoXS7zISEdmofq2A/MfkTwleFrL4NFdD5l3l3R/3jBkW89kPiVobdLNNQ+/4pQh7Kt0zEIQFoD3T6O06SfqMlnNrYyewQSkCWSesojDfFXlYgPWn6FwcUfSiOaoox1+/yMSPg20fDrmNFu+TTdUIQdJRxkfNbrfaKRmoM7u2wGU3bsKnqqg5Ysd+WI5SGZWLdaqU71HJe5q/efzu0vwhKrRHn5pHuzcFncabvIQRqm5jpNSMW1VddgFNqaNT9bUVj73jD3zISgSEsuLL1KG67L3ddDX2XQOWp64XTq56kbsW1Asa4v5HbbekZj27H3LgrqMqiLoR8wfgc6RjYBsgAoNSMJNr2Yy+DHx2KaNCX/JBSRbK9z0ewjVZqJxxGbA5f8kcRCSBPLN+kvg1Ze1dwU0MVKIx22A3MqEIWcEigYY44YHdyD+c40Nc6HGWJ/9+OpmTp4PqR8j8zo+spyup7p69lg2hJkqs1XuJuVngacmjk5XuXtGl+mz3wMhYSEHLXObox7WLrNs1wppvjphywuKOpycAg710F+r1ijRAsq8HsqtNL6ir6zjMNgLBTCnGBdDUhEgJvw8HuAh96yxxNKfcuowaaH3Of7GmTyK0pX+kMloK6UT7s6o9sRjd+IycDlf3iRlpCp2GVsO7uaxbW71+FQRl8YxGP016TDFReH6HVGVSexsKY1DFMRpYzTLeITUsPEslWZ5is8oM/VyqVGSgZjtA6i07yPUWBurK42PabgS0iWJICIwZd4+L3Qu5xbenJkCNBuEPU2RxEsY0HeJ5xh1qvdh4asn7mYG1u0Z7/sPWzA6TgrLz43FUYy+X9OY0t0e/4PdnURjjHhLBj8F+iwp8dX8XtJSAD2k/wV2cVEIl5DXlMf2pr3GxOtNuWD1I5SkBlb72GqFDTtoAn2sRI8yjSp8MhKDP08KxH3+dtiIms1Q7/hMfxf7jboUUs/j9n2uNDnxdesT+QI1uxe9gj8GCvjvc45Ii0rHKdbzHJHri57IyMl5I5YoKyDulKnI2v9yCRXaEee23TUBr8mNsWi1CBU5gYYg+iDOYQa5ENWy0kJ+uBq8obS2pMrzNSZdML/egLIO+O3OfXSXgn/rCrb49YCh/O6LFs4c55W1H4agCGAo+sV8RXPoh4SeZvGFH7WDK+65UboHdhWqW705UWREErAM+bLK08gcTw2mqsCEdZr+CaqPeZnTSzMPnWl+f+N5zbjE6aBp/qe5o+2EBaK2HyyM0d3Z+fKsOJevryGmLCYz3u5yqdiOF6sAoJMjSAlBPILguY1NmRetIqymi3kgs41M2qAP0lkzyxlHuLn5PI X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 07:18:42.8326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a67dbe1-1bda-4db2-1cf4-08dcbcfa7e84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4154 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea The change in the fixes tag cleaned up too much: it removed the part that was releasing header pages that were posted via UMR but haven't been acknowledged yet on the ICOSQ. This patch corrects this omission by setting the bits between pi and ci to on when shutting down a queue with SHAMPO. To be consistent with the Striding RQ code, this action is done in mlx5e_free_rx_missing_descs(). Fixes: e839ac9a89cb ("net/mlx5e: SHAMPO, Simplify header page release in teardown") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 8 ++++++ .../net/ethernet/mellanox/mlx5/core/en_rx.c | 25 +++++++++++-------- 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index bb5da42edc23..d9e241423bc5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -998,6 +998,7 @@ void mlx5e_build_ptys2ethtool_map(void); bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, enum mlx5e_mpwrq_umr_mode umr_mode); +void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 5df904639b0c..583fa24a7ae9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1236,6 +1236,14 @@ void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq) rq->mpwqe.actual_wq_head = wq->head; rq->mpwqe.umr_in_progress = 0; rq->mpwqe.umr_completed = 0; + + if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { + struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; + u16 len; + + len = (shampo->pi - shampo->ci) & shampo->hd_per_wq; + mlx5e_shampo_fill_umr(rq, len); + } } void mlx5e_free_rx_descs(struct mlx5e_rq *rq) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 23aa555ca0ae..de9d01036c28 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -963,26 +963,31 @@ void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq) sq->cc = sqcc; } -static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, - struct mlx5e_icosq *sq) +void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len) { - struct mlx5e_channel *c = container_of(sq, struct mlx5e_channel, icosq); - struct mlx5e_shampo_hd *shampo; - /* assume 1:1 relationship between RQ and icosq */ - struct mlx5e_rq *rq = &c->rq; - int end, from, len = umr.len; + struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; + int end, from, full_len = len; - shampo = rq->mpwqe.shampo; end = shampo->hd_per_wq; from = shampo->ci; - if (from + len > shampo->hd_per_wq) { + if (from + len > end) { len -= end - from; bitmap_set(shampo->bitmap, from, end - from); from = 0; } bitmap_set(shampo->bitmap, from, len); - shampo->ci = (shampo->ci + umr.len) & (shampo->hd_per_wq - 1); + shampo->ci = (shampo->ci + full_len) & (shampo->hd_per_wq - 1); +} + +static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, + struct mlx5e_icosq *sq) +{ + struct mlx5e_channel *c = container_of(sq, struct mlx5e_channel, icosq); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net 3/4] net/mlx5e: XPS, Fix oversight of Multi-PF Netdev changes Date: Thu, 15 Aug 2024 10:16:10 +0300 Message-ID: <20240815071611.2211873-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815071611.2211873-1-tariqt@nvidia.com> References: <20240815071611.2211873-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|SJ1PR12MB6364:EE_ X-MS-Office365-Filtering-Correlation-Id: 03e54ef7-031c-4e98-5e79-08dcbcfa751e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: EBZWfZix1JXaUfPpW0+OBUa4ApSA5DyI1nxKqp4nuktyqNtu+F/D+Ycq2Wmhw5h9etCWE5/S8OG1EG2A7O5mxLjCXGF3op9vIk38Br+z1apUIs5ujJXMf45KUKH3/xJOKtz5fVfrp8CjIgmaEonR1erhSfYNw4tP9Lm6wsR4S2OhkoZd1wMAblnKDLVikRw/zJYN8hfdQjOPM8nplul6vz6+5CumJoCmvoqU7QJn26wUOLXJy18AyiA0EKfmvFCeeTre/6/On4o69wxXWK7LLRl/h8Pfp28mqtxa9Xq0CVo0hOPgKaMKIz5+nOYrfRTtxeHYkptPTqBhOEpdi8SLZTA6NkQ9TbbMglepJlsWNVbHT+gOwPxGZMyO6Qo1kLeJoTvHw0eECLtF4PGiNA5Jm0iN+Pn3rMLzHxDY0/7JVfsuQPT9M0SYgnsbR7cH53cwXu27jhPEhaCEiaGMR+CS2bZX1RqWRfSu/ihy3hI+Ksj+Mw4zP6ugM72IAGxg0+X46oSVsr8owIe4OLdURF+W4UtxYIGaP0QZ00z7A4OOavPSXZr7TkunozGwpr+5lQ3o2GQmgU9ybazt2T0G6pu7DWqsKcikfPZwEqN26bPE3rlw/wWEKKW89gLxOzCiufnRGcNSjE//0e+Gr5IwEyLcKpBA1XQSTjM3AjluukfMu8rF7XLDEZZh09lIY6vs2UdURoh4XZfTZ/O7RnBabqxKqYnBoxoPc4kj1DYLYfK0gU5FVDJi7Hex3vy6pbI7a56qGw6FwKW0UNS91dOFcYDzSQ9liPKa9kQmTuqx0LionNHBxL8khn6YAlvvHQmp+AGlyqT3hJoHWl4KiUUc6ZFtM/kXouDHbhu9h0lPkmk0PI8nCMV8+ZfsY6I3/ePLMzqqXMznNgQ4TTHsDknsBExd7IVXEgGsy388V5uIbW/rB489j+N7dVUFd3oru9VV1tM8xhfqd5LHoA8AICzs2FyhLRytLfwWC1HfuS7Y4c6rRJgilHnxIfFTr2k+O2pSNONV8unKOP2Rw0be1KG0A8xsfnqz/JW8VKSafElSPoza1DHYsnN9VpFzXN80qF06s/8ctqnswWEKG9RPMAgEkq2PNODMPJvIDGJHMqo+ALLhyZUDNdAji9VXpIZZ0PRPbx0xSb56oRbjHhUgEDMgrJXPWCNfeqHE3bWrHh8M7Z5DWA2JKvale68pNjN85C6hTWRb2xsKw2vvBXlTwLdlocSBvo/5SkXChTcBp6S3WaX7BC01apPYxHG1+QxXivoiCr58fm1kaJXB2XHHy1Oy9r5IkVq4tHXTI7aht6Xd/t1BxYshHDyI1XNz9lpPrkAjdwGw0n411eZSLc8p5nMJaVYe0qHHezqnTV7ZEy51Zv7xXuL0Eyu3YJo0kR36hkbv2XE274qQ2DkgSjRidmRcfOLXUVYTPrpeO4iKwqFqPwFr86bBTXpb3RqSIZit1cjlIBdo X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 07:18:27.0975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03e54ef7-031c-4e98-5e79-08dcbcfa751e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6364 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran The offending commit overlooked the Multi-PF Netdev changes. Revert mlx5e_set_default_xps_cpumasks to incorporate Multi-PF Netdev changes. Fixes: bcee093751f8 ("net/mlx5e: Modifying channels number and updating TX queues") Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 583fa24a7ae9..16b67c457b60 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3028,15 +3028,18 @@ int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, struct mlx5e_params *params) { - struct mlx5_core_dev *mdev = priv->mdev; - int num_comp_vectors, ix, irq; - - num_comp_vectors = mlx5_comp_vectors_max(mdev); + int ix; for (ix = 0; ix < params->num_channels; ix++) { + int num_comp_vectors, irq, vec_ix; + struct mlx5_core_dev *mdev; + + mdev = mlx5_sd_ch_ix_get_dev(priv->mdev, ix); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Patrisious Haddad , Tariq Toukan Subject: [PATCH net 4/4] net/mlx5: Fix IPsec RoCE MPV trace call Date: Thu, 15 Aug 2024 10:16:11 +0300 Message-ID: <20240815071611.2211873-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815071611.2211873-1-tariqt@nvidia.com> References: <20240815071611.2211873-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AEA:EE_|SA3PR12MB8024:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b45cb3d-5dcc-45f1-3ce9-08dcbcfa777e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: cqUEwxkWAcqxjHZ9vXI4m/OBrv3eLwp8GwqwGI2SVrgqxeTilrUbzKQktt0yzRfme92RxSKs14SiPPZs+KttcrWKX+EfzTMcEjggsJmUPln2CYVIAIz1MVky+YUIQrc41F369mCd1dfQFvWDILVqxtp+CmtOaEU5Fnan8kyMCWsbAwciW1cUfd5W6o/qIlV1sRaBbtgUOUY8cSXKgMHySU6CzcojK8RAw6FnMMsVywhkXkF8MI8dD1iiE3XC9AOpW6KSQZVwiud8z8baQgH/iCSZTr/hBmTwtqq9glajzj+XNQFRW3IJG7nbpoix0dCMIOFfyIQxPp5dGMXXz1WmwK3zIMamnAkrm7AWvQ3x5RPlxyn8dFlXKbnD4pBijOkVmbetOpfa5SLo58Yaqx8IexhmU0FY27NjbNEE4X/8NgpJWmAFuxKFS8J8FMVaC/vF2QYZJU8XeOJ7h5jqqSedIe9sdHBYoj5wwuXi5j9ptzgnwzKuk48tiOYsy0sqzuvRlcbbCkrYaFleP6p9ODu4l7bqoRFPA+A7gVnt1HTpuTjdDJMph/D4pPCJxqzu5cxkwWRr/u7+QkYFg3tEIr9xtnO0ARoVzDm9HTtD7llkJrsOSeDgnMoUXN+pkkSaLEKEmQzTfGs+dcPcC19yXQUEUkKs06eqHIg/LucAtAVGeyHPM/olAC12cY9dzJv6ukQJLGtIfRnQu4ajV83iBRvtZ42eeh0R+yzDtcCuyb573wKf2ObsNWQ27IFT7EcsEQiNR6ru1xMtew0prZRSRk80/+UcKS1AV2NL2CpxMhQYD4BEg8O3t6orJaG39/WB2gE2varY3o0r//u4m5AdEZB7QwW9bp4IuwMKslVPOc69/DqieL7WZSLYdizPfT9K6Hcx/H7ZEbgSooFxBZ9IL+AeqjJbRLIp9CZ9TRovywpC6r2pPTyFbOKMJSLQ/Xl7VH9SQF86LBxiRjgXxvQ/AvdPlyYNv0Lswx33S9t2UtKS9WV+3FctGa77HEX5XjPVySVDQM6o/onE6EHElIkk1PGmOHDryXwz+k/ppSJhkFsdVekBpobZqSI/VQXvP9M7nFJd6Sg03hFOwtQ9t3h1pr/nf04cmcNBbj2Q5bifZyHuDfwVZVEzzeWCWaicqy/H5hjSbXLWguWI4Af4CKNhoTFdg0U+VNzJ3EKw+rEDgMySBxCnf6fwkXPtGTJwlWeLtso6ClKK4hAvjgQPKz99+KNFZ10NKjuEHLLpqw6MgnT2y8ZlTuWsLJkQ36oQGXHQb+GuSjC5hTFx6IQ21yOxXxCMZfqeeUERL7qEn1p2t8eTD4bDVlZJwQSCq7hGoNPvwANGj3k0Vc/vghNHd6sdWdaVgz1eI+JbnxPqCiT1HFFOA6Zcb3vhtVYLmg39VX+7Z84/wWELDuSxBU75/nTKA4EBFnQzNtiqX743mY1OgauUj1BjR6n1jWVp3pYC7gBASC4S X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 07:18:31.0969 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b45cb3d-5dcc-45f1-3ce9-08dcbcfa777e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AEA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8024 X-Patchwork-Delegate: kuba@kernel.org From: Patrisious Haddad Prevent the call trace below from happening, by not allowing IPsec creation over a slave, if master device doesn't support IPsec. WARNING: CPU: 44 PID: 16136 at kernel/locking/rwsem.c:240 down_read+0x75/0x94 Modules linked in: esp4_offload esp4 act_mirred act_vlan cls_flower sch_ingress mlx5_vdpa vringh vhost_iotlb vdpa mst_pciconf(OE) nfsv3 nfs_acl nfs lockd grace fscache netfs xt_CHECKSUM xt_MASQUERADE xt_conntrack ipt_REJECT nf_reject_ipv4 nft_compat nft_counter nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 rfkill cuse fuse rpcrdma sunrpc rdma_ucm ib_srpt ib_isert iscsi_target_mod target_core_mod ib_umad ib_iser libiscsi scsi_transport_iscsi rdma_cm ib_ipoib iw_cm ib_cm ipmi_ssif intel_rapl_msr intel_rapl_common amd64_edac edac_mce_amd kvm_amd kvm irqbypass crct10dif_pclmul crc32_pclmul mlx5_ib ghash_clmulni_intel sha1_ssse3 dell_smbios ib_uverbs aesni_intel crypto_simd dcdbas wmi_bmof dell_wmi_descriptor cryptd pcspkr ib_core acpi_ipmi sp5100_tco ccp i2c_piix4 ipmi_si ptdma k10temp ipmi_devintf ipmi_msghandler acpi_power_meter acpi_cpufreq ext4 mbcache jbd2 sd_mod t10_pi sg mgag200 drm_kms_helper syscopyarea sysfillrect mlx5_core sysimgblt fb_sys_fops cec ahci libahci mlxfw drm pci_hyperv_intf libata tg3 sha256_ssse3 tls megaraid_sas i2c_algo_bit psample wmi dm_mirror dm_region_hash dm_log dm_mod [last unloaded: mst_pci] CPU: 44 PID: 16136 Comm: kworker/44:3 Kdump: loaded Tainted: GOE 5.15.0-20240509.el8uek.uek7_u3_update_v6.6_ipsec_bf.x86_64 #2 Hardware name: Dell Inc. PowerEdge R7525/074H08, BIOS 2.0.3 01/15/2021 Workqueue: events xfrm_state_gc_task RIP: 0010:down_read+0x75/0x94 Code: 00 48 8b 45 08 65 48 8b 14 25 80 fc 01 00 83 e0 02 48 09 d0 48 83 c8 01 48 89 45 08 5d 31 c0 89 c2 89 c6 89 c7 e9 cb 88 3b 00 <0f> 0b 48 8b 45 08 a8 01 74 b2 a8 02 75 ae 48 89 c2 48 83 ca 02 f0 RSP: 0018:ffffb26387773da8 EFLAGS: 00010282 RAX: 0000000000000000 RBX: ffffa08b658af900 RCX: 0000000000000001 RDX: 0000000000000000 RSI: ff886bc5e1366f2f RDI: 0000000000000000 RBP: ffffa08b658af940 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: ffffa0a9bfb31540 R13: ffffa0a9bfb37900 R14: 0000000000000000 R15: ffffa0a9bfb37905 FS: 0000000000000000(0000) GS:ffffa0a9bfb00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000055a45ed814e8 CR3: 000000109038a000 CR4: 0000000000350ee0 Call Trace: ? show_trace_log_lvl+0x1d6/0x2f9 ? show_trace_log_lvl+0x1d6/0x2f9 ? mlx5_devcom_for_each_peer_begin+0x29/0x60 [mlx5_core] ? down_read+0x75/0x94 ? __warn+0x80/0x113 ? down_read+0x75/0x94 ? report_bug+0xa4/0x11d ? handle_bug+0x35/0x8b ? exc_invalid_op+0x14/0x75 ? asm_exc_invalid_op+0x16/0x1b ? down_read+0x75/0x94 ? down_read+0xe/0x94 mlx5_devcom_for_each_peer_begin+0x29/0x60 [mlx5_core] mlx5_ipsec_fs_roce_tx_destroy+0xb1/0x130 [mlx5_core] tx_destroy+0x1b/0xc0 [mlx5_core] tx_ft_put+0x53/0xc0 [mlx5_core] mlx5e_xfrm_free_state+0x45/0x90 [mlx5_core] ___xfrm_state_destroy+0x10f/0x1a2 xfrm_state_gc_task+0x81/0xa9 process_one_work+0x1f1/0x3c6 worker_thread+0x53/0x3e4 ? process_one_work.cold+0x46/0x3c kthread+0x127/0x144 ? set_kthread_struct+0x60/0x52 ret_from_fork+0x22/0x2d ---[ end trace 5ef7896144d398e1 ]--- Fixes: dfbd229abeee ("net/mlx5: Configure IPsec steering for egress RoCEv2 MPV traffic") Reviewed-by: Leon Romanovsky Signed-off-by: Patrisious Haddad Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lib/ipsec_fs_roce.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/ipsec_fs_roce.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/ipsec_fs_roce.c index 234cd00f71a1..b7d4b1a2baf2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/ipsec_fs_roce.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/ipsec_fs_roce.c @@ -386,7 +386,8 @@ static int ipsec_fs_roce_tx_mpv_create(struct mlx5_core_dev *mdev, return -EOPNOTSUPP; peer_priv = mlx5_devcom_get_next_peer_data(*ipsec_roce->devcom, &tmp); - if (!peer_priv) { + if (!peer_priv || !peer_priv->ipsec) { + mlx5_core_err(mdev, "IPsec not supported on master device\n"); err = -EOPNOTSUPP; goto release_peer; } @@ -455,7 +456,8 @@ static int ipsec_fs_roce_rx_mpv_create(struct mlx5_core_dev *mdev, return -EOPNOTSUPP; peer_priv = mlx5_devcom_get_next_peer_data(*ipsec_roce->devcom, &tmp); - if (!peer_priv) { + if (!peer_priv || !peer_priv->ipsec) { + mlx5_core_err(mdev, "IPsec not supported on master device\n"); err = -EOPNOTSUPP; goto release_peer; }