From patchwork Fri Aug 16 18:25:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13766761 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE60B2F43 for ; Fri, 16 Aug 2024 18:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723832767; cv=none; b=d9ylJ7dcV64xIjSslQzdFkwhjS7JFSacYETkXn/ON4QSy/7rvxYPM24EuNWICrrBasnzjuK8kxBl0P3OIEm0dgjbUdMSJR7mXldI3IJUz9MjJ/2OfqQJkHk09q80geZ8bU0eBfir11sOGI4m9yIQis1rT5BJZjpseKWQI6m0N28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723832767; c=relaxed/simple; bh=UpzadmpD5JAWm7JbXK79TiN9tBl/ICyRxDFsukaWQOQ=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=aJXjyd0GGomayfJouvkPPc2Mxk18LzaoubKKCShrvfxMLuZMKn6u6AsBDgfXReRqa3kapcxhUCyFQxZ6juC/Gx9YHl7xcRGS0Kt1CG9+XSraGi7ww31b8UWuvKp5WQrB+tGyc48cXHv4IyMOq3avHO6gevR3HrrUkVz6JACmSSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=wJtZHI5c; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wJtZHI5c" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6b3825748c2so8791727b3.2 for ; Fri, 16 Aug 2024 11:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1723832764; x=1724437564; darn=vger.kernel.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=vHU41TdFfuYSxHFsH0hBT59EzOX4pM0RwY0qoH1omnY=; b=wJtZHI5cZJeo4CjdwaXHO8G5sGwfDwMwfrQi0ox/oO6twFWrMLVtIwnftmIOZpgsRK oUCCAOriz1X289HRNoQrbOZWLIFNZ38vHGiukv+hzzCBUyx3p6wStRh6R92YkAHlHNfs FS/mzOVSYePmhLfr8Lo+gTXt9Ze+zO4kkZyzRQz0sFbrPkgPjiCFoN4bwrjC2dC+Ex7c NTODFMpxcRWxkzgOhSGIdya18gZElmtPY5A3oN+wQ+W7udT/evRjD+vbdKmeicxoJWVH eMnwLpN/IakUOLWDpoXRw5/dBfA/8b9CsIfNpWfPja9wf6e4hjBcQMrIWaXgF8hCJqi/ /LBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723832764; x=1724437564; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=vHU41TdFfuYSxHFsH0hBT59EzOX4pM0RwY0qoH1omnY=; b=iBi7GYzHmsefWJAyixgO8/BvnHqXZxOpkCLMGbLFXBWz/1Dr7D2rpJdFPbZAqvDk/W HQbJ1pf991fRIiDLG+vPF4UuXLz9ZUt6zWhCI78DdE7M5glALT9i470jFNiBESgE4H6a ttOO6AlTUgw0yMM5yprTTCdqS8SPWPEZOqkBbpBTeqFpBvuI/Kq3nA/Wf9oAZi9M7IZ7 XlrO+RdWxeDRJmzvwB6VcHyHY32rrqzOCh42EYY8mVwr/UubqqNwWKXxHB8V08uPUsBP GpE4aNiPg/1R+scTCSG/RW/srwgqvAq6dPjJwKSqQ5DJdEE5OaYlKkG2YLHOZWg+ZkJW VK/w== X-Forwarded-Encrypted: i=1; AJvYcCW35vTUoWlOLQMzhoju1qTObZUewAyEFIUGgWJFJhl74ENREiuXAk6yvxVIgUGgbmy0A1owcnxttvHtc7fPBDMwWPOj X-Gm-Message-State: AOJu0Yy3KmB7PxRCsAu3XHZXIFtJ8wWgthpz2F/CrizC/yrncfiewYDn iymQ4HYsbyQwZyhSbIYtYd/kd8NRXf2COBQ6M7xjbm56szBw0bTK60p1KnvocTzq/PCzvU3s88c B9FdESSH/WA== X-Google-Smtp-Source: AGHT+IEJc+hFQIAnQCVr0tRCdxFBw2gcFs1n3D9qIS2qPVf+9CWDN63ejNRhGhy2SGZLXx61jxNCjlGe4UDROQ== X-Received: from loggerhead.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:29a]) (user=jmattson job=sendgmr) by 2002:a81:a253:0:b0:650:a16c:91ac with SMTP id 00721157ae682-6b1bd17dbaemr975007b3.8.1723832763870; Fri, 16 Aug 2024 11:26:03 -0700 (PDT) Date: Fri, 16 Aug 2024 11:25:21 -0700 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.46.0.184.g6999bdac58-goog Message-ID: <20240816182533.2478415-1-jmattson@google.com> Subject: [PATCH v2 1/2] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Daniel Sneddon , Kai Huang , Sandipan Das , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Jim Mattson , Venkatesh Srinivas AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[bit 30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dd4682857c12..e5bcb428dcf9 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ From patchwork Fri Aug 16 18:25:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13766762 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 963861C379E for ; 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Fri, 16 Aug 2024 11:26:05 -0700 (PDT) Date: Fri, 16 Aug 2024 11:25:22 -0700 In-Reply-To: <20240816182533.2478415-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240816182533.2478415-1-jmattson@google.com> X-Mailer: git-send-email 2.46.0.184.g6999bdac58-goog Message-ID: <20240816182533.2478415-2-jmattson@google.com> Subject: [PATCH v2 2/2] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Daniel Sneddon , Kai Huang , Sandipan Das , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Jim Mattson , Venkatesh Srinivas From Intel's documention [1], "CPUID.(EAX=07H,ECX=0):EDX[26] enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB)." Further, from [2], "Software that executed before the IBPB command cannot control the predicted targets of indirect branches (4) executed after the command on the same logical processor," where footnote 4 reads, "Note that indirect branches include near call indirect, near jump indirect and near return instructions. Because it includes near returns, it follows that **RSB entries created before an IBPB command cannot control the predicted targets of returns executed after the command on the same logical processor.**" [emphasis mine] On the other hand, AMD's IBPB "may not prevent return branch predictions from being specified by pre-IBPB branch targets" [3]. However, some AMD processors have an "enhanced IBPB" [terminology mine] which does clear the return address predictor. This feature is enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4]. Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID accordingly. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html [2] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-execution-side-channel-mitigations.html#Footnotes [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.html [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as derived in generic x86 code") Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Reviewed-by: Venkatesh Srinivas --- v2: Use IBPB_RET to identify semantic equality (Venkatesh) arch/x86/kvm/cpuid.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 2617be544480..044bdc9e938b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); - if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) + if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && + boot_cpu_has(X86_FEATURE_AMD_IBPB) && + boot_cpu_has(X86_FEATURE_AMD_IBRS)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); if (boot_cpu_has(X86_FEATURE_STIBP)) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); @@ -759,8 +761,10 @@ void kvm_set_cpu_caps(void) * arch/x86/kernel/cpu/bugs.c is kind enough to * record that in cpufeatures so use them. */ - if (boot_cpu_has(X86_FEATURE_IBPB)) + if (boot_cpu_has(X86_FEATURE_IBPB)) { kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); + kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); + } if (boot_cpu_has(X86_FEATURE_IBRS)) kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); if (boot_cpu_has(X86_FEATURE_STIBP))