From patchwork Thu Aug 22 17:09:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 13773964 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B16161CEAAA; Thu, 22 Aug 2024 17:10:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346612; cv=none; b=LLjCUGfJEaZNUIflK+9yDF0MH/v/WaL5mT0Yob1fyg/DjZBkgJk2/dmIVvq3/jHaTCnZLXxvAjR2wFJHVM5/QBqg8LS9FvJWM3NVdcl1DKpotVOJYgFDHMrSyx4k1xDfVwgtkQIg/cv2MGI9Yi44hcDS/hSMBLx5J1ray9uZjAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346612; c=relaxed/simple; bh=X0W6f9O8bYoUbFIXpqrbKRr4+wfpl8fCRYJ/t85ZcTw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dGNrzz212N9UWjnsVomjqIAQ9JzOSE/fTdfrYbxJ7DnSoYnYefkJzjNCGwZpFpUtt8XX0g2pGr1iccYzXJvh35tDiBk2blU/cgJ3qXK/G2lDvUvDoF4dcepj0PdSgVWSxgGaUpZQ5o27FIJTT12OlCWgR6vUWG6Xy3mzrAdZEtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F17BAFEC; Thu, 22 Aug 2024 10:10:35 -0700 (PDT) Received: from e130802.cambridge.arm.com (e130802.arm.com [10.1.37.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4E98E3F58B; Thu, 22 Aug 2024 10:10:06 -0700 (PDT) From: Abdellatif El Khlifi To: mathieu.poirier@linaro.org Cc: Adam.Johnston@arm.com, Hugues.KambaMpiana@arm.com, Drew.Reed@arm.com, abdellatif.elkhlifi@arm.com, andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org, sudeep.holla@arm.com, robin.murphy@arm.com Subject: [PATCH v2 1/5] dt-bindings: remoteproc: sse710: Add the External Systems remote processors Date: Thu, 22 Aug 2024 18:09:47 +0100 Message-Id: <20240822170951.339492-2-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> References: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add devicetree binding schema for the External Systems remote processors The External Systems remote processors are provided on the Corstone-1000 IoT Reference Design Platform via the SSE-710 subsystem. For more details about the External Systems, please see Corstone SSE-710 subsystem features [1]. [1]: https://developer.arm.com/documentation/102360/0000/Overview-of-Corstone-1000/Corstone-SSE-710-subsystem-features Signed-off-by: Abdellatif El Khlifi --- .../remoteproc/arm,sse710-extsys.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml b/Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml new file mode 100644 index 000000000000..827ba8d962f1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/arm,sse710-extsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SSE-710 External System Remote Processor + +maintainers: + - Abdellatif El Khlifi + - Hugues Kamba Mpiana + +description: | + SSE-710 is an heterogeneous subsystem supporting up to two remote + processors aka the External Systems. + +properties: + compatible: + enum: + - arm,sse710-extsys + + firmware-name: + description: + The default name of the firmware to load to the remote processor. + + '#extsys-id': + description: + The External System ID. + enum: [0, 1] + + mbox-names: + items: + - const: txes0 + - const: rxes0 + + mboxes: + description: + The list of Message Handling Unit (MHU) channels used for bidirectional + communication. This property is only required if the virtio-based Rpmsg + messaging bus is used. For more details see the Arm MHUv2 Mailbox + Controller at devicetree/bindings/mailbox/arm,mhuv2.yaml + + minItems: 2 + maxItems: 2 + + memory-region: + description: + If present, a phandle for a reserved memory area that used for vdev + buffer, resource table, vring region and others used by the remote + processor. + minItems: 2 + maxItems: 32 + +required: + - compatible + - firmware-name + - '#extsys-id' + +additionalProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + extsys0_vring0: vdev0vring0@82001000 { + reg = <0 0x82001000 0 0x8000>; + no-map; + }; + + extsys0_vring1: vdev0vring1@82009000 { + reg = <0 0x82009000 0 0x8000>; + no-map; + }; + }; + + syscon@1a010000 { + compatible = "arm,sse710-host-base-sysctrl", "simple-mfd", "syscon"; + reg = <0x1a010000 0x1000>; + + extsys0 { + compatible = "arm,sse710-extsys"; + #extsys-id = <0>; + firmware-name = "es_flashfw.elf"; + mbox-names = "txes0", "rxes0"; + mboxes = <&mhu0_hes0 0 1>, <&mhu0_es0h 0 1>; + memory-region = <&extsys0_vring0>, <&extsys0_vring1>; + }; + }; From patchwork Thu Aug 22 17:09:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 13773965 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C87E1CEAC5; Thu, 22 Aug 2024 17:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346615; cv=none; b=gJ7Dtj5Ya/OYOaRsXSNBpQOcydaEqFAq2uVwHPs9DTLvamdaFVFkuCx5FiF7RfRBB5ZvEo6hlbtwe/Wf4kEBswxlI0U8n+sBAqZDeH35tFQkE09WB8G+k9dZ6XbH6sd2BEUQ5Ni5vtQo6fp9ooE+j+QL2PhzwLmTSIBiVkU4r/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346615; c=relaxed/simple; bh=Wp0A8wfh3Dmu197tkkOnI7V2/dtUt1/KcRgBzxBMvMA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hN3+EF3vrKYIEuEPlxSkkLR0YSBca98zKS5Hu+wjVm84WKPNFilvilIrdylnDwGWReDZdIj2oEwMQSfJmcUI/uOM+R8oJLx6s4K3TI4Q6wyBV6ZsRMrf2pu/UuuPpb+RT5ydz39s1VX/rT3crVV7hW0+I1w3jRVxxtyA7MB1YEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0EB53DA7; Thu, 22 Aug 2024 10:10:39 -0700 (PDT) Received: from e130802.cambridge.arm.com (e130802.arm.com [10.1.37.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F43C3F86F; Thu, 22 Aug 2024 10:10:10 -0700 (PDT) From: Abdellatif El Khlifi To: mathieu.poirier@linaro.org Cc: Adam.Johnston@arm.com, Hugues.KambaMpiana@arm.com, Drew.Reed@arm.com, abdellatif.elkhlifi@arm.com, andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org, sudeep.holla@arm.com, robin.murphy@arm.com Subject: [PATCH v2 2/5] dt-bindings: arm: sse710: Add Host Base System Control Date: Thu, 22 Aug 2024 18:09:48 +0100 Message-Id: <20240822170951.339492-3-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> References: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add devicetree binding schema for the SSE-710 Host Base System Control SSE-710 is implemented by the Corstone-1000 IoT Reference Design Platform [1]. The Host Base System Control has registers to control the clocks, power, and reset for SSE-710 subsystem [2]. It resides within AONTOP power domain. The registers are mapped under the SSE-710 Host System memory map [3]. [1]: https://developer.arm.com/Processors/Corstone-1000 [2]: https://developer.arm.com/documentation/102342/latest/ [3]: https://developer.arm.com/documentation/102342/0000/Programmers-model/Register-descriptions/Host-Base-System-Control-register-summary Signed-off-by: Abdellatif El Khlifi --- .../arm/arm,sse710-host-base-sysctrl.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml b/Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml new file mode 100644 index 000000000000..e344a73e329d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,sse710-host-base-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SSE-710 Host Base System Control + +maintainers: + - Abdellatif El Khlifi + - Hugues Kamba Mpiana + +description: |+ + The Host Base System Control has registers to control the clocks, power, and + reset for SSE-710 subsystem. It resides within AONTOP power domain. + The registers are mapped under the SSE-710 Host System memory map. + +properties: + compatible: + items: + - enum: + - arm,sse710-host-base-sysctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + +patternProperties: + "^extsys[0-1]$": + description: + SSE-710 subsystem supports up to two External Systems. + $ref: /schemas/remoteproc/arm,sse710-extsys.yaml# + unevaluatedProperties: false + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + syscon@1a010000 { + compatible = "arm,sse710-host-base-sysctrl", "simple-mfd", "syscon"; + reg = <0x1a010000 0x1000>; + + extsys0 { + compatible = "arm,sse710-extsys"; + firmware-name = "es_flashfw.elf"; + #extsys-id = <0>; + mbox-names = "txes0", "rxes0"; + mboxes = <&mhu0_hes0 0 1>, <&mhu0_es0h 0 1>; + memory-region = <&extsys0_vring0>, <&extsys0_vring1>; + }; + }; From patchwork Thu Aug 22 17:09:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 13773966 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B8C7A1CE70F; Thu, 22 Aug 2024 17:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346619; cv=none; b=hFc2JWkw6p9nevXt+arDTGaAYWQsXhHdJxihRdFzG8fu0bknyMuXmINw4ayXX4BJhbHst0wbAJswjiLl0BxWBR7bIxs48maZBG6gRweP4TqpqYnKiu5hlBoJqMcg0s1Tluo8D5c2o3V7Es6J8sIIeA4x0LKnBJuP2HZi653eBSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346619; c=relaxed/simple; bh=SVVDOlU0lPxfHsJW/1DZF2dUeryvrT3UoJyn2d4MUWM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KqGwtzECcR3pDeQzlksBadlZ6TmrgELQNOL3oqQrgrdsXLllgamgko4mBpPzmJlkC/IWgGVKFgn0hzxbIdKBhaIj109P2f7MvvO9qjfDOObxPL0XG4FWBhXbJsVeouPHeySP2H8wyNHK5j9t4MjqsSvxQiPRP+usLTtd9u3Dn/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CC76DA7; Thu, 22 Aug 2024 10:10:43 -0700 (PDT) Received: from e130802.cambridge.arm.com (e130802.arm.com [10.1.37.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5ECA13F58B; Thu, 22 Aug 2024 10:10:13 -0700 (PDT) From: Abdellatif El Khlifi To: mathieu.poirier@linaro.org Cc: Adam.Johnston@arm.com, Hugues.KambaMpiana@arm.com, Drew.Reed@arm.com, abdellatif.elkhlifi@arm.com, andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org, sudeep.holla@arm.com, robin.murphy@arm.com Subject: [PATCH v2 3/5] arm64: dts: corstone1000: Add MHU nodes used by the External System Date: Thu, 22 Aug 2024 18:09:49 +0100 Message-Id: <20240822170951.339492-4-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> References: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add normal world mhu0_hes0 and mhu0_es0h nodes In Corstone-1000 IoT Reference Design Platform, communication between the host (Cortex-A35) running in normal world (EL0 and EL1) and the external system (Cortex-M3) is done with MHU0. MHU0 is a bidirectional communication channel described in the device tree through mhu0_hes0 and mhu0_es0h. Signed-off-by: Abdellatif El Khlifi --- arch/arm64/boot/dts/arm/corstone1000.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index bb9b96fb5314..01c65195ca53 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 OR MIT /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, 2024 Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. * */ @@ -134,6 +134,26 @@ uart1: serial@1a520000 { clock-names = "uartclk", "apb_pclk"; }; + mhu0_hes0: mhu@1b000000 { + compatible = "arm,mhuv2-tx","arm,primecell"; + reg = <0x1b000000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 1>; + }; + + mhu0_es0h: mhu@1b010000 { + compatible = "arm,mhuv2-rx","arm,primecell"; + reg = <0x1b010000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 1>; + }; + mhu_hse1: mailbox@1b820000 { compatible = "arm,mhuv2-tx", "arm,primecell"; reg = <0x1b820000 0x1000>; From patchwork Thu Aug 22 17:09:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 13773967 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 759571CE70F; Thu, 22 Aug 2024 17:10:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346622; cv=none; b=ias62CUB0L1rObovNpGfVsSpNDA+FhxjXXye/uhfvkgbF5xlV0gXJzEiUiKlekUu5CZgzfkf5PVfqMg75ojCjQPsEAUSfELqi/3S5TBHxj4kNMkCp+uK788eJF2rSZuW+ZS3lxqoeZWcpC0a74H0A1aDVKfURjB6iRMPnP71l5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346622; c=relaxed/simple; bh=O3wC87vh8+30SLLrbyihGQV6hC1v8cqmuw/RrrA1X0w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y2Vre6z5+ZwXOppgd1Hi0nNdWwW2DU7aYq4Jb9Ff0GPw+b9tAXAX+/xjk2p4fkDAU01FXjAVjHohZ6sI5Z+DTs7JMbhMO/RVDQ4v/6pyya1jfUI/c0XClj1pUqrp35Ov3h6iUyVRe2YnyuGodMh3YlgfypnedwddXcC6xjPQ/gI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0ECE0DA7; Thu, 22 Aug 2024 10:10:47 -0700 (PDT) Received: from e130802.cambridge.arm.com (e130802.arm.com [10.1.37.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5D3B03F58B; Thu, 22 Aug 2024 10:10:17 -0700 (PDT) From: Abdellatif El Khlifi To: mathieu.poirier@linaro.org Cc: Adam.Johnston@arm.com, Hugues.KambaMpiana@arm.com, Drew.Reed@arm.com, abdellatif.elkhlifi@arm.com, andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org, sudeep.holla@arm.com, robin.murphy@arm.com Subject: [PATCH v2 4/5] arm64: dts: corstone1000: Add External System support Date: Thu, 22 Aug 2024 18:09:50 +0100 Message-Id: <20240822170951.339492-5-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> References: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add extsys0 remoteproc node as a child node of syscon extsys0 describes the Corstone-1000 external system [1] (the remote processor). The host (Cortex-A35) can control the external system through memory mapped registers located in a memory area called the Host Base System Control [2][3]. This area is part of the host memory space. We use syscon to represent the Host Base System Control area and the remoteproc node is a child node. [1]: Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml [2]: https://developer.arm.com/documentation/102342/0000/Programmers-model/Register-descriptions/Host-Base-System-Control-register-summary [3]: Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml Signed-off-by: Abdellatif El Khlifi --- arch/arm64/boot/dts/arm/corstone1000.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 01c65195ca53..17d6638f9ca6 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -103,6 +103,18 @@ soc { interrupt-parent = <&gic>; ranges; + syscon@1a010000 { + compatible = "arm,sse710-host-base-sysctrl", + "simple-mfd", "syscon"; + reg = <0x1a010000 0x1000>; + + extsys0 { + compatible = "arm,sse710-extsys"; + #extsys-id = <0>; + firmware-name = "es_flashfw.elf"; + }; + }; + timer@1a220000 { compatible = "arm,armv7-timer-mem"; reg = <0x1a220000 0x1000>; From patchwork Thu Aug 22 17:09:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdellatif El Khlifi X-Patchwork-Id: 13773968 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F16551CE70F; Thu, 22 Aug 2024 17:10:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346626; cv=none; b=il7HO8ayIin96gSGJDyO89c+nZps9b8n6ZJunDocjuCOvy75qcqkzB1vYVDQHK1mcr4p0OEtNL1Fsmcs49Ro5vho+pa3fTVf7BdIwliJWdlxqlWNZostfISu3olHZs0skZc1/GqZwAM45XtRuPGJle5PJ/MFUrV/QCTskSTK12o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724346626; c=relaxed/simple; bh=tjZBQXiYXB+vLJzPClmFpU6zvsTT+tk8yknUhP4mEP0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XeHolp9VobVnEzbj1ZM1WOA9RcLRK8gRqGGvvLo1po2iVMCk4X1NDi90QdmzGVrHRMtRwTwyQkC9yns2GNB4ocolIgrH5WtXy/2Kvek5g/twDQNuf6ck0jn5IA1MuawqVZsQLDInsOlBIGgAxOSBwnxrkm3Fcm+mKA8rDhGST+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B1A2DA7; Thu, 22 Aug 2024 10:10:50 -0700 (PDT) Received: from e130802.cambridge.arm.com (e130802.arm.com [10.1.37.66]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 407283F58B; Thu, 22 Aug 2024 10:10:21 -0700 (PDT) From: Abdellatif El Khlifi To: mathieu.poirier@linaro.org Cc: Adam.Johnston@arm.com, Hugues.KambaMpiana@arm.com, Drew.Reed@arm.com, abdellatif.elkhlifi@arm.com, andersson@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, liviu.dudau@arm.com, lpieralisi@kernel.org, robh@kernel.org, sudeep.holla@arm.com, robin.murphy@arm.com Subject: [PATCH v2 5/5] remoteproc: arm64: corstone1000: Add the External Systems driver Date: Thu, 22 Aug 2024 18:09:51 +0100 Message-Id: <20240822170951.339492-6-abdellatif.elkhlifi@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> References: <20240822170951.339492-1-abdellatif.elkhlifi@arm.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce remoteproc support for Corstone-1000 external systems The Corstone-1000 IoT Reference Design Platform supports up to two external systems processors. These processors can be switched on or off using their reset registers. For more details, please see the SSE-710 External System Remote Processor binding [1] and the SSE-710 Host Base System Control binding [2]. The reset registers are MMIO mapped registers accessed using regmap. [1]: Documentation/devicetree/bindings/remoteproc/arm,sse710-extsys.yaml [2]: Documentation/devicetree/bindings/arm/arm,sse710-host-base-sysctrl.yaml Signed-off-by: Abdellatif El Khlifi --- drivers/remoteproc/Kconfig | 14 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/corstone1000_rproc.c | 350 ++++++++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 drivers/remoteproc/corstone1000_rproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 0f0862e20a93..a0ff5d4f2319 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -379,6 +379,20 @@ config XLNX_R5_REMOTEPROC It's safe to say N if not interested in using RPU r5f cores. +config CORSTONE1000_REMOTEPROC + tristate "Arm Corstone-1000 remoteproc support" + depends on ARM64 || (HAS_IOMEM && COMPILE_TEST) + help + Say y here to support Arm Corstone-1000 remote processors via the + remote processor framework. + + Corstone-1000 remote processors are controlled with a reset status + and control registers. The driver also supports control of multiple + remote cores at the same time. + + It's safe to say N here if not interested in utilizing remote + processors. + endif # REMOTEPROC endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 5ff4e2fee4ab..e017f75143e3 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -40,3 +40,4 @@ obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o obj-$(CONFIG_TI_K3_M4_REMOTEPROC) += ti_k3_m4_remoteproc.o obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o +obj-$(CONFIG_CORSTONE1000_REMOTEPROC) += corstone1000_rproc.o diff --git a/drivers/remoteproc/corstone1000_rproc.c b/drivers/remoteproc/corstone1000_rproc.c new file mode 100644 index 000000000000..bf351af6a1c3 --- /dev/null +++ b/drivers/remoteproc/corstone1000_rproc.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Arm Corstone-1000 Remoteproc driver + * + * The driver adds remoteproc support for the external cores used in Arm + * Corstone-1000 IoT Reference Design Platform [1][2] + * [1] Arm Corstone-1000 Technical Overview: https://developer.arm.com/documentation/102360/0000 + * [2] Arm Corstone SSE-710 Subsystem Technical Reference Manual: https://developer.arm.com/documentation/102342/0000 + * + * Copyright (C) 2024 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +/** + * struct corstone1000_rproc - Arm remote processor instance + * @rproc: rproc handler + * @regmap: MMIO register map + * @ctrl_reg: control register offset + * @state_reg: state register offset + */ +struct corstone1000_rproc { + struct rproc *rproc; + struct regmap *regmap; + u16 ctrl_reg; + u16 state_reg; +}; + +/* Definitions for Arm Corstone-1000 External System */ + +/* External Systems identifiers */ +#define EXT_SYS0_ID (0) /* External System 0 ID */ +#define EXT_SYS1_ID (1) /* External System 1 ID */ + +/* External System 0 registers offset */ +#define EXT_SYS0_RST_CTRL (0x310) /* Reset Control register */ +#define EXT_SYS0_RST_ST (0x314) /* Reset Status register */ + +/* External System 1 registers offset */ +#define EXT_SYS1_RST_CTRL (0x318) /* Reset Control register */ +#define EXT_SYS1_RST_ST (0x31c) /* Reset Status register */ + +/* External System Reset Control register bit definitions */ +#define EXTSYS_RST_CTRL_CPUWAIT BIT(0) /* CPU Wait control */ +#define EXTSYS_RST_CTRL_RST_REQ BIT(1) /*Reset request */ + +/* Status of reset request bits */ +#define EXTSYS_RST_ACK_MASK GENMASK(2, 1) +#define GET_EXTSYS_RST_ST_RST_ACK(x) ((u8)(FIELD_GET(EXTSYS_RST_ACK_MASK, \ + (x)))) + +/* Possible values for the Status of reset request */ +#define EXTSYS_RST_ACK_NO_RESET_REQ (0x0) +#define EXTSYS_RST_ACK_NOT_COMPLETE (0x1) +#define EXTSYS_RST_ACK_COMPLETE (0x2) +#define EXTSYS_RST_ACK_RESERVED (0x3) + +/* Polling settings used when reading the Status of reset request */ +#define EXTSYS_RST_ACK_POLL_TRIES (3) +#define EXTSYS_RST_ACK_POLL_TIMEOUT (1000) + +static int corstone1000_rproc_extsys_poll_rst_ack(struct rproc *rproc, + u8 exp_ack, u8 *rst_ack); + +/** + * corstone1000_rproc_start() - custom start operation + * @rproc: pointer to the remote processor object + * + * Start function for Corstone-1000 External System. + * Allow the External System core start execute instructions. + * + * Return: + * + * 0 on success. Otherwise, failure + */ +static int corstone1000_rproc_start(struct rproc *rproc) +{ + struct corstone1000_rproc *priv = rproc->priv; + + /* CPUWAIT signal of the External System is de-asserted */ + + return regmap_write_bits(priv->regmap, priv->ctrl_reg, + EXTSYS_RST_CTRL_CPUWAIT, + (unsigned int)~EXTSYS_RST_CTRL_CPUWAIT); +} + +/** + * corstone1000_rproc_stop() - custom stop operation + * @rproc: pointer to the remote processor object + * + * Reset all logic within the External System, the core will be in a halt state. + * + * Return: + * + * 0 on success. Otherwise, failure + */ +static int corstone1000_rproc_stop(struct rproc *rproc) +{ + struct corstone1000_rproc *priv = rproc->priv; + u8 rst_ack, req_status; + int ret; + + ret = regmap_write_bits(priv->regmap, priv->ctrl_reg, + EXTSYS_RST_CTRL_RST_REQ, + EXTSYS_RST_CTRL_RST_REQ); + if (ret) + return ret; + + ret = corstone1000_rproc_extsys_poll_rst_ack(rproc, + EXTSYS_RST_ACK_COMPLETE | + EXTSYS_RST_ACK_NOT_COMPLETE, + &rst_ack); + if (ret) + return ret; + + req_status = rst_ack; + + ret = regmap_write_bits(priv->regmap, priv->ctrl_reg, + EXTSYS_RST_CTRL_RST_REQ, + (unsigned int)~EXTSYS_RST_CTRL_RST_REQ); + if (ret) + return ret; + + ret = corstone1000_rproc_extsys_poll_rst_ack(rproc, + EXTSYS_RST_ACK_NO_RESET_REQ, + &rst_ack); + if (ret) + return ret; + + if (req_status == EXTSYS_RST_ACK_COMPLETE) + return 0; + + return -EACCES; +} + +/** + * corstone1000_rproc_parse_fw() - Parse firmware operation + * @rproc: pointer to the remote processor object + * @fw: pointer to the firmware + * + * Does nothing currently. No resource information needed from the firmware + * image. + * + * Return: + * + * 0 for success. + */ +static int corstone1000_rproc_parse_fw(struct rproc *rproc, + const struct firmware *fw) +{ + return 0; +} + +/** + * corstone1000_rproc_load() - Load firmware to memory operation + * @rproc: pointer to the remote processor object + * @fw: pointer to the firmware + * + * The remoteproc subsystem expects a firmware image to be provided and loaded + * into memory. In case of Corstone-1000, the firmware is already loaded before + * the Corstone-1000 is powered on and this is done through the FPGA board + * bootloader in case of the FPGA target. Or by the Corstone-1000 FVP model + * when using the FVP target. + * + * Return: + * + * 0 for success. + */ +static int corstone1000_rproc_load(struct rproc *rproc, + const struct firmware *fw) +{ + return 0; +} + +static const struct rproc_ops corstone1000_rproc_ops = { + .start = corstone1000_rproc_start, + .stop = corstone1000_rproc_stop, + .load = corstone1000_rproc_load, + .parse_fw = corstone1000_rproc_parse_fw, +}; + +/** + * corstone1000_rproc_extsys_poll_rst_ack() - poll RST_ACK bits + * @rproc: pointer to the remote processor object + * @exp_ack: expected bits value + * @rst_ack: bits value read + * + * Tries to read RST_ACK bits until the timeout expires. + * EXTSYS_RST_ACK_POLL_TRIES tries are made, + * every EXTSYS_RST_ACK_POLL_TIMEOUT milliseconds. + * + * Return: + * + * 0 on success. Otherwise, failure + */ +static int corstone1000_rproc_extsys_poll_rst_ack(struct rproc *rproc, + u8 exp_ack, u8 *rst_ack) +{ + struct device *dev; + struct corstone1000_rproc *priv; + int tries = EXTSYS_RST_ACK_POLL_TRIES; + int ret; + unsigned long timeout; + u32 state_reg; + + if (!rproc || !rst_ack) + return -ENODATA; + + dev = rproc->dev.parent; + priv = rproc->priv; + + do { + ret = regmap_read(priv->regmap, priv->state_reg, &state_reg); + if (ret) + return ret; + + *rst_ack = GET_EXTSYS_RST_ST_RST_ACK(state_reg); + + if (*rst_ack == EXTSYS_RST_ACK_RESERVED) { + dev_err(dev, "unexpected RST_ACK value: 0x%x\n", + *rst_ack); + return -EINVAL; + } + + /* + * when RST_REQ bit is cleared (No reset requested) + * RST_ACK is expected to be 00 (No reset requested) + */ + if (exp_ack == EXTSYS_RST_ACK_NO_RESET_REQ && + *rst_ack == exp_ack) + return 0; + + /* + * when a reset is requested (RST_REQ set) , RST_ACK is either + * 01 (Reset request unable to complete) or 10 (Reset request + * complete) + */ + if (*rst_ack & exp_ack) + return 0; + + timeout = msleep_interruptible(EXTSYS_RST_ACK_POLL_TIMEOUT); + + if (timeout) { + dev_err(dev, "polling RST_ACK aborted\n"); + return -ECONNABORTED; + } + } while (--tries); + + dev_err(dev, "polling RST_ACK timed out\n"); + + return -ETIMEDOUT; +} + +/** + * corstone1000_rproc_probe() - the platform device probe + * @pdev: the platform device + * + * Setup an rproc device and regmap using syscon + * + * Return: + * + * 0 on success. Otherwise, failure + */ +static int corstone1000_rproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *parent; + struct corstone1000_rproc *priv; + struct rproc *rproc; + const char *fw_name; + struct regmap *regmap; + int ret; + u8 extsys_id = EXT_SYS0_ID; + + ret = rproc_of_parse_firmware(dev, 0, &fw_name); + if (ret) + return dev_err_probe(dev, ret, + "can't parse firmware-name from DT\n"); + + dev_dbg(dev, "firmware-name: %s\n", fw_name); + + rproc = devm_rproc_alloc(dev, np->name, &corstone1000_rproc_ops, fw_name, + sizeof(*priv)); + if (!rproc) + return dev_err_probe(dev, -ENOMEM, + "can't allocate rproc device\n"); + + priv = rproc->priv; + priv->rproc = rproc; + + parent = of_get_parent(dev->of_node); /* parent is syscon node */ + regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + if (IS_ERR_OR_NULL(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "can't read syscon node\n"); + priv->regmap = regmap; + + ret = of_property_read_u8(np, "#extsys-id", &extsys_id); + if (ret) + return dev_err_probe(dev, ret, "can't read '#extsys-id' property\n"); + + if (extsys_id == EXT_SYS0_ID) { + priv->ctrl_reg = EXT_SYS0_RST_CTRL; + priv->state_reg = EXT_SYS0_RST_ST; + } else { + priv->ctrl_reg = EXT_SYS1_RST_CTRL; + priv->state_reg = EXT_SYS1_RST_ST; + } + + platform_set_drvdata(pdev, priv); + + ret = devm_rproc_add(dev, rproc); + if (ret) + return dev_err_probe(dev, ret, "can't add remote processor\n"); + + return 0; +} + +static const struct of_device_id corstone1000_rproc_of_match[] = { + { .compatible = "arm,sse710-extsys"}, + { /* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, corstone1000_rproc_of_match); + +static struct platform_driver corstone1000_rproc_driver = { + .probe = corstone1000_rproc_probe, + .driver = { + .name = "corstone1000-rproc", + .of_match_table = corstone1000_rproc_of_match, + }, +}; +module_platform_driver(corstone1000_rproc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Arm Corstone-1000 Remote Processor Control Driver"); +MODULE_AUTHOR("Abdellatif El Khlifi ");