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Peter Anvin" , Thomas Gleixner , Kim Phillips Subject: [PATCH v2 1/2] x86/cpufeatures: Add "Allowed SEV Features" Feature Date: Thu, 22 Aug 2024 17:19:37 -0500 Message-ID: <20240822221938.2192109-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240822221938.2192109-1-kim.phillips@amd.com> References: <20240822221938.2192109-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|IA1PR12MB8496:EE_ X-MS-Office365-Filtering-Correlation-Id: c3742c60-02c5-4154-77a8-08dcc2f89193 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: Lv2JbVuH/Nw5bSEi32+STPGwSWvyH6tmiVgoNddGWra3lvbn3HinfxoV1nQsU4qllRKa8XXxsZLjBtjsfRHbPJ4Z7NdJXNNZcMeE54/0mIVP++aaeOKPsDRMta3IsP7hSSOuRshLtpKs+NxrEu53oSJnEiYKa4nm9diUKe2B0mdadYU+58tRclnM1Q4T65DRlmZ3RxjJmAJLEjX6CMK4keZsIA6komrwL9Rw6N9oWmp1poVxF/kKok0fgZR2V/rwxJmrjYjbS92Fqo7NjL/mDv4neFKhC48Y737KO3um8Gz7qHT18cX6DyrETBGlLiqbzORBsny4PRiXsd+KQrzgxZyuiFOyT/NnieEw7drmwMLYa50ZpWPG/9KMg11LEUocm6TVid4B5NYdZfGj/HsrOuA36MBL6PGzH68G5WXwb+4jOrEZcU4t6zXi0VcCmuTUInxwQjs5e6l4HoUS+wuFcQBhmfKfGpqMsWnQt56yxYex3vEUv/MLWBjc01Ipcm/0F4uIDcH79xNSjNFlIBTvF8F+b9q0E1oLZgZK4ScdePjSDj1Bn4Y79aUBeAOU4P+HO2/ra9uQapQ3Ab/PWj3mG4RCAzfEoXDm5QMIRjDnECtRqy+h6U6Sq73+g6FCadRICH+bfRSli69Z30TLgVZLwL61I+a0U5LICFcs1ekUHEmSpiyrUkFOdzQXe44AgV8rdnCNKvSbxR6ZbXszXpPoM3RKUL+kbEa5hF/8nLZN9/GVEUftPTGwUql6b6NgO1frf6jMH4lscOASe+YcEwKW47uCq5M/tz4988Jza+wvD1N/s1pAUO1bwCnS5rNDCti/x2uYyRP3A4kG5CQ/ClSPZozP5k1R2bFGoHSGNQTiOgu55DVrDcSCyzVwMck5p7/nSNZ8R7BY8Xy7bNTm8YkFkIAKhyiaNjMUfZqp+k00fxIfZnD69nTPe3EzhIaCyCuza4FjXroH1KLpzpHNgd1pp2MQixAOcbxIzOUt6TzNwMMKsyE3RZgzuzMe5dCGnqgs1jZ4tsXSJJNrLaw1UMIlSvhzH2nqUIgDYOM9HKKgxejVLH04fr3Desvm/ItgtQSKjz6UPo/m5c2D8/e2DPonfRya6l5zQMRsFdvHGtu+6lVlxYKsJSJCeyulRoCT4zrawYZql2+/IfU9akwIeTo0sHqiuRpUUyCLC+TW+ruaSMuJPfffO5HpVgDDAL1Bz5ZPfX1Y6oBVtziBKWd3I75EGU+HftL5+jswQ4B2fZ4iC7axL0rbCvuhgKEuBJXl6H0hKod6zKLivSqpNHOk5byqy8XDMvuiCygaWEZaBJJ6BKdFfRcpcfx1fmFsbWC6Zo9qMOudHwW9NzPY1bldO5X7hfJu8mhzWrHHFbAWWUccYdTWaxgaWEeSVxaMPzImBwncpBK9jx0vSLwL6NDK3ZSi9MKvkBtKAHMuBZfrh4KYAXm60PE8Px4U7XRxKRfiOlQ/ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2024 22:20:02.7306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3742c60-02c5-4154-77a8-08dcc2f89193 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8496 Add CPU feature detection for "Allowed SEV Features" to allow the Hypervisor to enforce that SEV-ES and SEV-SNP guest VMs cannot enable features (via SEV_FEATURES) that the Hypervisor does not support or wish to be enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Kim Phillips --- v2: no changes arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dd4682857c12..0c73da91a041 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -447,6 +447,7 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */ +#define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* AMD Allowed SEV Features */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ From patchwork Thu Aug 22 22:19:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13774283 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2052.outbound.protection.outlook.com [40.107.92.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B124E1D2784; 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Thu, 22 Aug 2024 17:20:11 -0500 From: Kim Phillips To: , , , CC: Tom Lendacky , Michael Roth , Ashish Kalra , "Nikunj A . Dadhania" , Borislav Petkov , Dave Hansen , Sean Christopherson , "Paolo Bonzini" , Ingo Molnar , "H. Peter Anvin" , Thomas Gleixner , Kim Phillips Subject: [PATCH v2 2/2] KVM: SEV: Configure "ALLOWED_SEV_FEATURES" VMCB Field Date: Thu, 22 Aug 2024 17:19:38 -0500 Message-ID: <20240822221938.2192109-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240822221938.2192109-1-kim.phillips@amd.com> References: <20240822221938.2192109-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|BY5PR12MB4259:EE_ X-MS-Office365-Filtering-Correlation-Id: e192ebd8-2a6e-4a32-f8b0-08dcc2f897a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: 5ESogAfz8YlmPAi5FQAs5IsVLWfeh652ZpuXoA1yqLxdnbFS0NVgx/EibQHPfvCW5smkr67rT4S1KRPHCvzKMnYWdj2GK91BxEaWYy6F+FgfPH9Mg7/BlBgGmgHUrYHkkGk5yqtsV8mTFFvGNhyZ6tohAvSoCQle3heqRrhnjLkHPiGGj2wpt/qsmI3Q054CDFosib/f4h0HCdYVKiSkH8zDwSG+Fs9fjY8THJISmVMZtnnJoM0Kcg+oO36MjyIVInnK84KboJzK37pHXAiDw+f22Im8IBdvSEOyWbSGHEqAR8VP2kIr6FZSrUlW1mk4cHmFtHWzKTCSutwnUaf5qRJqWbw8p3eKLpK2rXdy8YD4JvILR18INtb0KWDQJEQYeyO4M06wcbXeTx1z570jSHr1Xn2fiib2vSfHApy4rCMI/ix1qmS8FDA71kAuJV1NdPV5EiTJh/OWlDacxlau82s4IBCSuzyUKbghkNEf2zXiv+vitBN8DZ4JKfrHg6f5xqOPRyDQdipWwnQCZOxyjB0bc7GTn08M7JRVxsTHcNB9hCRZPzBGZOfCbWDWMP5YO+GkK5XO9Ir6gVz9LY+eE0R+ffSY7dXE9aCFzZsgyXHIwB99/dcetMkhpGm/FRDAcVnTILMbWjEbnIGyEF0YmEUfC6/UuaCtP6XNwwWgyn4/qMdMq8MjAAiC+77OLLPXGX0UWiOVSTcDabqPrzLXosv1FEiqKflvWKsB+F3M1RmiWyjurB2IxHKG8eYEDLswKRddTXzS5Hc9FlKDvOpigcDCrTYuMojoWlBHxpLzzI4rC2argoSQqWIV3a2BIpkr62WVACoLzOnhI44MG/ybeJhD0K2JTS0HJBcu/GX8yDLdw8vpbIpM/R7awZ03fI3UBK1IEcOcereD6g59ycO6URGfynBfUndpo3Sy2ewK4dJb91lgtbSDdjUoaqA+P31KyBOrd/41Owk2OMWey0nrSw0pEl73wuAgyXYKJatlWDOH2TvOpqJ3qTBIalOLTFPkiJA9M8A7HoJouZrTEWdP9zIRCskt7QT8v2+TIQ/6uN/M/ysnc4Pg+ka8nbsrZTDHYdM1vyuGZ9YtRi9dv5QvS4t/MRSGWxUQ6sBs7kXjalwu9DEOam2KFmdD+F6M6Mi3yzGk7d0XtiTvm2pRxj30GQPNofDrkA3NEaRbvuAkXJcmPyfXEYqPdu2K+J15RvP2IYu5kKLUr9S1zjFIc8VZhatipz271IqkgvGDLpbQMXD9sik/UWrtfheOP4D7077XHpMGLgD5GRxPNvnvJBB8uAhx0cZiJ66OTp/qPYhyImvb6JBQernhesawcGLgxfZz5lpUddIxeb6Uo9SgIj4NV5EqxYXINEkllUYGDpoKQnHt1GwT1kjQBQWlCVpmgm81sFoset0fpC3XpwjCSzY3SQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2024 22:20:13.0744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e192ebd8-2a6e-4a32-f8b0-08dcc2f897a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4259 AMD EPYC 5th generation processors have introduced a feature that allows the hypervisor to control the SEV_FEATURES that are set for, or by, a guest [1]. ALLOWED_SEV_FEATURES can be used by the hypervisor to enforce that SEV-ES and SEV-SNP guests cannot enable features that the hypervisor does not want to be enabled. When ALLOWED_SEV_FEATURES is enabled, a VMRUN will fail if any non-reserved bits are 1 in SEV_FEATURES but are 0 in ALLOWED_SEV_FEATURES. Some SEV_FEATURES (currently PmcVirtualization and SecureAvic according to Appendix B, Table B-4) require an opt-in via ALLOWED_SEV_FEATURES, i.e. are off-by-default, whereas all other features are effectively on-by-default, but still honor ALLOWED_SEV_FEATURES. [1] Section 15.36.20 "Allowed SEV Features", AMD64 Architecture Programmer's Manual, Pub. 24593 Rev. 3.42 - March 2024: https://bugzilla.kernel.org/attachment.cgi?id=306250 Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Kim Phillips Reviewed-by: Nikunj A. Dadhania --- v2: - Added some SEV_FEATURES require to be explicitly allowed by ALLOWED_SEV_FEATURES wording (Sean). - Added Nikunj's Reviewed-by. v1: https://lore.kernel.org/lkml/20240802015732.3192877-3-kim.phillips@amd.com/ arch/x86/include/asm/svm.h | 6 +++++- arch/x86/kvm/svm/sev.c | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index f0dea3750ca9..59516ad2028b 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -158,7 +158,9 @@ struct __attribute__ ((__packed__)) vmcb_control_area { u64 avic_physical_id; /* Offset 0xf8 */ u8 reserved_7[8]; u64 vmsa_pa; /* Used for an SEV-ES guest */ - u8 reserved_8[720]; + u8 reserved_8[40]; + u64 allowed_sev_features; /* Offset 0x138 */ + u8 reserved_9[672]; /* * Offset 0x3e0, 32 bytes reserved * for use by hypervisor/software. @@ -294,6 +296,8 @@ static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_ (SVM_SEV_FEAT_RESTRICTED_INJECTION | \ SVM_SEV_FEAT_ALTERNATE_INJECTION) +#define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) + struct vmcb_seg { u16 selector; u16 attrib; diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index a16c873b3232..d12b4d615b32 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -899,6 +899,7 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) static int __sev_launch_update_vmsa(struct kvm *kvm, struct kvm_vcpu *vcpu, int *error) { + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; struct sev_data_launch_update_vmsa vmsa; struct vcpu_svm *svm = to_svm(vcpu); int ret; @@ -908,6 +909,10 @@ static int __sev_launch_update_vmsa(struct kvm *kvm, struct kvm_vcpu *vcpu, return -EINVAL; } + if (cpu_feature_enabled(X86_FEATURE_ALLOWED_SEV_FEATURES)) + svm->vmcb->control.allowed_sev_features = VMCB_ALLOWED_SEV_FEATURES_VALID | + sev->vmsa_features; + /* Perform some pre-encryption checks against the VMSA */ ret = sev_es_sync_vmsa(svm); if (ret)