From patchwork Mon Aug 26 17:56:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13778318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4C26C5321D for ; Mon, 26 Aug 2024 17:59:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=K3qKt60IA+8SMUnwHI81gxuyfVTw/GaObbKMY0sD6g8=; b=49yr69wjpHbKLDK98w3PHfbmMw kOl6ZF/qjKOz3Fv8vvpqhdfIpw1hGmfCbPak6ohRGvTClHan0x9+z56KE40kYT9og6VH1KsTxlQVB FUq/0pREAe1OjldmDesBl+JB3x5QcYblVfmJ9ztMGwgi7INVmmDe34sMoTENNz5NwUlCcgZOT46HD wpK4Q36Ss8edt1ncIw4c4bHYBKRw3XYTwWzHZ59UkiuAfx+L23TEhds31UPeE6j3vfV+8wK7QBBC9 k7RKuRJaAphnOHPFsABurfIVk1GeBBzBQ+qNA0EAEvcwGSHFGix2H38TvUXDEzr5Hghw7st72O2OL Y1gXCxvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sie00-00000008JAW-2HFN; Mon, 26 Aug 2024 17:59:28 +0000 Received: from mta-64-226.siemens.flowmailer.net ([185.136.64.226]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sidwv-00000008IQ9-0QJ0 for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2024 17:56:19 +0000 Received: by mta-64-226.siemens.flowmailer.net with ESMTPSA id 20240826175611796af162386e4c4a6f for ; Mon, 26 Aug 2024 19:56:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=K3qKt60IA+8SMUnwHI81gxuyfVTw/GaObbKMY0sD6g8=; b=BwVym2FKf4NoJWXhih/m0Sd3L3Ikr+o+yfSWKoWnX/ONFGSxaRKHkyIJTTAaxcrD+tAdCE yv+tzWGCBXqBVppbG21kxwzXblJ9dOfDMJItcil1KdNQ8DcNFbiIi8RTc8nTHJx8rv317I8C x7scrumhMEqsWPGpGTz1KwEG40HKe2d0wVM92wLjgjUwX4o7+Df9Fuu1T3Lo4lxreqkuYQMB gzRXWbBgCNS4rPhZWARRyVYwfAotziKOj7fSEsW6FnECGo+B0VeFLukLWGvcTIl7tvA4o1tv XdJRijY8NBFh2f3scuIcG8q+CiDkvcJIkLVFttQge97ulEp/Gqq7Qn4w==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH 1/5] dt-bindings: soc: ti: Add AM65 peripheral virtualization unit Date: Mon, 26 Aug 2024 19:56:05 +0200 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_105617_306316_74C06B06 X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka The PVU allows to define a limited set of mappings for incoming DMA requests to the system memory. It is not a real IOMMU, thus hooked up under the TI SoC bindings. Signed-off-by: Jan Kiszka --- .../bindings/soc/ti/ti,am654-pvu.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml diff --git a/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml b/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml new file mode 100644 index 000000000000..3095db0bef44 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) Siemens AG, 2024 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ti,am654-pvu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM654 Peripheral Virtualization Unit + +properties: + compatible: + enum: + - ti,am654-pvu + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: tlbif + + interrupts: + items: + - description: fault interrupt + + interrupt-names: + items: + - const: pvu + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + ti-pvu@30f80000 { + compatible = "ti,am654-pvu"; + reg = <0 0x30f80000 0 0x1000>, + <0 0x36000000 0 0x100000>; + reg-names = "cfg", "tlbif"; + interrupts-extended = <&intr_main_navss 390>; + interrupt-names = "pvu"; + }; From patchwork Mon Aug 26 17:56:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13778319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C7B3C5472D for ; Mon, 26 Aug 2024 18:00:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eDmdVYVrSEBX0NAgV+sGm+rXTWvUKFLaVbBX2oL5YuU=; b=yR4aoSMDz33A2p5yGUOC+k+Jq9 a3rrwdQ18evar1hL46r0nbTW7vyaW9AcToz9eSEmKpA2YjYzVcA3k3K6m44sOsZv5WzwpEVc2jDqt mXSF7vvKplSybwDH77f8bawXhZFe8vbAE9o0S5XvGBtFz9jP0gPXyxHkjvphVqHfTWqcBM1V1yYYs CHwgUeqguI9x7fdNqVMaTOM1XwoKhJutoxtVfQTxAtmWCS9CBHJzixJMnn7X9i60KnVnnsUE4E2Hf AcruBeEcQBywa0l0zroL9YiEbLNs3eVeM70TS573qLeRPXufGejeKP2lXYMRwiTZMOYzEE1wrs677 qQtBu2+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sie0k-00000008JGx-24Nf; Mon, 26 Aug 2024 18:00:14 +0000 Received: from mta-65-225.siemens.flowmailer.net ([185.136.65.225]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sidwu-00000008IQ3-0Gb9 for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2024 17:56:20 +0000 Received: by mta-65-225.siemens.flowmailer.net with ESMTPSA id 202408261756121760633121aac1a969 for ; Mon, 26 Aug 2024 19:56:12 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=eDmdVYVrSEBX0NAgV+sGm+rXTWvUKFLaVbBX2oL5YuU=; b=B5EikNzpZh+nl6CapnQuTjEAtohu5QpESCsXfavi5QstCC7z5PDyW+9wPrTK4bJS8HRV43 dX1DY5bp5s1IkWuw5kAxt1i/ROc5jf62o+jf43M/UpEe1Z7jslxpGwtHot69nE/swPOgZcUS RDIFOMqu4/cHjIheGqg2B1670RwE5H4enioKGbfjMemoIUjBSRIAaWyNz7WuRX8gVnmCc3Sn 585W+PWSpkFCTqCgWH/OS0Dxa4hwPpMSEghKaruSky3mOfa5HO5GT41Qkwkj8wuvMEreNv5d EWgXNFqRdhxNrIg7pqSJ7BdFX9+IG+vxBFm9tznFtmvsy9AkTknsHo3w==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH 2/5] soc: ti: Add IOMPU-like PVU driver Date: Mon, 26 Aug 2024 19:56:06 +0200 Message-ID: <30e16282dd0f7583c8d6ad0078ccdb17a804504d.1724694969.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_105616_711819_D8BC7ECD X-CRM114-Status: GOOD ( 27.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka The TI Peripheral Virtualization Unit (PVU) permits to define a limited set of mappings for DMA requests on the system memory. Unlike with an IOMMU, there is no fallback to a memory-backed page table, only a fixed set of register-backed TLBs. Emulating an IOMMU behavior appears to be the more fragile the more fragmentation of pending requests occur. Therefore, this driver does not expose the PVU as an IOMMU. It rather introduces a simple, static interface to devices that are under restricted-dma-pool constraints. They can register their pools with the PVUs, enabling only those pools to work for DMA. As also MSI is issued as DMA, the PVU already register the related translator region of the AM654 as valid DMA target. This driver is the essential building block for limiting DMA from untrusted devices to clearly defined memory regions in the absence of a real IOMMU (SMMU). Co-developed-by: Diogo Ivo Signed-off-by: Jan Kiszka --- drivers/soc/ti/Kconfig | 4 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/ti-pvu.c | 487 ++++++++++++++++++++++++++++++++++++++++ include/linux/ti-pvu.h | 11 + 4 files changed, 503 insertions(+) create mode 100644 drivers/soc/ti/ti-pvu.c create mode 100644 include/linux/ti-pvu.h diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 1a93001c9e36..af7173ad84de 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -82,6 +82,10 @@ config TI_PRUSS processors on various TI SoCs. It's safe to say N here if you're not interested in the PRU or if you are unsure. +config TI_PVU + bool "TI Peripheral Virtualization Unit driver" + depends on ARCH_K3 && DMA_RESTRICTED_POOL + endif # SOC_TI config TI_SCI_INTA_MSI_DOMAIN diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index cb800a745e66..ecff3fd8c433 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TI_K3_RINGACC) += k3-ringacc.o obj-$(CONFIG_TI_K3_SOCINFO) += k3-socinfo.o obj-$(CONFIG_TI_PRUSS) += pruss.o obj-$(CONFIG_POWER_AVS_OMAP) += smartreflex.o +obj-$(CONFIG_TI_PVU) += ti-pvu.o diff --git a/drivers/soc/ti/ti-pvu.c b/drivers/soc/ti/ti-pvu.c new file mode 100644 index 000000000000..af1cadc2f4bc --- /dev/null +++ b/drivers/soc/ti/ti-pvu.c @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#include +#include +#include +#include +#include +#include + +#define PVU_CONFIG 0x4 +#define PVU_ENABLE 0x10 +#define PVU_VIRTID_MAP1 0x14 +#define PVU_VIRTID_MAP2 0x18 +#define PVU_EXCEPTION_LOGGING_CONTROL 0x120 +#define PVU_EXCEPTION_LOGGING_HEADER0 0x124 +#define PVU_EXCEPTION_LOGGING_HEADER1 0x128 +#define PVU_EXCEPTION_LOGGING_DATA0 0x12c +#define PVU_EXCEPTION_LOGGING_DATA1 0x130 +#define PVU_EXCEPTION_LOGGING_DATA2 0x134 +#define PVU_EXCEPTION_LOGGING_DATA2_SECURE BIT(0) +#define PVU_EXCEPTION_LOGGING_DATA2_PRIV BIT(1) +#define PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE BIT(2) +#define PVU_EXCEPTION_LOGGING_DATA2_DEBUG BIT(3) +#define PVU_EXCEPTION_LOGGING_DATA2_READ BIT(4) +#define PVU_EXCEPTION_LOGGING_DATA2_WRITE BIT(5) +#define PVU_EXCEPTION_LOGGING_DATA3 0x138 +#define PVU_EXCEPTION_ENABLE_SET 0x148 +#define PVU_EOI_REG 0x150 + +#define PVU_CHAIN 0x0 +#define PVU_CHAIN_EN BIT(31) +#define PVU_CHAIN_LOG_DIS BIT(30) +#define PVU_CHAIN_FAULT BIT(29) +#define PVU_CHAIN_MASK 0xfff +#define PVU_ENTRY0 0x20 +#define PVU_ENTRY1 0x24 +#define PVU_ENTRY1_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY1_VBASE_H_MASK 0xffff +#define PVU_ENTRY2 0x28 +#define PVU_ENTRY2_RESERVED_MASK 0x1fd00080 +#define PVU_ENTRY2_INVALID (0U << 30) +#define PVU_ENTRY2_VALID (2U << 30) +#define PVU_ENTRY2_MODE_MASK 0xc0000000 +#define PVU_ENTRY2_PSIZE_SHIFT 16 +#define PVU_ENTRY2_PSIZE_MASK 0xf +#define PVU_ENTRY2_PERM_SX BIT(15) +#define PVU_ENTRY2_PERM_SW BIT(14) +#define PVU_ENTRY2_PERM_SR BIT(13) +#define PVU_ENTRY2_PERM_UX BIT(12) +#define PVU_ENTRY2_PERM_UW BIT(11) +#define PVU_ENTRY2_PERM_UR BIT(10) +#define PVU_ENTRY2_MEM_WRITETHROUGH (2 << 8) +#define PVU_ENTRY2_OUTER_SHARABLE BIT(4) +#define PVU_ENTRY2_IS_NOALLOC (0 << 2) +#define PVU_ENTRY2_OS_NOALLOC (0 << 0) +#define PVU_ENTRY4 0x30 +#define PVU_ENTRY5 0x34 +#define PVU_ENTRY5_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY5_PBASE_H_MASK 0xffff +#define PVU_ENTRY6 0x38 +#define PVU_ENTRY6_RESERVED_MASK 0xffffffe0 + +#define NUM_VIRTIDS 1 + +static const struct regmap_config pvu_cfg_regmap_cfg = { + .name = "pvu-cfg", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = PVU_EOI_REG, +}; + +enum pvu_cfg_regfields { + PVU_TLBS, + PVU_TLB_ENTRIES, + PVU_ENABLED, + PVU_DMA_CNT, + PVU_DMA_CL0, + PVU_DMA_CL1, + PVU_DMA_CL2, + PVU_DMA_CL3, + PVU_MAX_VIRTID, + PVU_EXC_SRC_ID, + PVU_EXC_CODE, + PVU_EXC_ADDR_L, + PVU_EXC_ADDR_H, + PVU_EXC_PRIV_ID, + PVU_EXC_PROPS, + PVU_EXC_ROUTE_ID, + PVU_EXC_BYTE_CNT, + PVU_EXC_ENABLE, + PVU_EOI, + PVU_MAX_CFG_FIELDS, +}; + +static const struct reg_field pvu_cfg_reg_fields[] = { + [PVU_TLBS] = REG_FIELD(PVU_CONFIG, 0, 15), + [PVU_TLB_ENTRIES] = REG_FIELD(PVU_CONFIG, 16, 23), + [PVU_ENABLED] = REG_FIELD(PVU_ENABLE, 0, 0), + [PVU_DMA_CNT] = REG_FIELD(PVU_VIRTID_MAP1, 0, 11), + [PVU_DMA_CL0] = REG_FIELD(PVU_VIRTID_MAP1, 16, 17), + [PVU_DMA_CL1] = REG_FIELD(PVU_VIRTID_MAP1, 18, 19), + [PVU_DMA_CL2] = REG_FIELD(PVU_VIRTID_MAP1, 20, 21), + [PVU_DMA_CL3] = REG_FIELD(PVU_VIRTID_MAP1, 22, 23), + [PVU_MAX_VIRTID] = REG_FIELD(PVU_VIRTID_MAP2, 0, 11), + [PVU_EXC_SRC_ID] = REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER0, 8, 23), + [PVU_EXC_CODE] = REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER1, 16, 23), + [PVU_EXC_ADDR_L] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA0, 0, 31), + [PVU_EXC_ADDR_H] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA1, 0, 15), + [PVU_EXC_PRIV_ID] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 0, 7), + [PVU_EXC_PROPS] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 8, 13), + [PVU_EXC_ROUTE_ID] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 16, 27), + [PVU_EXC_BYTE_CNT] = REG_FIELD(PVU_EXCEPTION_LOGGING_DATA3, 0, 9), + [PVU_EXC_ENABLE] = REG_FIELD(PVU_EXCEPTION_ENABLE_SET, 0, 0), + [PVU_EOI] = REG_FIELD(PVU_EOI_REG, 0, 15), +}; + +struct ti_pvu { + struct list_head entry; + struct platform_device *pdev; + struct regmap *cfg; + struct regmap_field *cfg_fields[PVU_MAX_CFG_FIELDS]; + void __iomem *tlbif_base; + unsigned int num_tlbs; + unsigned int num_entries; +}; + +static const char *pvu_excp_code_string[] = { + "PVU miss", + "maximum VirtID violation", + "", + "read permission violation", + "write permission violation", + "execute permission violation", + "prefetch permission violation", + "", +}; + +static const u64 pvu_page_size[] = { + 4 * 1024ULL, + 16 * 1024ULL, + 64 * 1024ULL, + 2 * 1024 * 1024ULL, + 32 * 1024 * 1024ULL, + 512 * 1024 * 1024ULL, + 1 * 1024 * 1024 * 1024ULL, + 16 * 1024 * 1024 * 1024ULL +}; + +static DEFINE_MUTEX(ti_pvu_lock); +static LIST_HEAD(ti_pvu_list); + +static unsigned int pvu_field_read(struct ti_pvu *pvu, enum pvu_cfg_regfields f) +{ + int ret; + unsigned int val; + + ret = regmap_field_read(pvu->cfg_fields[f], &val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to read field\n"); + + return val; +} + +static void pvu_field_write(struct ti_pvu *pvu, enum pvu_cfg_regfields f, + unsigned int val) +{ + int ret; + + ret = regmap_field_write(pvu->cfg_fields[f], val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to write field\n"); +} + +static irqreturn_t pvu_fault_isr(int irq, void *dev_id) +{ + u32 code, bytes, route_id, priv_id, props; + struct ti_pvu *pvu = dev_id; + const char *code_str; + u64 address; + + code = pvu_field_read(pvu, PVU_EXC_CODE); + code_str = pvu_excp_code_string[ + min(code, (u32)ARRAY_SIZE(pvu_excp_code_string) - 1)]; + + dev_err(&pvu->pdev->dev, "fault detected, code %d (%s)\n", + code, code_str); + + address = pvu_field_read(pvu, PVU_EXC_ADDR_L); + address |= (u64)pvu_field_read(pvu, PVU_EXC_ADDR_H) << 32; + + bytes = pvu_field_read(pvu, PVU_EXC_BYTE_CNT); + + route_id = pvu_field_read(pvu, PVU_EXC_ROUTE_ID); + priv_id = pvu_field_read(pvu, PVU_EXC_PRIV_ID); + props = pvu_field_read(pvu, PVU_EXC_PROPS); + + dev_err(&pvu->pdev->dev, + " address 0x%016llx size %d route-ID %d priv-ID %d flags %c%c%c%c%c%c\n", + address, bytes, route_id, priv_id, + (props & PVU_EXCEPTION_LOGGING_DATA2_WRITE) ? 'W' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_READ) ? 'R' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_DEBUG) ? 'D' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE) ? 'C' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_PRIV) ? 'P' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_SECURE) ? 'S' : '-'); + + pvu_field_write(pvu, PVU_EOI, 0); + + return IRQ_HANDLED; +} + +static int pvu_get_free_entry(struct ti_pvu *pvu) +{ + unsigned int n; + u32 val; + + for (n = 0; n < pvu->num_entries; n++) { + val = readl(pvu->tlbif_base + n * 0x20 + PVU_ENTRY2); + if ((val & PVU_ENTRY2_MODE_MASK) == PVU_ENTRY2_INVALID) + return n; + } + return -ENOSPC; +} + +static void pvu_write_entry(struct ti_pvu *pvu, unsigned int entry, + u64 addr, u32 psize) +{ + void __iomem *entry_base = pvu->tlbif_base + entry * 0x20; + u32 val; + + writel((u32)addr, entry_base + PVU_ENTRY0); + + val = readl(entry_base + PVU_ENTRY1); + val &= PVU_ENTRY1_RESERVED_MASK; + val |= (addr >> 32) & PVU_ENTRY1_VBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY1); + + writel((u32)addr, entry_base + PVU_ENTRY4); + + val = readl(entry_base + PVU_ENTRY5); + val &= PVU_ENTRY5_RESERVED_MASK; + val |= (addr >> 32) & PVU_ENTRY5_PBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY5); + + val = readl(entry_base + PVU_ENTRY6); + val &= PVU_ENTRY6_RESERVED_MASK; + writel(val, entry_base + PVU_ENTRY6); + + val = readl(entry_base + PVU_ENTRY2); + val &= PVU_ENTRY2_RESERVED_MASK; + val |= psize << PVU_ENTRY2_PSIZE_SHIFT; + val |= PVU_ENTRY2_VALID | + PVU_ENTRY2_PERM_UR | PVU_ENTRY2_PERM_SR | + PVU_ENTRY2_PERM_UW | PVU_ENTRY2_PERM_SW | + PVU_ENTRY2_PERM_UX | PVU_ENTRY2_PERM_SX | + PVU_ENTRY2_MEM_WRITETHROUGH | PVU_ENTRY2_OUTER_SHARABLE | + PVU_ENTRY2_IS_NOALLOC | PVU_ENTRY2_OS_NOALLOC; + writel(val, entry_base + PVU_ENTRY2); +} + +static int pvu_create_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + u64 page_size; + int psize; + int entry; + + while (size > 0) { + entry = pvu_get_free_entry(pvu); + if (entry < 0) { + dev_err(&pvu->pdev->dev, "ran out of TLB entries\n"); + return -ENOSPC; + } + + for (psize = ARRAY_SIZE(pvu_page_size) - 1; psize >= 0; psize--) { + page_size = pvu_page_size[psize]; + if (size >= page_size && (addr & (page_size - 1)) == 0) + break; + } + if (psize < 0) { + dev_err(&pvu->pdev->dev, "unaligned region provided\n"); + return -EINVAL; + } + + pvu_write_entry(pvu, entry, addr, psize); + dev_info(&pvu->pdev->dev, + "created TLB entry 0.%d: 0x%08llx, psize %d (0x%08llx)\n", + entry, addr, psize, page_size); + + size -= page_size; + addr += page_size; + } + + return 0; +} + +static void pvu_remove_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + void __iomem *entry_base; + unsigned int n, psize; + u64 entry_addr; + u32 entry2; + + for (n = 0; n < pvu->num_entries; n++) { + entry_base = pvu->tlbif_base + n * 0x20; + entry2 = readl(entry_base + PVU_ENTRY2); + if ((entry2 & PVU_ENTRY2_MODE_MASK) != PVU_ENTRY2_VALID) + continue; + + entry_addr = readl(entry_base + PVU_ENTRY0); + entry_addr |= (u64)(readl(entry_base + PVU_ENTRY1) & + PVU_ENTRY1_VBASE_H_MASK) << 32; + + psize = (entry2 >> PVU_ENTRY2_PSIZE_SHIFT) & + PVU_ENTRY2_PSIZE_MASK; + if (psize >= ARRAY_SIZE(pvu_page_size)) + continue; + + if (entry_addr >= addr && + (entry_addr + pvu_page_size[psize]) <= (addr + size)) { + entry2 &= ~PVU_ENTRY2_MODE_MASK; + entry2 |= PVU_ENTRY2_INVALID; + writel(entry2, entry_base + PVU_ENTRY2); + + dev_info(&pvu->pdev->dev, + "removed TLB entry 0.%d\n", n); + } + } +} + +int ti_pvu_create_region(unsigned int virt_id, const struct resource *region) +{ + struct ti_pvu *pvu; + int err = 0; + + if (virt_id >= NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + err = pvu_create_region(pvu, region->start, + region->end + 1 - region->start); + if (err) + break; + } + + mutex_unlock(&ti_pvu_lock); + + return err; +} + +int ti_pvu_remove_region(unsigned int virt_id, const struct resource *region) +{ + struct ti_pvu *pvu; + + if (virt_id >= NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + pvu_remove_region(pvu, region->start, + region->end + 1 - region->start); + } + + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static int ti_pvu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *its_node; + void __iomem *base; + struct ti_pvu *pvu; + u32 val; + int ret; + + pvu = devm_kzalloc(dev, sizeof(struct ti_pvu), GFP_KERNEL); + if (!pvu) + return -ENOMEM; + + pvu->pdev = pdev; + + base = devm_platform_ioremap_resource_byname(pdev, "cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + + pvu->cfg = devm_regmap_init_mmio(dev, base, &pvu_cfg_regmap_cfg); + if (IS_ERR(pvu->cfg)) + return dev_err_probe(dev, PTR_ERR(pvu->cfg), "failed to init cfg regmap"); + + ret = devm_regmap_field_bulk_alloc(dev, pvu->cfg, pvu->cfg_fields, + pvu_cfg_reg_fields, PVU_MAX_CFG_FIELDS); + if (ret) + return dev_err_probe(dev, ret, "failed to alloc cfg regmap fields"); + + pvu->num_tlbs = pvu_field_read(pvu, PVU_TLBS); + pvu->num_entries = pvu_field_read(pvu, PVU_TLB_ENTRIES); + dev_info(dev, "TLBs: %d, entries per TLB: %d\n", pvu->num_tlbs, + pvu->num_entries); + + pvu->tlbif_base = devm_platform_ioremap_resource_byname(pdev, "tlbif"); + if (IS_ERR(pvu->tlbif_base)) + return PTR_ERR(pvu->tlbif_base); + + its_node = of_find_compatible_node(0, 0, "arm,gic-v3-its"); + if (its_node) { + u32 pre_its_window[2]; + + ret = of_property_read_u32_array(its_node, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window)); + if (ret) { + dev_err(dev, "failed to read pre-its property\n"); + return ret; + } + + ret = pvu_create_region(pvu, pre_its_window[0], + pre_its_window[1]); + if (ret) + return ret; + } + + val = readl(pvu->tlbif_base + PVU_CHAIN); + val |= PVU_CHAIN_EN; + writel(val, pvu->tlbif_base + PVU_CHAIN); + + pvu_field_write(pvu, PVU_DMA_CNT, 0); + pvu_field_write(pvu, PVU_DMA_CL0, 0); + pvu_field_write(pvu, PVU_DMA_CL1, 0); + pvu_field_write(pvu, PVU_DMA_CL2, 0); + pvu_field_write(pvu, PVU_DMA_CL3, 0); + pvu_field_write(pvu, PVU_MAX_VIRTID, NUM_VIRTIDS); + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get irq\n"); + + ret = devm_request_irq(dev, ret, pvu_fault_isr, 0, dev_name(dev), pvu); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + pvu_field_write(pvu, PVU_EXC_ENABLE, 1); + pvu_field_write(pvu, PVU_ENABLED, 1); + + dev_set_drvdata(dev, pvu); + + mutex_lock(&ti_pvu_lock); + list_add(&pvu->entry, &ti_pvu_list); + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static void ti_pvu_remove(struct platform_device *pdev) +{ + struct ti_pvu *pvu = dev_get_drvdata(&pdev->dev); + + mutex_lock(&ti_pvu_lock); + list_del(&pvu->entry); + mutex_unlock(&ti_pvu_lock); +} + +static const struct of_device_id ti_pvu_of_match[] = { + { .compatible = "ti,am654-pvu", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ti_pvu_of_match); + +static struct platform_driver ti_pvu_driver = { + .driver = { + .name = "ti-pvu", + .of_match_table = ti_pvu_of_match, + }, + .probe = ti_pvu_probe, + .remove_new = ti_pvu_remove, +}; +module_platform_driver(ti_pvu_driver); diff --git a/include/linux/ti-pvu.h b/include/linux/ti-pvu.h new file mode 100644 index 000000000000..d40642522cf0 --- /dev/null +++ b/include/linux/ti-pvu.h @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#include + +int ti_pvu_create_region(unsigned int virt_id, const struct resource *region); +int ti_pvu_remove_region(unsigned int virt_id, const struct resource *region); From patchwork Mon Aug 26 17:56:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13778320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B58FFC5472E for ; Mon, 26 Aug 2024 18:01:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=994WEgmSr6YSmkCGjFYWFV2N5vlQvq3ltUdhvovY9/Y=; b=B7mFFY1kPleNz1b3yLiXsmFVh5REX58dw4cmjx1c1TYsvOqKbkG+S30Ya5ntPtEkEsFSIh MtfGiubE7qD2KNymMQaYlPmx4KQ3WWbB/kCtzpwRVfv8hlao62/SrOZg41kudoGCFbfqg15W pgWj8I286/pDczzQ89YrQpzD2zwnZhmNCMijYChY6MOXQ1Y79UV1YgFehySeVr4382ZciN+P IKjioAM942km4+yhhwPbeKYoWCj7lfE9H+2oAaxIXQVnTl2II/j12sWdODAb9rdHrD1cAQtZ y92ionDvkrft0iBDJuc7LfVj2TatPmHPzmzortA7HUPu8yY3mNPTUFSw==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH 3/5] arm64: dts: ti: k3-am65-main: Add VMAP registers to PCI root complexes Date: Mon, 26 Aug 2024 19:56:07 +0200 Message-ID: <592bf31689620f4d9c8164fa0865bc3663d20ca0.1724694969.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_105617_441145_F9896110 X-CRM114-Status: UNSURE ( 8.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka Rewrap the long lines at this chance. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index a8664b246795..c91969ddcf4d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -867,8 +867,13 @@ main_gpio1: gpio@601000 { pcie0_rc: pcie@5500000 { compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + reg = <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x2000>, + <0x0 0x5506000 0x0 0x1000>, + <0x0 0x2900000 0x0 0x1000>, + <0x0 0x2908000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>; @@ -888,8 +893,13 @@ pcie0_rc: pcie@5500000 { pcie1_rc: pcie@5600000 { compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; + reg = <0x0 0x5600000 0x0 0x1000>, + <0x0 0x5601000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x2000>, + <0x0 0x5606000 0x0 0x1000>, + <0x0 0x2910000 0x0 0x1000>, + <0x0 0x2918000 0x0 0x1000>; + reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; #size-cells = <2>; From patchwork Mon Aug 26 17:56:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13778315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08982C5472D for ; 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From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , linux-pci@vger.kernel.org Subject: [PATCH 4/5] PCI: keystone: Add supported for PVU-based DMA isolation on AM654 Date: Mon, 26 Aug 2024 19:56:08 +0200 Message-ID: <3a41969d3f3af044fbde04c9314e9644c833451c.1724694969.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_105616_697766_D7544D5F X-CRM114-Status: GOOD ( 20.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka The AM654 lacks an IOMMU, thus does not support isolating DMA requests from untrusted PCI devices to selected memory regions this way. Use static PVU-based protection instead. For this, we use the availability of restricted-dma-pool memory regions as trigger and register those as valid DMA targets with the PVU. In addition, we need to enable the mapping of requester IDs to VirtIDs in the PCI RC. We only use a single VirtID so far, catching all devices. This may be extended later on. Signed-off-by: Jan Kiszka --- CC: Lorenzo Pieralisi CC: "Krzysztof Wilczyński" CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pci-keystone.c | 101 ++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 2219b1a866fa..96b871656da4 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include #include "../../pci.h" #include "pcie-designware.h" @@ -111,6 +113,16 @@ #define PCI_DEVICE_ID_TI_AM654X 0xb00c +#define KS_PCI_VIRTID 0 + +#define PCIE_VMAP_xP_CTRL 0x0 +#define PCIE_VMAP_xP_REQID 0x4 +#define PCIE_VMAP_xP_VIRTID 0x8 + +#define PCIE_VMAP_xP_CTRL_EN BIT(0) + +#define PCIE_VMAP_xP_VIRTID_VID_MASK 0xfff + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -1125,6 +1137,89 @@ static const struct of_device_id ks_pcie_of_match[] = { { }, }; +#ifdef CONFIG_TI_PVU +static const char *ks_vmap_res[] = {"vmap_lp", "vmap_hp"}; + +static int ks_init_restricted_dma(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct of_phandle_iterator it; + bool init_vmap = false; + struct resource phys; + struct resource *res; + void __iomem *base; + unsigned int n; + u32 val; + int err; + + of_for_each_phandle(&it, err, dev->of_node, "memory-region", + NULL, 0) { + if (!of_device_is_compatible(it.node, "restricted-dma-pool")) + continue; + + err = of_address_to_resource(it.node, 0, &phys); + if (err < 0) { + dev_err(dev, "failed to parse memory region %pOF: %d\n", + it.node, err); + continue; + } + + err = ti_pvu_create_region(KS_PCI_VIRTID, &phys); + if (err < 0) + return err; + + init_vmap = true; + } + + if (init_vmap) { + for (n = 0; n < ARRAY_SIZE(ks_vmap_res); n++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + ks_vmap_res[n]); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + writel(0, base + PCIE_VMAP_xP_REQID); + + val = readl(base + PCIE_VMAP_xP_VIRTID); + val &= ~PCIE_VMAP_xP_VIRTID_VID_MASK; + val |= KS_PCI_VIRTID; + writel(val, base + PCIE_VMAP_xP_VIRTID); + + val = readl(base + PCIE_VMAP_xP_CTRL); + val |= PCIE_VMAP_xP_CTRL_EN; + writel(val, base + PCIE_VMAP_xP_CTRL); + } + } + + return 0; +} + +static void ks_release_restricted_dma(struct platform_device *pdev) +{ + struct of_phandle_iterator it; + struct resource phys; + int err; + + of_for_each_phandle(&it, err, pdev->dev.of_node, "memory-region", + NULL, 0) { + if (of_device_is_compatible(it.node, "restricted-dma-pool") && + of_address_to_resource(it.node, 0, &phys) == 0) + ti_pvu_remove_region(KS_PCI_VIRTID, &phys); + + } +} +#else +static inline int ks_init_restricted_dma(struct platform_device *pdev) +{ + return 0; +} + +static inline void ks_release_restricted_dma(struct platform_device *pdev) +{ +} +#endif + static int ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; @@ -1273,6 +1368,10 @@ static int ks_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_get_sync; + ret = ks_init_restricted_dma(pdev); + if (ret < 0) + goto err_get_sync; + switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { @@ -1354,6 +1453,8 @@ static void ks_pcie_remove(struct platform_device *pdev) int num_lanes = ks_pcie->num_lanes; struct device *dev = &pdev->dev; + ks_release_restricted_dma(pdev); + pm_runtime_put(dev); pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); From patchwork Mon Aug 26 17:56:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 13778317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16F12C5472D for ; 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From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH 5/5] arm64: dts: ti: iot2050: Enforce DMA isolation for devices behind PCI RC Date: Mon, 26 Aug 2024 19:56:09 +0200 Message-ID: <270232f43d17c95610904928502ad00bb975304c.1724694969.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_105617_314132_82C547E2 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jan Kiszka Reserve a 64M memory region below the top of 1G RAM (smallest RAM size across the series, space left for firmware carve-outs) and ensure that all PCI devices do their DMA only inside that region. This is configured via a restricted-dma-pool and enforced with the help of the first PVU. Signed-off-by: Jan Kiszka --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index e76828ccf21b..cc0f33e3519c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -82,6 +82,11 @@ wdt_reset_memory_region: wdt-memory@a2200000 { reg = <0x00 0xa2200000 0x00 0x1000>; no-map; }; + + pci_restricted_dma_region: restricted-dma@ba000000 { + compatible = "restricted-dma-pool"; + reg = <0 0xba000000 0 0x4000000>; + }; }; leds { @@ -571,6 +576,10 @@ seboot-backup@e80000 { }; }; +&pcie0_rc { + memory-region = <&pci_restricted_dma_region>; +}; + &pcie1_rc { status = "okay"; pinctrl-names = "default"; @@ -580,6 +589,8 @@ &pcie1_rc { phys = <&serdes1 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy0"; reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + + memory-region = <&pci_restricted_dma_region>; }; &mailbox0_cluster0 { @@ -640,3 +651,24 @@ &mcu_r5fss0 { /* lock-step mode not supported on iot2050 boards */ ti,cluster-mode = <0>; }; + +&main_navss { + ti_pvu0: ti-pvu@30f80000 { + compatible = "ti,am654-pvu"; + reg = <0 0x30f80000 0 0x1000>, + <0 0x36000000 0 0x100000>; + reg-names = "cfg", "tlbif"; + interrupts-extended = <&intr_main_navss 390>; + interrupt-names = "pvu"; + }; + + ti_pvu1: ti-pvu@30f81000 { + compatible = "ti,am654-pvu"; + reg = <0 0x30f81000 0 0x1000>, + <0 0x36100000 0 0x100000>; + reg-names = "cfg", "tlbif"; + interrupts-extended = <&intr_main_navss 389>; + interrupt-names = "pvu"; + status = "disabled"; + }; +};