From patchwork Wed Mar 6 17:47:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10841503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D84F0180E for ; Wed, 6 Mar 2019 17:47:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF4172ED15 for ; Wed, 6 Mar 2019 17:47:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B23F22ED18; Wed, 6 Mar 2019 17:47:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B5792ED15 for ; Wed, 6 Mar 2019 17:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730542AbfCFRrO (ORCPT ); Wed, 6 Mar 2019 12:47:14 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:38263 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726178AbfCFRrN (ORCPT ); Wed, 6 Mar 2019 12:47:13 -0500 Received: by mail-pf1-f193.google.com with SMTP id n125so9180802pfn.5 for ; Wed, 06 Mar 2019 09:47:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wIDuHEQWfSGozqoJvBxHadpJ6Vo2hH3jLM6+B+AQsyw=; b=m9c5xwPsupNm+5WKr/xik3yQYkk684eFAEHpfPYj+fJ4wY5U00YBJ1ZgdIapAtUWWq tIqDYAqxVO+iuUYOiEnUAhkeKG4FC+hiiRUP1H6XMCOZjG7QcFyBJaiOrBpFXEcqa6Ox zn2iimma6tx4siCRfuV8/YIU/CmEp4BLUaEolK4IRT3HmK8FOluBW/E77EAf4YCL2YD9 hlGrgRNgFg/SvY9j8o1Tx5n2QnXeS+pmvDxjxAxkxOOGkn6js0FrOUd2xPRcoHZM1T1r oSqGH27WZKUOF3NlIRvuVaN70rlxmAj0IV7JcH1C/hwjLrhmQfquLVFdnYhxVpgtJVZA r6iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wIDuHEQWfSGozqoJvBxHadpJ6Vo2hH3jLM6+B+AQsyw=; b=DOgvTWDgwqzv70DPQ3crscVDCVWEEGA845W4QBrnbiAdS8blRzxE8OjRyYaGC47aLl eIKXPBvQZ6ZjGj+/w9FIhhacEtHzGdZvZPkF+nErWkUOspQqZMU6VjK+qcGvWzZYI+wG 8KmogIZjnxAMBtcbOMMNpFx2C96DFd9DsRPkMy0f6viL1DJ8TQLn14mouN9i+s/KzCRi BT4aa3gunyslMKnn9KP1bi9HNfXZ5xLaV82Jc2D596pTuMAXg4ZBN99DQ/eHzrHMMHUF GXpWwBYFIbUPysUISEJlpfaqBVau7kgf8NLF6hG7V5FrTKSbIpKkJtg+FMdPY2oFHcdD 3zXQ== X-Gm-Message-State: APjAAAW9QSUo48O3bSVKGPz1p0zR1fJDKmgasLcE90v01OQrF7Tum/ll 8l9cyKTEndEV9tOTm5bXd1J69Q== X-Google-Smtp-Source: APXvYqz8MQI+57gbd4zxGupvAhLXk3KOkqf2tRVq/TAunyHqBfXgiU0B1rdL+64pc0N4ezLNKz7pSA== X-Received: by 2002:aa7:8299:: with SMTP id s25mr8435662pfm.56.1551894432472; Wed, 06 Mar 2019 09:47:12 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id h64sm4098293pfj.40.2019.03.06.09.47.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 09:47:11 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: clock: Introduce Qualcomm Turing Clock controller Date: Wed, 6 Mar 2019 09:47:56 -0800 Message-Id: <20190306174758.22462-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190306174758.22462-1-bjorn.andersson@linaro.org> References: <20190306174758.22462-1-bjorn.andersson@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add devicetree binding for the turing clock controller found in QCS404. Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../bindings/clock/qcom,turingcc.txt | 19 +++++++++++++++++++ .../dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,turingcc.txt create mode 100644 include/dt-bindings/clock/qcom,turingcc-qcs404.h diff --git a/Documentation/devicetree/bindings/clock/qcom,turingcc.txt b/Documentation/devicetree/bindings/clock/qcom,turingcc.txt new file mode 100644 index 000000000000..126517de5f9a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,turingcc.txt @@ -0,0 +1,19 @@ +Qualcomm Turing Clock & Reset Controller Binding +------------------------------------------------ + +Required properties : +- compatible: shall contain "qcom,qcs404-turingcc". +- reg: shall contain base register location and length. +- clocks: ahb clock for the TuringCC +- #clock-cells: from common clock binding, shall contain 1. +- #reset-cells: from common reset binding, shall contain 1. + +Example: + turingcc: clock-controller@800000 { + compatible = "qcom,qcs404-turingcc"; + reg = <0x00800000 0x30000>; + clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h new file mode 100644 index 000000000000..838faef57c67 --- /dev/null +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Linaro Ltd + */ + +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +#define _DT_BINDINGS_CLK_TURING_QCS404_H + +#define TURING_Q6SS_Q6_AXIM_CLK 0 +#define TURING_Q6SS_AHBM_AON_CLK 1 +#define TURING_WRAPPER_AON_CLK 2 +#define TURING_Q6SS_AHBS_AON_CLK 3 +#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 + +#endif From patchwork Wed Mar 6 17:47:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10841501 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 572FE1575 for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h64sm4098293pfj.40.2019.03.06.09.47.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 09:47:13 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] clk: qcom: branch: Add AON clock ops Date: Wed, 6 Mar 2019 09:47:57 -0800 Message-Id: <20190306174758.22462-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190306174758.22462-1-bjorn.andersson@linaro.org> References: <20190306174758.22462-1-bjorn.andersson@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some clocks can only be turned on by resetting the block containing them, provide a clock type that allow us to reference these clocks and have the client drivers enable and "disable" them. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-branch.c | 6 ++++++ drivers/clk/qcom/clk-branch.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 99446bf630aa..f869fc6aaed6 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -146,6 +146,12 @@ const struct clk_ops clk_branch2_ops = { }; EXPORT_SYMBOL_GPL(clk_branch2_ops); +const struct clk_ops clk_branch2_aon_ops = { + .enable = clk_branch2_enable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_aon_ops); + const struct clk_ops clk_branch_simple_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index b3561e0a3984..17a58119165e 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -40,6 +40,7 @@ struct clk_branch { extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; +extern const struct clk_ops clk_branch2_aon_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr) From patchwork Wed Mar 6 17:47:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10841499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC7581575 for ; Wed, 6 Mar 2019 17:47:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B9512ED0C for ; Wed, 6 Mar 2019 17:47:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F9A82ED13; Wed, 6 Mar 2019 17:47:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1F1A2ED0C for ; Wed, 6 Mar 2019 17:47:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730544AbfCFRrR (ORCPT ); Wed, 6 Mar 2019 12:47:17 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:47028 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730549AbfCFRrQ (ORCPT ); Wed, 6 Mar 2019 12:47:16 -0500 Received: by mail-pf1-f195.google.com with SMTP id g6so9176842pfh.13 for ; Wed, 06 Mar 2019 09:47:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mQqRiUcOBnf84owwha1uaK826K7g8AcK1SIu5pAC4cY=; b=yKRcvIa0DkIaHDQxu1z4+ypdBKlq6eamk8w3W+jcg+s/8cpAdwFSARvx0egLS8JL9H CS5/NHTedguwCIt/3AZXEEz771qMkyNa9+v3m1OPfHKieGPNy6hu/mkB56br8ECcPCBG nZCD2YaZHUyT2m9TdqPwgtyaV4p/akJPn4w1OtEDmKs3JWjP+q94mz0DNHu8EliWVcqs 9IT/28u0wylN6Dg6CFlNW0GCyIujGYNWx5iA+AbYA/y3hML9THBqby78VVc0NNKnKcP7 nkzJzPfIzzUAeP2Fp4Jt7ZUEn1lKM3jBbBlDC7Ix5DMcCynV8uCGyMhwKzlCayCMvCEC oCuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mQqRiUcOBnf84owwha1uaK826K7g8AcK1SIu5pAC4cY=; b=jcUTvj+tlsqOFTLZaJTV8pMAzuaGURv+twNQ3uUC7t1XvgkjXj+jvPTvwvp+iSDzID w/6zPGnkaQJKd0E8LRb+7Z/hv0H6BC9ZpwSmXGNGGzg/YctU2Erl2XZFwuUnk7wwFjQd C5oenWmpB5PWslcCG/RijNyR8UKxMvEvJAl+zNGnJbdNAx6L6CujpVqYUr1meJtMdwsD lS/KrKki5Ur4bPPwllR3o0tyrC8HZZ52PoHxV8lVOVnL6TIURY4XF06LXaqp8hzTRdJq ifMydwcEsA8U/ufVNL536g6ZDziUdQ+uUquP1qtpyUsUdQMZ/6EOU4heVjxffxYEOYmR Pq7Q== X-Gm-Message-State: APjAAAUP0ByK5ynxQlAUVSPhS0VsSaPzRcKxHFS0vtjWLmPthLjR5jgD u3wrM4J48fTunREIwqbEnYk7lQ== X-Google-Smtp-Source: APXvYqyoyy8QD4QZPgCyvUZnyDFGKoidnJexwhZekrgpy3BMswO/hlD4V1uBvgGFEupbUzqGhOxTyw== X-Received: by 2002:a62:20c9:: with SMTP id m70mr8297130pfj.118.1551894434669; Wed, 06 Mar 2019 09:47:14 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id h64sm4098293pfj.40.2019.03.06.09.47.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 09:47:14 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] clk: qcom: Add QCS404 TuringCC Date: Wed, 6 Mar 2019 09:47:58 -0800 Message-Id: <20190306174758.22462-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190306174758.22462-1-bjorn.andersson@linaro.org> References: <20190306174758.22462-1-bjorn.andersson@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Turing Clock Controller provides resources related to running the Turing subsystem. PM runtime is used to ensure that the associated AHB clock is ticking while the clock framework is accessing the registers in the Turing clock controller. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/Kconfig | 6 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/turingcc-qcs404.c | 170 +++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 drivers/clk/qcom/turingcc-qcs404.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1c04575c118f..18bdf34d5e64 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -243,6 +243,12 @@ config SDM_GCC_660 Say Y if you want to use peripheral devices such as UART, SPI, i2C, USB, UFS, SDDC, PCIe, etc. +config QCS_TURING_404 + tristate "QCS404 Turing Clock Controller" + help + Support for the Turing Clock Controller on QCS404, provides clocks + and resets for the Turing subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ee8d0698e370..f0768fb1f037 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o +obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c new file mode 100644 index 000000000000..aa859e6ec9bd --- /dev/null +++ b/drivers/clk/qcom/turingcc-qcs404.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" +#include "reset.h" + +static struct clk_branch turing_wrapper_aon_cbcr = { + .halt_reg = 0x5098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "turing_wrapper_aon_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch turing_q6ss_ahbm_aon_cbcr = { + .halt_reg = 0x9000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "turing_q6ss_ahbm_aon_cbcr", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch turing_q6ss_q6_axim_clk = { + .halt_reg = 0xb000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "turing_q6ss_q6_axim_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch turing_q6ss_ahbs_aon_cbcr = { + .halt_reg = 0x10000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "turing_q6ss_ahbs_aon_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch turing_wrapper_qos_ahbs_aon_cbcr = { + .halt_reg = 0x11014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) { + .name = "turing_wrapper_qos_ahbs_aon_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_regmap *turingcc_clocks[] = { + [TURING_WRAPPER_AON_CLK] = &turing_wrapper_aon_cbcr.clkr, + [TURING_Q6SS_AHBM_AON_CLK] = &turing_q6ss_ahbm_aon_cbcr.clkr, + [TURING_Q6SS_Q6_AXIM_CLK] = &turing_q6ss_q6_axim_clk.clkr, + [TURING_Q6SS_AHBS_AON_CLK] = &turing_q6ss_ahbs_aon_cbcr.clkr, + [TURING_WRAPPER_QOS_AHBS_AON_CLK] = &turing_wrapper_qos_ahbs_aon_cbcr.clkr, +}; + +static const struct regmap_config turingcc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x30000, + .fast_io = true, +}; + +static const struct qcom_cc_desc turingcc_desc = { + .config = &turingcc_regmap_config, + .clks = turingcc_clocks, + .num_clks = ARRAY_SIZE(turingcc_clocks), +}; + +static int turingcc_probe(struct platform_device *pdev) +{ + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + ret = qcom_cc_probe(pdev, &turingcc_desc); + if (ret < 0) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int turingcc_remove(struct platform_device *pdev) +{ + pm_clk_destroy(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct dev_pm_ops turingcc_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static const struct of_device_id turingcc_match_table[] = { + { .compatible = "qcom,qcs404-turingcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, turingcc_match_table); + +static struct platform_driver turingcc_driver = { + .probe = turingcc_probe, + .remove = turingcc_remove, + .driver = { + .name = "qcs404-turingcc", + .of_match_table = turingcc_match_table, + .pm = &turingcc_pm_ops, + }, +}; + +module_platform_driver(turingcc_driver); + +MODULE_DESCRIPTION("Qualcomm QCS404 Turing Clock Controller"); +MODULE_LICENSE("GPL v2");