From patchwork Fri Aug 30 20:30:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785533 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB931BFDF6; Fri, 30 Aug 2024 20:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050102; cv=none; b=bT60Sxn2f0wZLbjdQdIs83lbP9mUf8VNTeJ2KpLfoX1tzJl0b+52t3FTA2ypalWt3mCm88tJ1mHHFYrp4QtLvd21BA9eBoNv5gmYZm3m8j2aT/pmrbJIJc0f0FiMfa0GfRGCM4k+euEzWlbkqqd4+ktnS/FJdZ/S8LunFjr/rYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050102; c=relaxed/simple; bh=lYkTEnnPcCugk/nsalm6Op60l/MgYrq9QArPuUxn8c0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lMhLBaYHpFDK72fm3zwsX1CnaBUVJ4a7dU3ODCbOGiBGbOJYUZGWKPoRGdhlnyUlOu5K0Fj3DZ4jWVzM7Vc/hGlATlqsMIi7yEaLIfIDYxkGC5CKDYvQwSncpBhZe37S7xiCF8V6HCRE79xq2yXKR5AvxuBaqcbgslMKt60GonU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=te/QhY/+; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=XMGj6izn; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="te/QhY/+"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="XMGj6izn" Received: from phl-compute-03.internal (phl-compute-03.nyi.internal [10.202.2.43]) by mailfhigh.nyi.internal (Postfix) with ESMTP id AEC04114017B; Fri, 30 Aug 2024 16:34:58 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-03.internal (MEProxy); Fri, 30 Aug 2024 16:34:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050098; x=1725136498; bh=+LzqbnOSHKHcDTgCNDGqaKM+uDKxUJO9P7aNNgkMlRU=; b= te/QhY/+e6CpMMPmvZ+b9BC8I+5TDo9TyvYNNrd94RchngOcMKPgqhoxyFZOsdnF hjyimkN7Bkl3zNNFBUzo3wK62U7ECjrvBpOA1747DHa+Q8rCa946jsNtT1QKfWp2 g85qEJU2JTk2uiaSW7xP2lKgFhlZz6nCEY5qD6NiNnfWBzCMO0CR6hvRZ91LQMM8 O2U+H9AfbzhZhVC5HOnrPIkQNSPS4sHC+6+ErjvX9NX3jTfg0OvYmY+BayO8o2Zn KZJuiwpH6eeBW2YEAkltiqFrkAeZsoqipUZkvKrWfxhyb1XF1g4o30/6Llq0hr1w B67O/mmpLVh9g+dNSQyLCA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050098; x= 1725136498; bh=+LzqbnOSHKHcDTgCNDGqaKM+uDKxUJO9P7aNNgkMlRU=; b=X MGj6iznroT4WQaOpo9irxwd1WUDQG5CnizCGNsMA8QnwNpFiRzpImdRjSpxi5iM+ muPVY3ght9mHWAKXaPvW7G8/akzqqBCXacJQErfVI6e/LrLMNIWuy18C0qouXRF7 7nW8yWYgGWGtGORUhhSYylMMM1fT4kWzilo3bbOTpxOCkKGvCt4zROQfhSBb+ZnK YjBAzPULJ8jkZdHBUHTmrQ8VXhP54tqOdNABfCAyxX651CjWJPRAAnohISYTZRVP UOo0vvr8EHKFXPnQMNKp+PVrO1b4oF7is5rk/ZpnIvSoqcp2SGddC++v0MInT73l 7rlkInV5GNIN3BicFZTBw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudeglecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddvpdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:34:58 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= , Conor Dooley Subject: [PATCH v2 1/8] dt-bindings: media: renesas,csi2: Add binding for V4M Date: Fri, 30 Aug 2024 22:30:57 +0200 Message-ID: <20240830203104.3479124-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document support for the CSI-2 module in the Renesas V4M (r8a779h0) SoC. Signed-off-by: Niklas Söderlund Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- * changes since v1 - group with driver changes. --- Documentation/devicetree/bindings/media/renesas,csi2.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.yaml b/Documentation/devicetree/bindings/media/renesas,csi2.yaml index 977ab188d654..80b77875874d 100644 --- a/Documentation/devicetree/bindings/media/renesas,csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,csi2.yaml @@ -32,6 +32,7 @@ properties: - renesas,r8a77990-csi2 # R-Car E3 - renesas,r8a779a0-csi2 # R-Car V3U - renesas,r8a779g0-csi2 # R-Car V4H + - renesas,r8a779h0-csi2 # R-Car V4M reg: maxItems: 1 From patchwork Fri Aug 30 20:30:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785534 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fout7-smtp.messagingengine.com (fout7-smtp.messagingengine.com [103.168.172.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DFC81C0DC5; Fri, 30 Aug 2024 20:35:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050103; cv=none; b=UyGsgUcTtM+7oOvYDre2YfdT79r96sA/tx7XJ5pI1omIaL1hVsV34DOHc5R0j9rh10lJVAmP9g/l7gaizkTkab7/i7JkkTE6Fhwppwdyb5Zd4cLW2V9EQJWoKJLGFPIIVBfNPWmCHOsYWVQ6u4M10A7yr3rTV3MycRIehL71BhQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050103; c=relaxed/simple; bh=Z5GIt5f7DPb9bQmjJjU/GaAtvD913pig2jxGXRbpouw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h8ZVRr9LTB3hACYVA4CGcnj+WR5XYMWxmwqBUFV8zyFJIpKydqPczWcWdsjnAxbqBgMGJCF97W4G91qgGI21TTACXr0UM/R1a3EIBdshAQixPNvq7kPqu/yBngy8YJ7nYJ5ACjYfmURHtpKfnnwPF1KYyXoaQNxQPbnZRZKLbHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=rXh5WBt9; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=mXYDpHop; arc=none smtp.client-ip=103.168.172.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="rXh5WBt9"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="mXYDpHop" Received: from phl-compute-08.internal (phl-compute-08.nyi.internal [10.202.2.48]) by mailfout.nyi.internal (Postfix) with ESMTP id A64501380132; Fri, 30 Aug 2024 16:35:00 -0400 (EDT) Received: from phl-mailfrontend-02 ([10.202.2.163]) by phl-compute-08.internal (MEProxy); Fri, 30 Aug 2024 16:35:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050100; x=1725136500; bh=QutUibBOlYFAkhIbQp9z+y9Dh4f7NN8pOiY+Tkgf0i8=; b= rXh5WBt9ibvyXwYAZ0Wywn5ywzb/A32K8n98W+cEofRwPC+mP4VA+CNoY5kc3qQL U/9axckz7N2LUj+q4/Eddapxz8ta9+2vF+zYBybz8ZhrZKq++3hsIKhAz7qhJJxD 9Knp62qe5vv0FMuWo13m8mRIu+OcAXHxHL8hQ4X42QWp8TCA8+1prUGF1xE5GIyf 2dPfX66mQOMLEd7wljKACdBC4C4VpQuIA4nG8YS7RNTxDHlJpIrWWR6VOeiw0p6X GtRQirrX2aqAzC8FROGYW6zDlKfpn5IPS4lzyRfxohC4Py2jgEtvaM5HYvlyk6xr 5sAARfX6BtS9/wm/8S8jmA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050100; x= 1725136500; bh=QutUibBOlYFAkhIbQp9z+y9Dh4f7NN8pOiY+Tkgf0i8=; b=m XYDpHoptVdV/H701bYgZAWqCQe0h/myFtymlvXGNQ3LkEgKm+7NlXSNji0oQ7ljR w52oby9Q0jWZvw63qrxtJOowu0ohWK/R5asOzcaKW/O7vnExhSZl/iQY7+JUJzi+ CqX4838Rtlm9JZjdXVqY14u6cAhz/Ea+v8btlGxGGKny568Ge0ZQgeWHu4f+BEV9 FV5/fL7H2lJmPNHLZxGnXlniRRaaAUFLy5r9oTk5Jck2kMZ8Yk50F7H0xi3Xc8CS ERSvfFzvVnIQwAMV4EVU0hLKSW9uDWsPK5omMdfylcJyJ8A3Kgs8USplS+Frq21j Vx5L6WaCtchelyvEJpqRQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudeglecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:00 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 2/8] media: rcar-csi2: Correct field size for PHTW writes Date: Fri, 30 Aug 2024 22:30:58 +0200 Message-ID: <20240830203104.3479124-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The data and code written thru the Test Interface Write Register (PHTW) register are 8-bit wide, change the datatype used to reflect this. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index c419ddb4c5a2..932826ee0961 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -238,13 +238,13 @@ static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { }; struct phtw_value { - u16 data; - u16 code; + u8 data; + u8 code; }; struct rcsi2_mbps_reg { u16 mbps; - u16 reg; + u8 reg; }; static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = { @@ -1451,7 +1451,7 @@ static int rcsi2_parse_dt(struct rcar_csi2 *priv) * NOTE: Magic values are from the datasheet and lack documentation. */ -static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code) +static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) { unsigned int timeout; @@ -1488,7 +1488,7 @@ static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, } static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, - const struct rcsi2_mbps_reg *values, u16 code) + const struct rcsi2_mbps_reg *values, u8 code) { const struct rcsi2_mbps_reg *value; const struct rcsi2_mbps_reg *prev_value = NULL; From patchwork Fri Aug 30 20:30:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785535 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15BF1C0DC4; Fri, 30 Aug 2024 20:35:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050105; cv=none; b=MChvrWw42lZPhYcdOjDJ2spFDb1lY9NNDNHEDviSpkMXd8wb4wsyExHAldGKfdQccG/Zz6gAqqrz5neL/VEW/sR6Yb9afHfU9qNoM8msj0/CbLPyzia0h6d/OwWqjM/QIwIQj1t6s3N2Uo5gqLxMvIQK/U6ZC0xk0bRDQdXvTh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050105; c=relaxed/simple; bh=RusLnnzXe0jlX36BmL8KW2HQb+8KMlD3M2aMYkJLfeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FuCcsqdbTpMYwdLayDZSrWxvojoZQd2jspUy8Ff3GKpd5lx89gk5lFSFccQfOjSbKMzO5ddu28TuB9V5cuNF+14wkPcg5QsezdDNEKJYpEBfYineolIfS6w6C/yDeYieQXS5NyOstPPPDzFxS9zSqvJ1K+yZTOI0mbbshte0wmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=qZ/J0GNn; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=jRPDSfGy; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="qZ/J0GNn"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="jRPDSfGy" Received: from phl-compute-03.internal (phl-compute-03.nyi.internal [10.202.2.43]) by mailfhigh.nyi.internal (Postfix) with ESMTP id B11F41140181; Fri, 30 Aug 2024 16:35:02 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-03.internal (MEProxy); Fri, 30 Aug 2024 16:35:02 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050102; x=1725136502; bh=zVPJjWpyJz870XcHiD2OTc0eZoFvRtxahIqTo+Tan/A=; b= qZ/J0GNnniPzrlSi07Wwbxm3H3iX0z+d3bVWuso1BA80t1DmclTv+WImXWcAh/t6 tiU/rujRwe35QG4mNkTl3WWRv2wVNMjD+kWMgS+Hd33XanjZOw+K24GcC2v8WeDK GEAevyvQ4gpM4lSDuFPC5Oi5pGbVb8uukVU/zyCQubnLk+Rr/ZR/Nx5qu7wq4ptS KEwVtAEDq2hVwuOfkm1jcPigG3KDXWZ3+va9KZwf7klnv63MgbDkEMeU7L394/uQ wCTxRBApzH3c6q87f5nElM/As7LULNRxrVcjoW/yAXlMhFm6F+xHbgV5s80/mXeA /H/TKhaxzxq9Cvd7rHcn4A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050102; x= 1725136502; bh=zVPJjWpyJz870XcHiD2OTc0eZoFvRtxahIqTo+Tan/A=; b=j RPDSfGyxosqMqhklT3O79JJX7O+rwVuuYa9MrFKMklUnO3fePIbITzBFRoX03GXX dzr9F7JMwAYbRdOaOZhIODNIL2qlPqwg5om/KSCS8+2IRiG7RS01ZQ/7mAcFkrWf /qTDx1htDF1XAwwLu/IhlbPDyk4qJun1qKf0tHAEKgyduNyIGgQ/zpqweR2JQNyz ryqpwB4ruBsMqdXO0aLjqE27TKfseiNQrB+CaHvu44trBcZADNJB+oPPaxemMAlV TUNvonfddhx2oWJI1Ehk+Ydnf+se99w2k47qaKDy1nGWVjRHNjTq/+lzLS1Geo3k CId5U336RPrvVyZ0ALFKQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudeglecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:02 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 3/8] media: rcar-csi2: Allow writing any code and data value to PHTW Date: Fri, 30 Aug 2024 22:30:59 +0200 Message-ID: <20240830203104.3479124-4-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The helper to write an array of code and data values to the PHY Test Interface Write Register (PHTW) register uses the case where both code and data are zero as an exit condition. This prevents writing data = 0 and code = 0 to the register. Up until now this has been OK as no such combination where needed, and it was a convenient exit condition. In future writing data = 0 and code = 0 to the PHTW register will be needed. Avoid using an exit condition when writing an array of PHTW values and instead pass the length of the array to the helper. This allows any combination of code and data to be written. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 29 ++++++++-------------- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 932826ee0961..5ab19f94fcde 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -1473,13 +1473,13 @@ static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) } static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, - const struct phtw_value *values) + const struct phtw_value *values, + unsigned int size) { - const struct phtw_value *value; int ret; - for (value = values; value->data || value->code; value++) { - ret = rcsi2_phtw_write(priv, value->data, value->code); + for (unsigned int i = 0; i < size; i++) { + ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); if (ret) return ret; } @@ -1520,7 +1520,6 @@ static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, { .data = 0x11, .code = 0xe4 }, { .data = 0x01, .code = 0xe5 }, { .data = 0x10, .code = 0x04 }, - { /* sentinel */ }, }; static const struct phtw_value step2[] = { @@ -1529,12 +1528,11 @@ static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, { .data = 0x4b, .code = 0xac }, { .data = 0x03, .code = 0x00 }, { .data = 0x80, .code = 0x07 }, - { /* sentinel */ }, }; int ret; - ret = rcsi2_phtw_write_array(priv, step1); + ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); if (ret) return ret; @@ -1549,7 +1547,7 @@ static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, return ret; } - return rcsi2_phtw_write_array(priv, step2); + return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); } static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) @@ -1575,10 +1573,9 @@ static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) { .data = 0xee, .code = 0x54 }, { .data = 0xee, .code = 0x84 }, { .data = 0xee, .code = 0x94 }, - { /* sentinel */ }, }; - return rcsi2_phtw_write_array(priv, step1); + return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); } static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, @@ -1587,20 +1584,17 @@ static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, /* In case of 1500Mbps or less */ static const struct phtw_value step1[] = { { .data = 0xcc, .code = 0xe2 }, - { /* sentinel */ }, }; static const struct phtw_value step2[] = { { .data = 0x01, .code = 0xe3 }, { .data = 0x11, .code = 0xe4 }, { .data = 0x01, .code = 0xe5 }, - { /* sentinel */ }, }; /* In case of 1500Mbps or less */ static const struct phtw_value step3[] = { { .data = 0x38, .code = 0x08 }, - { /* sentinel */ }, }; static const struct phtw_value step4[] = { @@ -1608,29 +1602,28 @@ static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, { .data = 0x4b, .code = 0xac }, { .data = 0x03, .code = 0x00 }, { .data = 0x80, .code = 0x07 }, - { /* sentinel */ }, }; int ret; if (mbps != 0 && mbps <= 1500) - ret = rcsi2_phtw_write_array(priv, step1); + ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); else ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); if (ret) return ret; - ret = rcsi2_phtw_write_array(priv, step2); + ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); if (ret) return ret; if (mbps != 0 && mbps <= 1500) { - ret = rcsi2_phtw_write_array(priv, step3); + ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); if (ret) return ret; } - ret = rcsi2_phtw_write_array(priv, step4); + ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4)); if (ret) return ret; From patchwork Fri Aug 30 20:31:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785536 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fout7-smtp.messagingengine.com (fout7-smtp.messagingengine.com [103.168.172.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A44801BF33D; Fri, 30 Aug 2024 20:35:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.150 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050107; cv=none; b=GEkqJLcq5Vp0+9/2B37CV4IlQFJwpvNR15nTFTlP4V83E3/Hn3RS0ihAW5TXQgIyLFrWkH7WfyM+6CYdCsMjQxuUI1v+uETKGUnn7Zmdz+C0eLJC12p+dr3YYzNyY23VbnxgsIBP1ejBmWmprX5AbAZEA9po/tWwlIvSHvfTl4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050107; c=relaxed/simple; bh=WUNz6y4voRiI4lcnqrqaRmOZ30otXWdyqupORu7kRh8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mIMCkMPn9pFZ4nlSV3DLA35PJCMHejfOOKeQgbjLaHslw+AMd5lBRqYC+sTnfau7nn7M2dlAwt39a5zdD7M/VBZhDM0WowYV00t0FoPxEPSFrJVhIIOL+a0VKjr0yfYjcOQ2y5VATpC/0XAFsDgiWqfBLzH9QcIUiKtnQKEiBfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=fodV0kkp; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=W2xKvBgf; arc=none smtp.client-ip=103.168.172.150 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="fodV0kkp"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="W2xKvBgf" Received: from phl-compute-01.internal (phl-compute-01.nyi.internal [10.202.2.41]) by mailfout.nyi.internal (Postfix) with ESMTP id ABDB913802B6; Fri, 30 Aug 2024 16:35:04 -0400 (EDT) Received: from phl-mailfrontend-02 ([10.202.2.163]) by phl-compute-01.internal (MEProxy); Fri, 30 Aug 2024 16:35:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050104; x=1725136504; bh=G4r1nZQumfjbzcghcDspzxo9k7U5JAHA0SOW7OoBfxE=; b= fodV0kkpbftxYdILUpBagg0w9XkaciqSaw81YZnQCZwjKLMhjz8e4B+yVcOjqlME 0I4+hSt3iXelcqI3B98A2H4Y0cxZpQDJV0gK2Z4AjY8JYCJBLoYpARviSDAuR21C CPdcyZQZDSE+vRbsdUZiVM/naW6QCH9tiHC/A75pb0ATBhxoHsKHKWCT01uL+oOM L412NydOHy5BIAJFMgM2uu3mxNP8+ZsvpidhQ/7rFtNBLVxJth/Oqi3J+7xvhgCK vLRVXgDqA1SAkFsCFSmCDRb6rgga6qr0lfZtBx+nVfctpNAlUBHmIRTGv0JhAsXm /nu1D76ZTIrEsSwMcvFsUg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050104; x= 1725136504; bh=G4r1nZQumfjbzcghcDspzxo9k7U5JAHA0SOW7OoBfxE=; b=W 2xKvBgfK4hqz4GKSaARr234lGxd/b/SnE722xo7nTVK4hV0znYvuI9+hSS2mW0cI qemgrdZ2CmjGeqMS3q48yzHAPqeDhgp+J25dHvjP1+bKJgUdjZ7blgANsMPquuVk ccx6BHI+mYdPf0ar4WSPlrVykIRdpoYqdtgqyQeC8EPRTV4Yo3K5/u9GRm5dE8F6 +2sYJOxzHk28QtmNdxYvE0AccKBXbMRZiJjH1Z+t2d45AeB/93wciCGkYdnjYuQo GjdgjuXxL3NUFklnpMtuMO7IwvDbxuHerwOw3qozYvEF6FR+P924l5rv3zHsVMJt 9DT6QwGhzTJ7Km5ocNczg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudehtdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:04 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 4/8] media: rcar-csi2: Abstract PHTW and PHYPLL register offsets Date: Fri, 30 Aug 2024 22:31:00 +0200 Message-ID: <20240830203104.3479124-5-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Most of the registers used on the R-Car V4M CSI-2 IP are shared with the devices already supported by the rcar-csi2 driver. Two registers which function and layout are the same are however found on different offsets. Prepare for adding support for R-Car V4M by storing the offset to these two registers offsets in the device information structured. This way the code, which is shared between the devices, can be reused when V4M support is added. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 27 +++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 5ab19f94fcde..4e85c47817a1 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -584,7 +584,13 @@ enum rcar_csi2_pads { NR_OF_RCAR_CSI2_PAD, }; +struct rcsi2_register_layout { + unsigned int phtw; + unsigned int phypll; +}; + struct rcar_csi2_info { + const struct rcsi2_register_layout *regs; int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); int (*phy_post_init)(struct rcar_csi2 *priv); int (*start_receiver)(struct rcar_csi2 *priv, @@ -730,7 +736,7 @@ static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps))) hsfreq = hsfreq_prev; - rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg)); + rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(hsfreq->reg)); return 0; } @@ -1455,13 +1461,13 @@ static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) { unsigned int timeout; - rcsi2_write(priv, PHTW_REG, + rcsi2_write(priv, priv->info->regs->phtw, PHTW_DWEN | PHTW_TESTDIN_DATA(data) | PHTW_CWEN | PHTW_TESTDIN_CODE(code)); /* Wait for DWEN and CWEN to be cleared by hardware. */ for (timeout = 0; timeout <= 20; timeout++) { - if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN))) + if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) return 0; usleep_range(1000, 2000); @@ -1707,7 +1713,13 @@ static int rcsi2_probe_resources(struct rcar_csi2 *priv, return PTR_ERR_OR_ZERO(priv->rstc); } +static const struct rcsi2_register_layout rcsi2_registers_gen3 = { + .phtw = PHTW_REG, + .phypll = PHYPLL_REG, +}; + static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, @@ -1719,6 +1731,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_h3es2, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, @@ -1730,6 +1743,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { + .regs = &rcsi2_registers_gen3, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_m3w, @@ -1738,6 +1752,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { + .regs = &rcsi2_registers_gen3, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, .hsfreqrange = hsfreqrange_m3w, @@ -1746,6 +1761,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, @@ -1757,6 +1773,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_v3m_e3, .phy_post_init = rcsi2_phy_post_init_v3m_e3, .start_receiver = rcsi2_start_receiver_gen3, @@ -1766,6 +1783,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, @@ -1776,6 +1794,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_v3m_e3, .phy_post_init = rcsi2_phy_post_init_v3m_e3, .start_receiver = rcsi2_start_receiver_gen3, @@ -1785,6 +1804,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { + .regs = &rcsi2_registers_gen3, .init_phtw = rcsi2_init_phtw_v3u, .start_receiver = rcsi2_start_receiver_gen3, .enter_standby = rcsi2_enter_standby_gen3, @@ -1796,6 +1816,7 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { }; static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { + .regs = &rcsi2_registers_gen3, .start_receiver = rcsi2_start_receiver_v4h, .use_isp = true, .support_cphy = true, From patchwork Fri Aug 30 20:31:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785537 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6561C173B; Fri, 30 Aug 2024 20:35:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050109; cv=none; b=uIvRYgJsvlE22NP9ysPSrjzsfVWWJRhJ7XS2DJ20t0rHWHIxaK1O0jnJxrKa01th20CxJVDuzQCIXB6Xfc5Xis4M8a+ILd8Z9VqvTvrizJe5WGip5qLTR62Dv9nJPS8UzUfvhuk74WeM8AsWztupXLes/cnWidT8yInPvUOtEz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050109; c=relaxed/simple; bh=/n5UkoeE/vp7MTk2uKXXS64C5AW9fa/pnkY1YfYJs+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Qfw690VxTGwVKGzhwdawD/bf+nEuc8lBKXrpjVkraAVr3zZ7g2Z0ltdazZBtIoa41xYMZmtkyAWYlugifiN4QQvEAE9fPZTsBdRa0GZXxoJxYBH2YhUG8xQbK8BnPRrdLNY2njDcsWH/8+6jDDrLHSJbFhYlpADHA8QvjmnNNkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=cavgjqLx; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=QRoy+vMe; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="cavgjqLx"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="QRoy+vMe" Received: from phl-compute-07.internal (phl-compute-07.nyi.internal [10.202.2.47]) by mailfhigh.nyi.internal (Postfix) with ESMTP id A408F114017B; Fri, 30 Aug 2024 16:35:06 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-07.internal (MEProxy); Fri, 30 Aug 2024 16:35:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050106; x=1725136506; bh=tkfYQwWrFOZJjVqUVb3P3b9wwFzVkThikFf2mLvjjrs=; b= cavgjqLxJFoJ6/n7GL+Dz9AJNlDGKADjSqGwcO+H11TA/G8W6LiQz3PKVCj87e84 5MTOHvViEftpvlLv2dMAOdiDN1M9qHeTSxvzqL921zlcpgd3PgSp0/Gw1f3QLE/g dITK4DUByp+snyHGAx2Rw+OPP+iF5Ts4cArBvHOMGsnvEYWaec83Q6YQFjKQPLG0 qB+0NAKpEpsoA7ys1fQfG2oTEfwypxi3rBuDGdZpHIefCmJ0O0MYvCflZ1W3uL2c AD8iMjmVi5sZs63luZjN6xfsf0ZDu+dHoPMqkZAwJeyQ2/XKGmSe5D4kFGReXC2+ 5bNPb2D7g9CBWYgln61YRQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050106; x= 1725136506; bh=tkfYQwWrFOZJjVqUVb3P3b9wwFzVkThikFf2mLvjjrs=; b=Q Roy+vMe2P1DmDdDVVuNFIzA0v0nTMVPUUpX1iMAqK3S/HJPUcQcSbSAUi7Gj6D/o H9AWifP0jg8pvR3T/cNyHzoP+QaV/Hasc8Hq6CIbbGm5S/wtbjpHswhmjhM53gPH I4KRHfe/uPzJxjCJPJz0Vyq+V4Jnd3hhI9WGH/DVvck14UnTFhxUB/bkiR4DM8fd 59Te51kEkIb6tvTJuYseleYusykUkvRSdkwmVZC9lCo2MdEgg10K/4nipdbJaDCW S2TsDGKqiqHliChAEYPsLzQdRQdkxwiOJy2ih3TjzQYEY2jHOKlLXyhXrAjQvaKC cLs5kME6+I0BmlAhhmDbA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudeglecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:06 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 5/8] media: rcar-csi2: Add helper to lookup mbps settings Date: Fri, 30 Aug 2024 22:31:01 +0200 Message-ID: <20240830203104.3479124-6-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The structure mapping a configuration information to a particular mpbs setting needs to be extended with more information to support future SoCs. Before it is extended reduce code duplication by creating a helper to lookup information from an array of mbps setting, the lookup code has already been copied to two speared locations. While at it rename the structure to make it clear it contains information related to a mbps setting, not just a single register value. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 90 +++++++++++----------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 4e85c47817a1..0c65c6aa7260 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -242,12 +242,12 @@ struct phtw_value { u8 code; }; -struct rcsi2_mbps_reg { +struct rcsi2_mbps_info { u16 mbps; u8 reg; }; -static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = { +static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { { .mbps = 1500, .reg = 0xcc }, { .mbps = 1550, .reg = 0x1d }, { .mbps = 1600, .reg = 0x27 }, @@ -272,7 +272,7 @@ static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = { { /* sentinel */ }, }; -static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { +static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = { { .mbps = 80, .reg = 0x86 }, { .mbps = 90, .reg = 0x86 }, { .mbps = 100, .reg = 0x87 }, @@ -292,7 +292,7 @@ static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { { /* sentinel */ }, }; -static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { +static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = { { .mbps = 80, .reg = 0x00 }, { .mbps = 90, .reg = 0x20 }, { .mbps = 100, .reg = 0x40 }, @@ -336,7 +336,7 @@ static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { #define PHYPLL_REG 0x68 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) -static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = { +static const struct rcsi2_mbps_info hsfreqrange_v3u[] = { { .mbps = 80, .reg = 0x00 }, { .mbps = 90, .reg = 0x10 }, { .mbps = 100, .reg = 0x20 }, @@ -402,7 +402,7 @@ static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = { { /* sentinel */ }, }; -static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = { +static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = { { .mbps = 80, .reg = 0x00 }, { .mbps = 90, .reg = 0x10 }, { .mbps = 100, .reg = 0x20 }, @@ -449,7 +449,7 @@ static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = { { /* sentinel */ }, }; -static const struct rcsi2_mbps_reg hsfreqrange_m3w[] = { +static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { { .mbps = 80, .reg = 0x00 }, { .mbps = 90, .reg = 0x10 }, { .mbps = 100, .reg = 0x20 }, @@ -596,7 +596,7 @@ struct rcar_csi2_info { int (*start_receiver)(struct rcar_csi2 *priv, struct v4l2_subdev_state *state); void (*enter_standby)(struct rcar_csi2 *priv); - const struct rcsi2_mbps_reg *hsfreqrange; + const struct rcsi2_mbps_info *hsfreqrange; unsigned int csi0clkfreqrange; unsigned int num_channels; bool clear_ulps; @@ -662,6 +662,34 @@ static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) iowrite16(data, priv->base + reg); } +static const struct rcsi2_mbps_info * +rcsi2_mbps_to_info(struct rcar_csi2 *priv, + const struct rcsi2_mbps_info *infotable, unsigned int mbps) +{ + const struct rcsi2_mbps_info *info; + const struct rcsi2_mbps_info *prev = NULL; + + if (mbps < infotable->mbps) + dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", + mbps, infotable->mbps); + + for (info = infotable; info->mbps != 0; info++) { + if (info->mbps >= mbps) + break; + prev = info; + } + + if (!info->mbps) { + dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); + return NULL; + } + + if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps))) + info = prev; + + return info; +} + static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) { rcsi2_write(priv, PHYCNT_REG, 0); @@ -714,29 +742,13 @@ static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) { - const struct rcsi2_mbps_reg *hsfreq; - const struct rcsi2_mbps_reg *hsfreq_prev = NULL; + const struct rcsi2_mbps_info *info; - if (mbps < priv->info->hsfreqrange->mbps) - dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", - mbps, priv->info->hsfreqrange->mbps); - - for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) { - if (hsfreq->mbps >= mbps) - break; - hsfreq_prev = hsfreq; - } - - if (!hsfreq->mbps) { - dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); + info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); + if (!info) return -ERANGE; - } - if (hsfreq_prev && - ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps))) - hsfreq = hsfreq_prev; - - rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(hsfreq->reg)); + rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg)); return 0; } @@ -1494,27 +1506,15 @@ static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, } static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, - const struct rcsi2_mbps_reg *values, u8 code) + const struct rcsi2_mbps_info *values, u8 code) { - const struct rcsi2_mbps_reg *value; - const struct rcsi2_mbps_reg *prev_value = NULL; + const struct rcsi2_mbps_info *info; - for (value = values; value->mbps; value++) { - if (value->mbps >= mbps) - break; - prev_value = value; - } - - if (prev_value && - ((mbps - prev_value->mbps) <= (value->mbps - mbps))) - value = prev_value; - - if (!value->mbps) { - dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); + info = rcsi2_mbps_to_info(priv, values, mbps); + if (!info) return -ERANGE; - } - return rcsi2_phtw_write(priv, value->reg, code); + return rcsi2_phtw_write(priv, info->reg, code); } static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, From patchwork Fri Aug 30 20:31:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785538 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB7D1C173A; Fri, 30 Aug 2024 20:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050111; cv=none; b=loNHQXP1PmnqbhNHHbdp+aFHW54MWd7NydqHsUPKznBIl/zhBe/jhCNXtSBAb/U2TePc9WgOTXdDT5fwz8K1dq1Yhufs5ixwmnz8KYJbQBUfVitbBbSrfZl2HRxR+0NTAvymYRyYhQOkr7LpVZIJcAe9fMzTqIJa+OikfGWO5kk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050111; c=relaxed/simple; bh=APSWh4mIXesIjwqaDvndgsOoJ0YBwIPQm7iGLeXVTtY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z/EoZQAo76Y69hVYYtkemUOssxlDoefg2na1SioxcXdOooaHFe22/lB3sTqp+813+wNlE1k9IqXJ4FRU5si8mMboSRucf8kkug6nVWY7gMZujPwyPJDSH4UeBdF+btu0olYkx2KHqgd/+n/cKEpUDIyD216D2CQqI9cz0xZn1xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=wTRcO6cL; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=ok0CTyLc; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="wTRcO6cL"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="ok0CTyLc" Received: from phl-compute-01.internal (phl-compute-01.nyi.internal [10.202.2.41]) by mailfhigh.nyi.internal (Postfix) with ESMTP id 96E80114017A; Fri, 30 Aug 2024 16:35:08 -0400 (EDT) Received: from phl-mailfrontend-02 ([10.202.2.163]) by phl-compute-01.internal (MEProxy); Fri, 30 Aug 2024 16:35:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050108; x=1725136508; bh=i4gRbM1pSVE2qzmXjU5zUsyD19N0QlayHIRtkAwZWrM=; b= wTRcO6cLs0qhV2PI0JPBSNWAQC8Dzmpvkm0IEioBfT8XUdDMBzaphrDdaLZ+LBjT M1q0u7Ub8otvNPsg/UwubJO4lNcy6e+g+YzGNpLwqLnD9xdDFn9tjfIulN/4BILz HcKlvRriH+/JeTuSFBy7E6RxsjJbO7UEg54cTZxF4jNlrcPXoqAqg0NjfygMWLQw 9FVt3cgayyjGYLhuzXzsTMlgjBqqL4Fvrj/FYMkM4XNZxqINIaYfltuYIAaBDIoY d/GVgUIliB4OOYYjkU1yzeV+ifwI3cDQCx0gyraNP0Fncz4ClkJMT7ecPRlyzbgw fNWngQDSfwHVPYK7di5bGw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050108; x= 1725136508; bh=i4gRbM1pSVE2qzmXjU5zUsyD19N0QlayHIRtkAwZWrM=; b=o k0CTyLcaNEz2pjmrW/ss1jqNyusz+42WpCgw+ap8Tu1d98kO2hQkwySiQtgyKHMa rIRQREQta+62BztnfP2ixKOpPdxMbZ8XthdkAlqPcs8BsM2I9Y25ap7PH+ghJUJw k5Xw3bWhxH2W+gtIgXsEr02Ni/nXqD5xAoH89UeO8u8wGH/qOfvwMSIHMXtlqrDF DlqByurS5tqvLgQHu0uBYKaqiBPiwMXGZqscVLVF9zyReO2rfwt6js2sEeO0riUm 5jT3JWUcdzpUnzuV9k82JImXp3d3cF6dMqY9z9x+PJIhUAANCt71P9fCiG37t0aO xG6XYplj9X0mvbNUO16pw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudehtdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:08 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 6/8] media: rcar-csi2: Move PHTW write helpers Date: Fri, 30 Aug 2024 22:31:02 +0200 Message-ID: <20240830203104.3479124-7-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Prepare for V4M support by moving the PHTW write helpers to the generic write helpers. This is needed as adding V4M support will involve interact with the PHTW register from code that are logically grouped with similar code in such a way that forward declarations of these helpers would otherwise be needed. The functions are moved verbatim. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 72 +++++++++++----------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 0c65c6aa7260..72fcb6ac840b 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -662,6 +662,42 @@ static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) iowrite16(data, priv->base + reg); } +static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) +{ + unsigned int timeout; + + rcsi2_write(priv, priv->info->regs->phtw, + PHTW_DWEN | PHTW_TESTDIN_DATA(data) | + PHTW_CWEN | PHTW_TESTDIN_CODE(code)); + + /* Wait for DWEN and CWEN to be cleared by hardware. */ + for (timeout = 0; timeout <= 20; timeout++) { + if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) + return 0; + + usleep_range(1000, 2000); + } + + dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); + + return -ETIMEDOUT; +} + +static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, + const struct phtw_value *values, + unsigned int size) +{ + int ret; + + for (unsigned int i = 0; i < size; i++) { + ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); + if (ret) + return ret; + } + + return 0; +} + static const struct rcsi2_mbps_info * rcsi2_mbps_to_info(struct rcar_csi2 *priv, const struct rcsi2_mbps_info *infotable, unsigned int mbps) @@ -1469,42 +1505,6 @@ static int rcsi2_parse_dt(struct rcar_csi2 *priv) * NOTE: Magic values are from the datasheet and lack documentation. */ -static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) -{ - unsigned int timeout; - - rcsi2_write(priv, priv->info->regs->phtw, - PHTW_DWEN | PHTW_TESTDIN_DATA(data) | - PHTW_CWEN | PHTW_TESTDIN_CODE(code)); - - /* Wait for DWEN and CWEN to be cleared by hardware. */ - for (timeout = 0; timeout <= 20; timeout++) { - if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) - return 0; - - usleep_range(1000, 2000); - } - - dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); - - return -ETIMEDOUT; -} - -static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, - const struct phtw_value *values, - unsigned int size) -{ - int ret; - - for (unsigned int i = 0; i < size; i++) { - ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); - if (ret) - return ret; - } - - return 0; -} - static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, const struct rcsi2_mbps_info *values, u8 code) { From patchwork Fri Aug 30 20:31:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785539 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 685B21C173B; Fri, 30 Aug 2024 20:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050113; cv=none; b=ZEqNb6YzdBANX9yso31bOy3kINR0KIqHDIdy2bFOFV+3vcTlCaPVzQaAQ1L6lKN2c/P0Hmnt9tdkTHSAkSGzHYZGfO7Rn9iG1HJh4vixAQwlCCzMV3hGAbTwKHo5jU7Lx47aJmlG/Xj8PgYa2b+GlbDV58RulkoJX16Lvd1WqvM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050113; c=relaxed/simple; bh=pKj2UMrtgtkN9tEY1DJrp9D/pzgki41UiQF/SzH+IRU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xc8KPKbTytg7udpR9zkyBUK6KmeOEiKolsWXLvAqyec4AT35/k9OseN/D53LJzZN9ytEuqfC94V7LqH0w9ecDVRjUZqnL9pzfvWYFYaFy8ViYaTYOzot9BLv1hq4oYaKZSyFKIEe37AtF+cdmVeRo/eisec+tBGh+DyRKWz3QoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=kS0C2cve; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=gZuVqEyu; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="kS0C2cve"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="gZuVqEyu" Received: from phl-compute-02.internal (phl-compute-02.nyi.internal [10.202.2.42]) by mailfhigh.nyi.internal (Postfix) with ESMTP id 8C84C114017B; Fri, 30 Aug 2024 16:35:10 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-02.internal (MEProxy); Fri, 30 Aug 2024 16:35:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050110; x=1725136510; bh=8JvMnm/1j96KVX2x6R72zw6O7YWpn/Ne514YSPMLphw=; b= kS0C2cvertv3h4VDxTi7X13rw8WU3d1EOCkEV/QBiogrkkWilOHXWuB/dTavOCjZ O11CV3ZHlUnKIe+eoTN2uXogjGdUjEPwbai24U30k+xQnNz4VZUT49JxykFpZlHb 9LLVWCLQLf2GBRfauS4ZHRoml7hQOum3d4fL10XJ6E60GJTaGhJ+w0z2K9bfGi8U Ehu1pPFImpPWy0WjjykJOzZB6IFP14YgNUfZEIJgttk/6TxtoE46ww3IKFhusxGD yvZQb2yMyK9Wcu9xYf8iGX2lEQ/k9NyIY5pb/kUfWpn90flCYEAmEntlv0Fr4RlH 00At/giBTLdN3CpMJvOQFw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050110; x= 1725136510; bh=8JvMnm/1j96KVX2x6R72zw6O7YWpn/Ne514YSPMLphw=; b=g ZuVqEyuRhnN1nnaT35egEw5UnkAkYMp7AbuPIJUlfb6QAiQUP7IBzt38C9wxcJti ioFbG+qk9Pry1rzeIwcm1OBpwzNAV8gUFWeeC81fhxjlgD/Gaexqro52/EoFPqpK z35TXTa3jDY/BOgTFuBRliJ5xix8CvkNdB9hqdyj1Yg+P0rKRpJjaKEnbKiM/fJT mCMwFDvnmOVrfUY2DqqvTV+7hInwQe4dq7HmixDQozvXmh/AJs6YF2bMtAImMTZX MqeNmt6de1V8FuN19zmUFGOwFnQxMKlbyDIr6ybf1LmD7qHRTiDl+g4mGEoioEJg YcoxI7H5j2CX6/KjUAgPg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudeglecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:09 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 7/8] media: rcar-csi2: Add documentation for PHY_EN and PHY_MODE registers Date: Fri, 30 Aug 2024 22:31:03 +0200 Message-ID: <20240830203104.3479124-8-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Later datasheets add documentation for two magic value used for V4H support. The same registers will also be used for V4M support, document them. Signed-off-by: Niklas Söderlund --- drivers/media/platform/renesas/rcar-csi2.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 72fcb6ac840b..386037a13786 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -135,13 +135,23 @@ struct rcar_csi2; /* V4H BASE registers */ #define V4H_N_LANES_REG 0x0004 #define V4H_CSI2_RESETN_REG 0x0008 + #define V4H_PHY_MODE_REG 0x001c +#define V4H_PHY_MODE_DPHY 0 +#define V4H_PHY_MODE_CPHY 1 + #define V4H_PHY_SHUTDOWNZ_REG 0x0040 #define V4H_DPHY_RSTZ_REG 0x0044 #define V4H_FLDC_REG 0x0804 #define V4H_FLDD_REG 0x0808 #define V4H_IDIC_REG 0x0810 + #define V4H_PHY_EN_REG 0x2000 +#define V4H_PHY_EN_ENABLE_3 BIT(7) +#define V4H_PHY_EN_ENABLE_2 BIT(6) +#define V4H_PHY_EN_ENABLE_1 BIT(5) +#define V4H_PHY_EN_ENABLE_0 BIT(4) +#define V4H_PHY_EN_ENABLE_CLK BIT(0) #define V4H_ST_PHYST_REG 0x2814 #define V4H_ST_PHYST_ST_PHY_READY BIT(31) @@ -1146,11 +1156,11 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); /* PHY static setting */ - rcsi2_write(priv, V4H_PHY_EN_REG, BIT(0)); + rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); rcsi2_write(priv, V4H_FLDC_REG, 0); rcsi2_write(priv, V4H_FLDD_REG, 0); rcsi2_write(priv, V4H_IDIC_REG, 0); - rcsi2_write(priv, V4H_PHY_MODE_REG, BIT(0)); + rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); /* Reset CSI2 */ From patchwork Fri Aug 30 20:31:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 13785540 X-Patchwork-Delegate: kieran@bingham.xyz Received: from fhigh3-smtp.messagingengine.com (fhigh3-smtp.messagingengine.com [103.168.172.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 673D61C1756; Fri, 30 Aug 2024 20:35:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050115; cv=none; b=hP4/gBbqrzgIQQlXLQeFTODUUBYNC/tgpq+BGBcDbpi4jALZp1FgMY5HAlll1qLzgCczQuiRw9r7N4W3gCCAwkMmefe/ccGeGV/WYgJSnlZPHHb+0URv7SA+zxaJS1wzZsbeI270z5/ESWbgGJb4q/rB7FcaMZfSU6MI403Be/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725050115; c=relaxed/simple; bh=ZObgsg5vid+wlOQoORQuIZ0GNpMv9U7NCEFFmgPgOaM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TRVbvLa5jhAOTajmMBYX2D1z6u9p2ae89WHn8ptNScWMUqNG5wcyeD+/+w1LH11RYto7jkTWb0E/zbOsbP/JALb1ZTASindYYiI+clp5X4OVMfWFTnfxjhXjHCC7faHV2hh5KtG6x0QqapuZNXTyfhZQR0e/bNKxdUMyRdQrzRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se; spf=pass smtp.mailfrom=ragnatech.se; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b=LPfpuaSI; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=uE/nIs6+; arc=none smtp.client-ip=103.168.172.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ragnatech.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ragnatech.se header.i=@ragnatech.se header.b="LPfpuaSI"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="uE/nIs6+" Received: from phl-compute-01.internal (phl-compute-01.nyi.internal [10.202.2.41]) by mailfhigh.nyi.internal (Postfix) with ESMTP id 84A3D1140122; Fri, 30 Aug 2024 16:35:12 -0400 (EDT) Received: from phl-mailfrontend-02 ([10.202.2.163]) by phl-compute-01.internal (MEProxy); Fri, 30 Aug 2024 16:35:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ragnatech.se; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm3; t=1725050112; x=1725136512; bh=UNOtOhMF9lyj1v4QkNpTkB/0jd1e0xbdsmGxpvNVlGo=; b= LPfpuaSIbWVdSp0aX5OJB06nab/wYEvYpFtxU+6/N7yBzCFVR10wMLngdFsSoW2h wAF/jzyiGUDCe15+biROt7M5UA8Nb1mnfT1mbdWWi1jNoZoLn7Ssx/IMUEmVp/tC UnHSF5BxbV8B3at4WSIk05lyqliNZM4SKj2gXuzASyXkihBATk82uqVtHNd1OgNu r0lOfhVjbq2FhHNe7NUeOfWlG9SPgNVoclAOQxZhm5hpCF+m5YGWDJJuo9m6M9cM l9lWa1cKCBbsfq3aT3uJgqkWLyYjinIyOL76ReNakH/L7IfgnLcX2B+EzjYrcWFw MyyciezfQVIeUbMwVVc4Tg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1725050112; x= 1725136512; bh=UNOtOhMF9lyj1v4QkNpTkB/0jd1e0xbdsmGxpvNVlGo=; b=u E/nIs6+U+RPaVgVS2WroBgGjvcA0PU4vpEPLFfrfN1SF0bdwsMplYyqrbvEBowHp eqq71fs4y4pqZXgpOhHeOIIJE5dRKQKh95gt6At/YUAz0y0iIjpSRXX64Y+/G0fj yZcj5Z0+XzFFepb0YQzrfnGkyoXOdNa3kKl1FuXvle/ta79/GKNzueHJyCQJK/Q3 gCRxvRXO/79qxBCkaux/dfdv+rCsnk1XT56njhOC03eEv09xl9qvUnjUcdtxau6+ DgJRW/sHOLshzWyAr1gdvL5e+SuXmIebn6FI4PWGFBXSGnqGYRw8iolr/Pfx+6Kh EwgPNNHZOtMvszwViLDNg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrudefiedgudehtdcutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpggftfghnshhusghstghrihgsvgdp uffrtefokffrpgfnqfghnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivg hnthhsucdlqddutddtmdenucfjughrpefhvfevufffkffojghfgggtgfesthekredtredt jeenucfhrhhomheppfhikhhlrghsucfunpguvghrlhhunhguuceonhhikhhlrghsrdhsoh guvghrlhhunhguodhrvghnvghsrghssehrrghgnhgrthgvtghhrdhsvgeqnecuggftrfgr thhtvghrnhepheeigfeuveeutdefhfehgeekvedtleeuueekveefudehhffhjeffgfegff elfeegnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomhep nhhikhhlrghsrdhsohguvghrlhhunhgusehrrghgnhgrthgvtghhrdhsvgdpnhgspghrtg hpthhtohepuddupdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehmtghhvghhrggs sehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlrghurhgvnhhtrdhpihhntghhrghrth esihguvggrshhonhgsohgrrhgurdgtohhmpdhrtghpthhtohepshgrkhgrrhhirdgrihhl uhhssehlihhnuhigrdhinhhtvghlrdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnh gvlhdrohhrghdprhgtphhtthhopehkrhiihihsiihtohhfrdhkohiilhhofihskhhiodgu theslhhinhgrrhhordhorhhgpdhrtghpthhtoheptghonhhorhdoughtsehkvghrnhgvlh drohhrghdprhgtphhtthhopehgvggvrhhtodhrvghnvghsrghssehglhhiuggvrhdrsggv pdhrtghpthhtoheplhhinhhugidqmhgvughirgesvhhgvghrrdhkvghrnhgvlhdrohhrgh dprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: i80c9496c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 30 Aug 2024 16:35:11 -0400 (EDT) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Mauro Carvalho Chehab , Laurent Pinchart , Sakari Ailus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , linux-media@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 8/8] media: rcar-csi2: Add support for R-Car V4M Date: Fri, 30 Aug 2024 22:31:04 +0200 Message-ID: <20240830203104.3479124-9-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> References: <20240830203104.3479124-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The V4M is the second Gen4 device that is enabled in the rcar-csi2 driver. There is much overlap with the already supported V4H device. The registers that where new on Gen4 and where added with the V4H prefix are retained and only new registers unique to the V4M are added with the new V4M prefix. This follows the style for when V4H was added which had an overlap with Gen3 registers. The V4M CSI-2 receiver supports D-PHY mode only, either in 1-, 2- or 4-lane configuration. The datasheets do not document lane swapping and is left out for now. While the V4M only supports D-PHY the configuration for it is added in such a way that it can be reused for V4H which supports both C-PHY and D-PHY. No known SoC exists to test the D-PHY configuration on V4H so it's not wired-up. Signed-off-by: Niklas Söderlund --- * Changes since v1 - Update to use subdevice active state as this have changed upstream. --- drivers/media/platform/renesas/rcar-csi2.c | 294 +++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/drivers/media/platform/renesas/rcar-csi2.c b/drivers/media/platform/renesas/rcar-csi2.c index 386037a13786..472e62306832 100644 --- a/drivers/media/platform/renesas/rcar-csi2.c +++ b/drivers/media/platform/renesas/rcar-csi2.c @@ -247,6 +247,25 @@ static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { { /* sentinel */ }, }; +/* V4M registers */ +#define V4M_OVR1_REG 0x0848 +#define V4M_OVR1_FORCERXMODE_3 BIT(12) +#define V4M_OVR1_FORCERXMODE_2 BIT(11) +#define V4M_OVR1_FORCERXMODE_1 BIT(10) +#define V4M_OVR1_FORCERXMODE_0 BIT(9) + +#define V4M_FRXM_REG 0x2004 +#define V4M_FRXM_FORCERXMODE_3 BIT(3) +#define V4M_FRXM_FORCERXMODE_2 BIT(2) +#define V4M_FRXM_FORCERXMODE_1 BIT(1) +#define V4M_FRXM_FORCERXMODE_0 BIT(0) + +#define V4M_PHYPLL_REG 0x02050 +#define V4M_CSI0CLKFCPR_REG 0x02054 +#define V4M_PHTW_REG 0x02060 +#define V4M_PHTR_REG 0x02064 +#define V4M_PHTC_REG 0x02068 + struct phtw_value { u8 data; u8 code; @@ -255,6 +274,7 @@ struct phtw_value { struct rcsi2_mbps_info { u16 mbps; u8 reg; + u16 osc_freq; /* V4M */ }; static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { @@ -506,6 +526,73 @@ static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { { /* sentinel */ }, }; +static const struct rcsi2_mbps_info hsfreqrange_v4m[] = { + { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 }, + { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 }, + { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 }, + { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 }, + { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 }, + { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 }, + { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 }, + { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 }, + { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 }, + { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 }, + { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 }, + { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 }, + { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 }, + { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 }, + { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 }, + { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 }, + { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 }, + { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 }, + { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 }, + { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 }, + { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 }, + { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 }, + { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 }, + { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 }, + { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 }, + { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 }, + { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 }, + { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 }, + { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 }, + { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 }, + { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 }, + { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 }, + { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 }, + { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 }, + { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 }, + { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 }, + { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 }, + { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 }, + { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 }, + { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 }, + { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 }, + { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 }, + { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 }, + { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 }, + { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 }, + { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 }, + { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 }, + { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a }, + { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 }, + { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b }, + { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 }, + { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c }, + { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 }, + { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d }, + { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 }, + { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e }, + { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 }, + { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f }, + { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 }, + { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 }, + { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 }, + { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 }, + { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 }, + { /* sentinel */ }, +}; + /* PHY ESC Error Monitor */ #define PHEERM_REG 0x74 @@ -1195,6 +1282,195 @@ static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, return 0; } +static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int data_rate) +{ + unsigned int timeout; + int ret; + + static const struct phtw_value step1[] = { + { .data = 0x00, .code = 0x00 }, + { .data = 0x00, .code = 0x1e }, + }; + + /* Shutdown and reset PHY. */ + rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); + rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); + + /* Start internal calibration (POR). */ + ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); + if (ret) + return ret; + + /* Wait for POR to complete. */ + for (timeout = 10; timeout > 0; timeout--) { + if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) + break; + usleep_range(1000, 2000); + } + + if (!timeout) { + dev_err(priv->dev, "D-PHY calibration failed\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps) +{ + const struct rcsi2_mbps_info *info; + struct phtw_value steps[] = { + { .data = 0x00, .code = 0x00 }, + { .code = 0xe2 }, /* Data filled in below. */ + { .code = 0xe3 }, /* Data filled in below. */ + { .data = 0x01, .code = 0xe4 }, + }; + + info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); + if (!info) + return -ERANGE; + + /* Fill in data for command. */ + steps[1].data = (info->osc_freq & 0x00ff) >> 0; + steps[2].data = (info->osc_freq & 0x0f00) >> 8; + + return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps)); +} + +static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps) +{ + int ret; + + static const struct phtw_value step1[] = { + { .data = 0x00, .code = 0x00 }, + { .data = 0x3c, .code = 0x08 }, + }; + + static const struct phtw_value step2[] = { + { .data = 0x00, .code = 0x00 }, + { .data = 0x80, .code = 0xe0 }, + { .data = 0x01, .code = 0xe1 }, + { .data = 0x06, .code = 0x00 }, + { .data = 0x0f, .code = 0x11 }, + { .data = 0x08, .code = 0x00 }, + { .data = 0x0f, .code = 0x11 }, + { .data = 0x0a, .code = 0x00 }, + { .data = 0x0f, .code = 0x11 }, + { .data = 0x0c, .code = 0x00 }, + { .data = 0x0f, .code = 0x11 }, + { .data = 0x01, .code = 0x00 }, + { .data = 0x31, .code = 0xaa }, + { .data = 0x05, .code = 0x00 }, + { .data = 0x05, .code = 0x09 }, + { .data = 0x07, .code = 0x00 }, + { .data = 0x05, .code = 0x09 }, + { .data = 0x09, .code = 0x00 }, + { .data = 0x05, .code = 0x09 }, + { .data = 0x0b, .code = 0x00 }, + { .data = 0x05, .code = 0x09 }, + }; + + if (priv->info->hsfreqrange) { + ret = rcsi2_set_phypll(priv, mbps); + if (ret) + return ret; + + ret = rcsi2_set_osc_freq(priv, mbps); + if (ret) + return ret; + } + + if (mbps <= 1500) { + ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); + if (ret) + return ret; + } + + if (priv->info->csi0clkfreqrange) + rcsi2_write(priv, V4M_CSI0CLKFCPR_REG, + CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); + + rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | + V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | + V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); + + if (mbps > 1500) { + ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); + if (ret) + return ret; + } + + return ret; +} + +static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv, + struct v4l2_subdev_state *state) +{ + const struct rcar_csi2_format *format; + const struct v4l2_mbus_framefmt *fmt; + unsigned int lanes; + int mbps; + int ret; + + /* Calculate parameters */ + fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); + format = rcsi2_code_to_fmt(fmt->code); + if (!format) + return -EINVAL; + + ret = rcsi2_get_active_lanes(priv, &lanes); + if (ret) + return ret; + + mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); + if (mbps < 0) + return mbps; + + /* Reset LINK and PHY */ + rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); + rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); + rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); + rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR); + + /* PHY static setting */ + rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); + rcsi2_write(priv, V4H_FLDC_REG, 0); + rcsi2_write(priv, V4H_FLDD_REG, 0); + rcsi2_write(priv, V4H_IDIC_REG, 0); + rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY); + rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); + + rcsi2_write(priv, V4M_FRXM_REG, + V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | + V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); + rcsi2_write(priv, V4M_OVR1_REG, + V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | + V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); + + /* Reset CSI2 */ + rcsi2_write(priv, V4M_PHTC_REG, 0); + rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); + + /* Common settings */ + ret = rcsi2_init_common_v4m(priv, mbps); + if (ret) + return ret; + + /* D-PHY settings */ + ret = rcsi2_d_phy_setting_v4m(priv, mbps); + if (ret) + return ret; + + rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | + V4H_ST_PHYST_ST_STOPSTATE_1 | + V4H_ST_PHYST_ST_STOPSTATE_2 | + V4H_ST_PHYST_ST_STOPSTATE_3); + + rcsi2_write(priv, V4M_FRXM_REG, 0); + + return 0; +} + static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) { int ret; @@ -1832,6 +2108,20 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { .support_cphy = true, }; +static const struct rcsi2_register_layout rcsi2_registers_v4m = { + .phtw = V4M_PHTW_REG, + .phypll = V4M_PHYPLL_REG, +}; + +static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = { + .regs = &rcsi2_registers_v4m, + .start_receiver = rcsi2_start_receiver_v4m, + .hsfreqrange = hsfreqrange_v4m, + .csi0clkfreqrange = 0x0c, + .use_isp = true, + .support_dphy = true, +}; + static const struct of_device_id rcar_csi2_of_table[] = { { .compatible = "renesas,r8a774a1-csi2", @@ -1885,6 +2175,10 @@ static const struct of_device_id rcar_csi2_of_table[] = { .compatible = "renesas,r8a779g0-csi2", .data = &rcar_csi2_info_r8a779g0, }, + { + .compatible = "renesas,r8a779h0-csi2", + .data = &rcar_csi2_info_r8a779h0, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);