From patchwork Thu Mar 7 00:03:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10842079 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F536139A for ; Thu, 7 Mar 2019 00:02:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F83D2E9FC for ; Thu, 7 Mar 2019 00:02:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 837B22EC45; Thu, 7 Mar 2019 00:02:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 133092E9FC for ; Thu, 7 Mar 2019 00:02:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726597AbfCGACh (ORCPT ); Wed, 6 Mar 2019 19:02:37 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:34053 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726544AbfCGACe (ORCPT ); Wed, 6 Mar 2019 19:02:34 -0500 Received: by mail-pg1-f195.google.com with SMTP id i130so9725754pgd.1 for ; Wed, 06 Mar 2019 16:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZbPJjxSoYcl81yQ1wEFQrBqpLWhgT90XsJgxTUaDTjI=; b=x0Stg7YrNUiHiDFMZVrLIf4dg3dIguNoxLz9GoEjKz81Lp8qb0LAJrVbJbBclfg+bZ Is9fiGZw5CrfI7xHIYKOKfxhdXWt4y+YDGdFd3TL8IDJZdK60NzTHg5ISMEEaVtF/VfE ujxt7s/vonSA+3lv5r1M9Wstrm/5uWdyxTmz5CdWs+bmX1hI+KFJ+zdJy2/EaWISWm47 H0VpMv+CR4+1HdMAZ2NFBpE/UWXSphD/Xc7A7o5X15sF219jgMX9mFm3dmR9PROsRE8o Navu5XWl+DDLKPp1z9+8e5lFO3F1uiIMePVcv5m4PG373i6GZ03SV7aSYB56cn5w3iGv RpyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZbPJjxSoYcl81yQ1wEFQrBqpLWhgT90XsJgxTUaDTjI=; b=e+83AG0g7u14PS5iEkeG5/xr3NEwveyRrCHAj9gYXdQrwqI1bsKgUnlfzrvYxuHn2u o58byHMXhgDqK5kd7R6j/x32ioAvyC7XhM3oBHJIn0jv5dfeNmpiWyGV1PItjPHC5C4o eMQweh6JVquWPtSzmXQllnNCIkydl1AYlJb9HXNkzEyPA2Lew83wMITWAprwqxIBXi7g 0lvnKv/3/r6DNupWAfL+VyoQMc+W2bxuWmLIIq0kuqZmgB/mAyvGRVzRjN/s6krJMuEx XCnQuZbO3fHYMGFHDEibwBUNkwwpT9z8cK1UuxIW/EZlRNyZuxDwe75HRbkVYHGTfhl+ mnjw== X-Gm-Message-State: APjAAAWohHO0LljO7IbiWqOP5ztxK7jk24JmBH5WXjD6uQQfw4VQRWta L8x43apMvkpcaTetekv3TD/8vQ== X-Google-Smtp-Source: APXvYqwdnPW/y9So1gIGyOR8jQDF5+ug0ciRCC8Hqqf5gKIvxcay45WltY76fJ2iU72L4F2snRXL1A== X-Received: by 2002:a65:6642:: with SMTP id z2mr8802824pgv.196.1551916953013; Wed, 06 Mar 2019 16:02:33 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id n10sm4105589pfa.139.2019.03.06.16.02.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 16:02:32 -0800 (PST) From: Bjorn Andersson To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: remoteproc: Rename and amend Hexagon v56 binding Date: Wed, 6 Mar 2019 16:03:17 -0800 Message-Id: <20190307000318.1750-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190307000318.1750-1-bjorn.andersson@linaro.org> References: <20190307000318.1750-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The SDM845 Audio DSP peripheral image loader binding describes the properties needed to load and boot firmware on a Hexagon v56. Rename the file and add the Compute DSP (CDSP) found in QCS404 to the binding. Signed-off-by: Bjorn Andersson --- ...qcom,adsp-pil.txt => qcom,hexagon-v56.txt} | 34 +++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) rename Documentation/devicetree/bindings/remoteproc/{qcom,adsp-pil.txt => qcom,hexagon-v56.txt} (74%) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt similarity index 74% rename from Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt rename to Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt index 66af2c30944f..8011f88f7c1f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,hexagon-v56.txt @@ -1,12 +1,13 @@ -Qualcomm Technology Inc. ADSP Peripheral Image Loader +Qualcomm Technology Inc. Hexagon v56 Peripheral Image Loader This document defines the binding for a component that loads and boots firmware -on the Qualcomm Technology Inc. ADSP Hexagon core. +on the Qualcomm Technology Inc. Hexagon v56 core. - compatible: Usage: required Value type: Definition: must be one of: + "qcom,qcs404-cdsp-pil", "qcom,sdm845-adsp-pil" - reg: @@ -28,10 +29,10 @@ on the Qualcomm Technology Inc. ADSP Hexagon core. - clocks: Usage: required Value type: - Definition: List of 8 phandle and clock specifier pairs for the adsp. + Definition: List of phandles and clock specifier pairs for the Hexagon. - clock-names: - Usage: required + Usage: required for SDM845 ADSP Value type: Definition: List of clock input name strings sorted in the same order as the clocks property. Definition must have @@ -39,6 +40,14 @@ on the Qualcomm Technology Inc. ADSP Hexagon core. "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep" and "qdsp6ss_core". +- clock-names: + Usage: required for QCS404 CDSP + Value type: + Definition: List of clock input name strings sorted in the same + order as the clocks property. Definition must have + "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", + "q6ss_master", "q6_axim". + - power-domains: Usage: required Value type: @@ -47,28 +56,33 @@ on the Qualcomm Technology Inc. ADSP Hexagon core. - resets: Usage: required Value type: - Definition: reference to the list of 2 reset-controller for the adsp. + Definition: reference to the list of resets for the Hexagon. - reset-names: - Usage: required + Usage: required for SDM845 ADSP Value type: Definition: must be "pdc_sync" and "cc_lpass" +- reset-names: + Usage: required for QCS404 CDSP + Value type: + Definition: must be "restart" + - qcom,halt-regs: Usage: required Value type: Definition: a phandle reference to a syscon representing TCSR followed - by the offset within syscon for lpass halt register. + by the offset within syscon for Hexagon halt register. - memory-region: Usage: required Value type: - Definition: reference to the reserved-memory for the ADSP + Definition: reference to the reserved-memory for the firmware - qcom,smem-states: Usage: required Value type: - Definition: reference to the smem state for requesting the ADSP to + Definition: reference to the smem state for requesting the Hexagon to shut down - qcom,smem-state-names: @@ -79,7 +93,7 @@ on the Qualcomm Technology Inc. ADSP Hexagon core. = SUBNODES The adsp node may have an subnode named "glink-edge" that describes the -communication edge, channels and devices related to the ADSP. +communication edge, channels and devices related to the Hexagon. See ../soc/qcom/qcom,glink.txt for details on how to describe these. = EXAMPLE From patchwork Thu Mar 7 00:03:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 10842083 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 005E61669 for ; Thu, 7 Mar 2019 00:02:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E583E2E9FC for ; Thu, 7 Mar 2019 00:02:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D95D42EA0E; Thu, 7 Mar 2019 00:02:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 593B32EC6A for ; Thu, 7 Mar 2019 00:02:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726618AbfCGACh (ORCPT ); Wed, 6 Mar 2019 19:02:37 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:33709 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726582AbfCGACf (ORCPT ); Wed, 6 Mar 2019 19:02:35 -0500 Received: by mail-pg1-f194.google.com with SMTP id h11so9734332pgl.0 for ; Wed, 06 Mar 2019 16:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7D9fT9nrITboyJ+SOXix9/gHXfGWOiHJwaPk2qVUU3c=; b=ddf5u3tNvdNs2EOND3azErflgszR8yihqngDsUDQiHfChHcViUpb3bqlsw2RsTDmgs ALIvgX5JW+QO718cnmBYYXF3IFh60xdFg/ltYWTIJ4fkGua53pKdv+MWrVap52AQJO8L tS3+/i4f99b7kiRVEQhw9NO/A6g55EcbQS646hMgY5PHpjMYnbpILFlIUZCxP643BXe7 3O4hTaTqPNW+9YCUoe85KOMjWJmcmH9eO1swzQkgH0+7NT06RwngsQ/0j+R5erbkPUaf HVQIZ/NDNRPo5v9xYmJPaWG/9GAkGMcck14zAFH49VRObiSJWIrzD3ar2eUqp3RD1+Cw dM3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7D9fT9nrITboyJ+SOXix9/gHXfGWOiHJwaPk2qVUU3c=; b=oDrigvO8CpTOIbw5Oh7Hpatqyjx+igSDVIUsPi9GAsIZXtN1mrS2wXNZ2wx7Xqp/tm cLTvwu3V/zkHRejvP8+S1WRwVjIgiXs9OBlpTzdzLwCtOTJeyRWO+8/ukyjmkazX20YG 1VY+GLivWUS6SvhkrEon6gX0yGftm6Wi9nMQqreRyzQle7vbd486+Nk9ktP2DN5TpqsI efhkXGFHFAvPkxzI8K00qoBsoR09r9FMMIiX8+efLJJ54isUx1atoB171S+uwuspLiXU ZR9guMuDR8Qcaqlh3xuB7ww02wFfjlSahrQS7+GznSV9cvsTjExdDayqafwj+DQSTmhe smdA== X-Gm-Message-State: APjAAAXVOE9/Mcun/++Y6pZyvK9dcwQzlEenSLVnAib96xe9d34C9c8E Bus6RqzzNSiRv2nMKJuGSbq7Evg2yBA= X-Google-Smtp-Source: APXvYqxOpnh4m3QcGsAd9vOKds2uFkHqc2JOsXpnp8z9cY9EwouRpWm/QVkYkuY+IAyNrJCZETR2qA== X-Received: by 2002:a63:3648:: with SMTP id d69mr8777394pga.314.1551916954331; Wed, 06 Mar 2019 16:02:34 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id n10sm4105589pfa.139.2019.03.06.16.02.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 16:02:33 -0800 (PST) From: Bjorn Andersson To: Ohad Ben-Cohen , Bjorn Andersson Cc: Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] remoteproc: qcom: qdsp6-adsp: Add support for QCS404 CDSP Date: Wed, 6 Mar 2019 16:03:18 -0800 Message-Id: <20190307000318.1750-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190307000318.1750-1-bjorn.andersson@linaro.org> References: <20190307000318.1750-1-bjorn.andersson@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the clock list to adsp_pil_data, make the pdc_reset optional and make the driver directly enable the xo, sleep and core clocks. The three clocks are previously toggled through the clock controller, but that means the same hardware block needs to be mapped in both drivers. Making the remoteproc driver enable the clocks is a nop when using the clock controller, but allow us to remove the clocks from the clock controller. Signed-off-by: Bjorn Andersson --- drivers/remoteproc/qcom_q6v5_adsp.c | 73 ++++++++++++++++++++++------- 1 file changed, 55 insertions(+), 18 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 1f3ef9ee493c..e953886b2eb7 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -46,11 +46,9 @@ #define LPASS_PWR_ON_REG 0x10 #define LPASS_HALTREQ_REG 0x0 -/* list of clocks required by ADSP PIL */ -static const char * const adsp_clk_id[] = { - "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", - "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", -}; +#define QDSP6SS_XO_CBCR 0x38 +#define QDSP6SS_CORE_CBCR 0x20 +#define QDSP6SS_SLEEP_CBCR 0x3c struct adsp_pil_data { int crash_reason_smem; @@ -59,6 +57,9 @@ struct adsp_pil_data { const char *ssr_name; const char *sysmon_name; int ssctl_id; + + const char **clk_ids; + int num_clks; }; struct qcom_adsp { @@ -75,7 +76,7 @@ struct qcom_adsp { void __iomem *qdsp6ss_base; struct reset_control *pdc_sync_reset; - struct reset_control *cc_lpass_restart; + struct reset_control *restart; struct regmap *halt_map; unsigned int halt_lpass; @@ -143,7 +144,7 @@ static int qcom_adsp_shutdown(struct qcom_adsp *adsp) /* Assert the LPASS PDC Reset */ reset_control_assert(adsp->pdc_sync_reset); /* Place the LPASS processor into reset */ - reset_control_assert(adsp->cc_lpass_restart); + reset_control_assert(adsp->restart); /* wait after asserting subsystem restart from AOSS */ usleep_range(200, 300); @@ -153,7 +154,7 @@ static int qcom_adsp_shutdown(struct qcom_adsp *adsp) /* De-assert the LPASS PDC Reset */ reset_control_deassert(adsp->pdc_sync_reset); /* Remove the LPASS reset */ - reset_control_deassert(adsp->cc_lpass_restart); + reset_control_deassert(adsp->restart); /* wait after de-asserting subsystem restart from AOSS */ usleep_range(200, 300); @@ -192,6 +193,15 @@ static int adsp_start(struct rproc *rproc) goto disable_power_domain; } + /* Enable the XO clock */ + writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR); + + /* Enable the QDSP6SS sleep clock */ + writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR); + + /* Enable the QDSP6 core clock */ + writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR); + /* Program boot address */ writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); @@ -280,8 +290,9 @@ static const struct rproc_ops adsp_ops = { .load = adsp_load, }; -static int adsp_init_clock(struct qcom_adsp *adsp) +static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids) { + int num_clks = 0; int i, ret; adsp->xo = devm_clk_get(adsp->dev, "xo"); @@ -292,32 +303,39 @@ static int adsp_init_clock(struct qcom_adsp *adsp) return ret; } - adsp->num_clks = ARRAY_SIZE(adsp_clk_id); + for (i = 0; clk_ids[i]; i++) + num_clks++; + + adsp->num_clks = num_clks; adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks, sizeof(*adsp->clks), GFP_KERNEL); if (!adsp->clks) return -ENOMEM; for (i = 0; i < adsp->num_clks; i++) - adsp->clks[i].id = adsp_clk_id[i]; + adsp->clks[i].id = clk_ids[i]; return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks); } static int adsp_init_reset(struct qcom_adsp *adsp) { - adsp->pdc_sync_reset = devm_reset_control_get_exclusive(adsp->dev, + adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev, "pdc_sync"); if (IS_ERR(adsp->pdc_sync_reset)) { dev_err(adsp->dev, "failed to acquire pdc_sync reset\n"); return PTR_ERR(adsp->pdc_sync_reset); } - adsp->cc_lpass_restart = devm_reset_control_get_exclusive(adsp->dev, - "cc_lpass"); - if (IS_ERR(adsp->cc_lpass_restart)) { - dev_err(adsp->dev, "failed to acquire cc_lpass restart\n"); - return PTR_ERR(adsp->cc_lpass_restart); + adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart"); + + /* Fall back to the old "cc_lpass" if "restart" is absent */ + if (!adsp->restart) + adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass"); + + if (IS_ERR(adsp->restart)) { + dev_err(adsp->dev, "failed to acquire restart\n"); + return PTR_ERR(adsp->restart); } return 0; @@ -415,7 +433,7 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto free_rproc; - ret = adsp_init_clock(adsp); + ret = adsp_init_clock(adsp, desc->clk_ids); if (ret) goto free_rproc; @@ -479,9 +497,28 @@ static const struct adsp_pil_data adsp_resource_init = { .ssr_name = "lpass", .sysmon_name = "adsp", .ssctl_id = 0x14, + .clk_ids = (const char*[]) { + "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", + "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL + }, + .num_clks = 7, +}; + +static const struct adsp_pil_data cdsp_resource_init = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mdt", + .ssr_name = "cdsp", + .sysmon_name = "cdsp", + .ssctl_id = 0x17, + .clk_ids = (const char*[]) { + "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", + "q6_axim", NULL + }, + .num_clks = 7, }; static const struct of_device_id adsp_of_match[] = { + { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, { }, };