From patchwork Tue Sep 3 21:39:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789333 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 777071EBFFF; Tue, 3 Sep 2024 21:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399614; cv=none; b=JJqFl6I0FfKDL3HFhkwRVWHID9Wfu9AZvtLLi47DTIcAKs53+CqDCaU2nqEEv4eTNRtYkVuK4gYnRIYeccqM9rlwcuyAVeQn3rkuo0neEV0O+DvH3HUYuoFbhogpkzwhFQqwtwg4Bfqb6AeCbgdKtppejOBMAyF8NAupaNE3Gzk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399614; c=relaxed/simple; bh=a9yzvBt3h24feKE6Zv0c1siWavObQsYicuqNnNEBo9w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C9lsNWC0a0ZyGOvY3lmtPGVIDijs9i5z+TsX093W49ZYbJIK9zs0vLfCuEUstsFTvcxBU6vPWuGsuu9gOA29SBMbiS28f5jlPtCG6kFh4Gopca8rOVsJ6P7FGOd2ywhOx/bZTX4bCQDnPAK+ogAupLtsmDnwvWCcR93Y9jGqGyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cjmtt2WD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cjmtt2WD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5FDA3C4CEC7; Tue, 3 Sep 2024 21:40:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399613; bh=a9yzvBt3h24feKE6Zv0c1siWavObQsYicuqNnNEBo9w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cjmtt2WDxYabR7hsfVrnspvFYsFEjhGgJw+yltVbTUqTU+rJDhankxTS/j5R9R/bW J7iEnJu4BpakAzTk7r9SD3BZmaRG7UEfDhgxgWXtZ8LUVL9zQKJ3b8jlx+LVGmRUxr ODOQPGObwQuYLycN1F/XAGvqIUlp06n2nFR8vY/cWe+CkdwM3mt94/owQunt0iPNfz gosylxGOk+meEP+6UNmPb5xYWNII5hkuMmGEmk26QxVL0gR7vgzRLu+CYM1Z81+M6F ks16YAMW6y25mricRbK1Z5eHWo3yjhJdwT0Z3naAdj7HDCL7KZhspFbqCI5HyLKdZu ALVX0qHH0cnpQ== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:45 +0200 Subject: [PATCH v2 1/7] dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC. Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-1-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 clk-en7523 driver for EN7581 SoC is mapping all the scu memory region while it is configuring the chip-scu one via a syscon. Update the reg mapping definition for this device. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi Reviewed-by: Rob Herring (Arm) --- .../bindings/clock/airoha,en7523-scu.yaml | 23 ++++++++-------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 84353fd09428..fe2c5c1baf43 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -34,8 +34,10 @@ properties: - airoha,en7581-scu reg: - minItems: 2 - maxItems: 4 + items: + - description: scu base address + - description: misc scu base address + minItems: 1 "#clock-cells": description: @@ -60,9 +62,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address + minItems: 2 '#reset-cells': false @@ -73,11 +73,7 @@ allOf: then: properties: reg: - items: - - description: scu base address - - description: misc scu base address - - description: reset base address - - description: pb scu base address + maxItems: 1 additionalProperties: false @@ -96,12 +92,9 @@ examples: #address-cells = <2>; #size-cells = <2>; - scuclk: clock-controller@1fa20000 { + scuclk: clock-controller@1fb00000 { compatible = "airoha,en7581-scu"; - reg = <0x0 0x1fa20000 0x0 0x400>, - <0x0 0x1fb00000 0x0 0x90>, - <0x0 0x1fb00830 0x0 0x8>, - <0x0 0x1fbe3400 0x0 0xfc>; + reg = <0x0 0x1fb00000 0x0 0x970>; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Tue Sep 3 21:39:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789334 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92B571C62C5; Tue, 3 Sep 2024 21:40:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399616; cv=none; b=KIREcC4eqFTZZZr21UxI917Sswlo7Q3bVVE5awGs5uCF4U2BZQTTgK4iDHUHNatW1hWTBjRgFmzgN7CjkCJPLaHcwuQEwaUxznTf6GbdMUiz9entsTndICUjYwtrfrxr679o0WeJ9GadLjElmiOk9th6L0sj2D0NB5v342eBFAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399616; c=relaxed/simple; bh=cGV5szsD+4z0z0sEdE3fe/LJ1oug+CG6EBmlovNucZo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iw8TvUWlCJyF6ZlNhB1kFkVg70jFbPAXAx3EtAZisN4l6kSipAIL4s4cWUgJJ7vfwIQuGbBs2TXe/NF8kdGYv92mOFpjJINGFTmSdQzyRSXInCnaRWSfvxSFFg3JoRQbLx6GE2F4VsQWhbmF+HD0/zKax1ui0PIDGc623a3ihDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RnlwPQE4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RnlwPQE4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BE56C4CEC7; Tue, 3 Sep 2024 21:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399616; bh=cGV5szsD+4z0z0sEdE3fe/LJ1oug+CG6EBmlovNucZo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RnlwPQE4WIP8cB21O/+sbHvXFbBuusAQEkIvC3DPSg6bKQUPM29Vw0knufz17EzTZ yoa7+AgoLJQqu7GWfPQOMSEz57S9KjlGWL8u1jvJyI5dACNC3cfYDfrytYGDLquhym i4QKwhzCHVuYzPetWNlTFvh7JGRsptdqvPxoZNXyl1tCbw1R9E/9o2783uastdwXlG sqysILn+W6mP+Tu1gnVuMQhddYSbqYxbH+f528rzup6TDmHEkQ8hOyN0EUCKAm9i3o 0RkOabdAaIbMjuU8YEgTwL6DIDdzaEUxyEptvpS88bc2/fyH60NSOgL+1+q8p4F6SV sdXEtgGWwNlDA== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:46 +0200 Subject: [PATCH v2 2/7] clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-2-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not part of the scu block on the EN7581 SoC and they are used to select the PCIE ports on the PBUS, so remove this configuration from the clock driver and set these registers in the PCIE host driver instead. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dc..ec6716844fdc 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -31,12 +31,6 @@ #define REG_RESET_CONTROL_PCIE1 BIT(27) #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ -#define REG_PCIE0_MEM 0x00 -#define REG_PCIE0_MEM_MASK 0x04 -#define REG_PCIE1_MEM 0x08 -#define REG_PCIE1_MEM_MASK 0x0c -#define REG_PCIE2_MEM 0x10 -#define REG_PCIE2_MEM_MASK 0x14 #define REG_NP_SCU_PCIC 0x88 #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) @@ -415,26 +409,14 @@ static void en7581_pci_disable(struct clk_hw *hw) static int en7581_clk_hw_init(struct platform_device *pdev, void __iomem *np_base) { - void __iomem *pb_base; u32 val; - pb_base = devm_platform_ioremap_resource(pdev, 3); - if (IS_ERR(pb_base)) - return PTR_ERR(pb_base); - val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); writel(val, np_base + REG_NP_SCU_SSTR); val = readl(np_base + REG_NP_SCU_PCIC); writel(val | 3, np_base + REG_NP_SCU_PCIC); - writel(0x20000000, pb_base + REG_PCIE0_MEM); - writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK); - writel(0x24000000, pb_base + REG_PCIE1_MEM); - writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK); - writel(0x28000000, pb_base + REG_PCIE2_MEM); - writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK); - return 0; } From patchwork Tue Sep 3 21:39:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789335 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 939FC1EBFFF; Tue, 3 Sep 2024 21:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399619; cv=none; b=GtWI1VfIvGD65YKhbI7PdwgqZHbfgkMf/RLq79DJFYhalmX/WvP/yjgOQisVXQntreULm9QfEKyDu9maev3xPRaB69tI3LsNgOY+aUD6cCEJRSJ5Ms+BIosj+VS6yz2WxF57v9Tt7nvVng2p0ZCVJEo507xREHRrny0MZ75b90o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399619; c=relaxed/simple; bh=1CoDf9/6bfA2XwXg3dR12y1kHEta6j59pRA8NTgiPQk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sYbN6NJh7gQ0aFEkdF6Khjvx9FLXZSwlmISha42xxpj60f8BKkZ/luPcSbb2emVp7FMY1HXc64z77/5h8rGOK3xFRs+Lx4hbWbYEpXIHBP7c2+cSUDT23CVO8JwE5OWNv8DZSV7DZ4BTtSadk6I8rJw1aQ+D2bLtXA8eymXNxVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bgsIyVlX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bgsIyVlX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8F9EC4CEC5; Tue, 3 Sep 2024 21:40:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399619; bh=1CoDf9/6bfA2XwXg3dR12y1kHEta6j59pRA8NTgiPQk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bgsIyVlXutJ6nUIZ4sc0/6EDX1p6W/FcO0acOjAsTpnmnaBdZwa2bYjBnlk4V2MrM fjP+Q2k0K3/7SV6naFJ1CdjylLGy541nGOsshEUZI5yiadwoMRgHeavn03VLtQ3b5u iq132FozcioeLDXJNWZQQDpWTKZY/2ASJ1FEXqj5pch0tU8vjNmHOmcaVrmpr1xAP7 RvfQWB8yeRRXV3H5bbx1yetcYTtB4WQKL0nyz02lux7cgSS+mT1fj6WTsjlyR0yYWT /EUGN7dH/ckp+IjuoMbnXvriJETdGyvuVe+3LRaaockd/qnCp/QDIXyXWx6lGu/CsL HT8g4DQUeCglA== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:47 +0200 Subject: [PATCH v2 3/7] clk: en7523: move clock_register in hw_init callback Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-3-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Move en7523_register_clocks routine in hw_init callback. Introduce en7523_clk_hw_init callback for EN7523 SoC. This is a preliminary patch to differentiate IO mapped region between EN7523 and EN7581 SoCs in order to access chip-scu IO region <0x1fa20000 0x384> on EN7581 SoC as syscon device since it contains miscellaneous registers needed by multiple devices (clock, pinctrl ..). Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 82 +++++++++++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index ec6716844fdc..da112c9fe8ef 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -78,7 +78,8 @@ struct en_clk_soc_data { const u16 *idx_map; u16 idx_map_nr; } reset; - int (*hw_init)(struct platform_device *pdev, void __iomem *np_base); + int (*hw_init)(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data); }; static const u32 gsw_base[] = { 400000000, 500000000 }; @@ -406,20 +407,6 @@ static void en7581_pci_disable(struct clk_hw *hw) usleep_range(1000, 2000); } -static int en7581_clk_hw_init(struct platform_device *pdev, - void __iomem *np_base) -{ - u32 val; - - val = readl(np_base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); - - return 0; -} - static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, void __iomem *base, void __iomem *np_base) { @@ -449,6 +436,49 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } +static int en7523_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *base, *np_base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + return 0; +} + +static int en7581_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *base, *np_base; + u32 val; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + val = readl(np_base + REG_NP_SCU_SSTR); + val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + writel(val, np_base + REG_NP_SCU_SSTR); + val = readl(np_base + REG_NP_SCU_PCIC); + writel(val | 3, np_base + REG_NP_SCU_PCIC); + + return 0; +} + static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -543,31 +573,18 @@ static int en7523_clk_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; const struct en_clk_soc_data *soc_data; struct clk_hw_onecell_data *clk_data; - void __iomem *base, *np_base; int r; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - np_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); - - soc_data = device_get_match_data(&pdev->dev); - if (soc_data->hw_init) { - r = soc_data->hw_init(pdev, np_base); - if (r) - return r; - } - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, EN7523_NUM_CLOCKS), GFP_KERNEL); if (!clk_data) return -ENOMEM; - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + soc_data = device_get_match_data(&pdev->dev); + r = soc_data->hw_init(pdev, clk_data); + if (r) + return r; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -590,6 +607,7 @@ static const struct en_clk_soc_data en7523_data = { .prepare = en7523_pci_prepare, .unprepare = en7523_pci_unprepare, }, + .hw_init = en7523_clk_hw_init, }; static const struct en_clk_soc_data en7581_data = { From patchwork Tue Sep 3 21:39:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789336 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB7B71EBFFF; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kp+Tv5zr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4EDCDC4CEC5; Tue, 3 Sep 2024 21:40:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399621; bh=Ph06Tg/4q5VIk3xDmgEvYK5TF6r7nuySH269VXi+Mc0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kp+Tv5zrsKPvMIjlpMQuG9FsxZXiiA2jDXRtG3s1hlGIHRaD2MGjcBwxHkX+xEveA Mrj820pWOwai1XbL08PoA3WaZKU81HHGQJl2B2yzj4Y/ze/HS6BYzkKnRSxoU6e7N5 YbUaFi0BRfO4mV7KPIlFLEpoMtW0x0JuTCx6Qm/Y083LE3c8G0IGCWL+WsSPzIbsOf nuAQLJZc3lG1ejWpmeo7vrI+xThU143W2sFAn89XseTze681iPQCEg1uQaA5+Ys5BR 9ORIwYQkD8fOD4Oobe6AZz3efA3VspSe/a8ZeXmmJKL69Kh5mmdM5YUw+4rATzPM5w uBdtFlZjBRuIg== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:48 +0200 Subject: [PATCH v2 4/7] clk: en7523: introduce chip_scu regmap Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-4-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Introduce chip_scu regmap pointer since EN7581 SoC will access chip-scu memory area via a syscon node. Remove first memory region mapping for EN7581 SoC. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 81 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 20 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index da112c9fe8ef..7f83cbce01ee 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -3,8 +3,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -247,15 +249,11 @@ static const u16 en7581_rst_map[] = { [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, }; -static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 val; - if (!desc->base_bits) return desc->base_value; - val = readl(base + desc->base_reg); val >>= desc->base_shift; val &= (1 << desc->base_bits) - 1; @@ -265,16 +263,11 @@ static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) return desc->base_values[val]; } -static u32 en7523_get_div(void __iomem *base, int i) +static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 reg, val; - if (!desc->div_bits) return 1; - reg = desc->div_reg ? desc->div_reg : desc->base_reg; - val = readl(base + reg); val >>= desc->div_shift; val &= (1 << desc->div_bits) - 1; @@ -416,9 +409,12 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; + u32 val = readl(base + desc->base_reg); - rate = en7523_get_base_rate(base, i); - rate /= en7523_get_div(base, i); + rate = en7523_get_base_rate(desc, val); + val = readl(base + reg); + rate /= en7523_get_div(desc, val); hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); if (IS_ERR(hw)) { @@ -454,21 +450,66 @@ static int en7523_clk_hw_init(struct platform_device *pdev, return 0; } +static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + struct regmap *map, void __iomem *base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; + int err; + + err = regmap_read(map, desc->base_reg, &val); + if (err) { + pr_err("Failed reading fixed clk rate %s: %d\n", + desc->name, err); + continue; + } + rate = en7523_get_base_rate(desc, val); + + err = regmap_read(map, reg, &val); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + desc->name, err); + continue; + } + rate /= en7523_get_div(desc, val); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - void __iomem *base, *np_base; + void __iomem *np_base; + struct regmap *map; u32 val; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); - np_base = devm_platform_ioremap_resource(pdev, 1); + np_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(np_base)) return PTR_ERR(np_base); - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + en7581_register_clocks(&pdev->dev, clk_data, map, np_base); val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -545,7 +586,7 @@ static int en7523_reset_register(struct platform_device *pdev, if (!soc_data->reset.idx_map_nr) return 0; - base = devm_platform_ioremap_resource(pdev, 2); + base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) return PTR_ERR(base); From patchwork Tue Sep 3 21:39:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789337 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2920F19341C; Tue, 3 Sep 2024 21:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725399626; cv=none; b=GSLZRphTF8Tj6ea3cJqj25vAStdvWEzLSLZFBtqjWzOUdDLE0usw81guPx+jMio9lQg9EyBnGe11boxuD26Q9Ur4951iS0Xp5bQfIhvr/aaOo1giWYU1FX9h97itc7klfhLJP/qpTJ+WDN9GpiXySX5IXW/pBnI1IQUnUAAdPQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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static const u32 bus_base[] = { 500000000, 540000000 }; static const u32 slic_base[] = { 100000000, 3125000 }; static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; +/* EN7581 */ +static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; +static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; +static const u32 crypto_base[] = { 540000000, 480000000 }; static const struct en_clk_desc en7523_base_clks[] = { { @@ -186,6 +191,102 @@ static const struct en_clk_desc en7523_base_clks[] = { } }; +static const struct en_clk_desc en7581_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = emi7581_base, + .n_base_values = ARRAY_SIZE(emi7581_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu7581_base, + .n_base_values = ARRAY_SIZE(npu7581_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 0, + .base_values = crypto_base, + .n_base_values = ARRAY_SIZE(crypto_base), + } +}; + static const u16 en7581_rst_ofs[] = { REG_RST_CTRL2, REG_RST_CTRL1, @@ -457,8 +558,8 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat u32 rate; int i; - for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; + for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { + const struct en_clk_desc *desc = &en7581_base_clks[i]; u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; int err; From patchwork Tue Sep 3 21:39:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789338 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9A1719CC2F; Tue, 3 Sep 2024 21:40:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 3 Sep 2024 21:40:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399627; bh=PW8ddy+pXAnxNJrPOQZKDlj/hwvRV8Ogci5h4BqHNeU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PA65CrZNNZKdzTjDfxNzpdiZnyyGffoGo68wGzKwCXM8wBeIMzx1slE/C1VXMStym PE4tCN/8iSqqjucQHGLcHRA28oQjsoftvIYu3aTspX4YXp9DRyqDX+jZqKTMDWjG9p 78Cex56wXjgu5ORgj0EPUYzX6UgWRpCkNjRsQQPTnY+uNCWLhEbRbtWFIJO3IAOybE YAHbEWl7y5oloBuPuJMdXLBmCKCdBDj1rp4A9aEu7fur9/k37+UUwYk1wrb4BszwgP 34Fd8BqZMrg3jltkJirlms5M+javUZAh0+ml9V7oZM1rEiQD/rQHuCkzp33p0bxIa6 M/Y9DS63uD7sQ== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:50 +0200 Subject: [PATCH v2 6/7] clk: en7523: move en7581_reset_register() in en7581_clk_hw_init() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-6-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Move en7581_reset_register routine in en7581_clk_hw_init() since reset feature is supported just by EN7581 SoC. Get rid of reset struct in en_clk_soc_data data struct. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 93 +++++++++++++++++------------------------------- 1 file changed, 33 insertions(+), 60 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index fdd8ea989ed2..60dc938144d7 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -76,11 +76,6 @@ struct en_rst_data { struct en_clk_soc_data { const struct clk_ops pcie_ops; - struct { - const u16 *bank_ofs; - const u16 *idx_map; - u16 idx_map_nr; - } reset; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); }; @@ -595,32 +590,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } -static int en7581_clk_hw_init(struct platform_device *pdev, - struct clk_hw_onecell_data *clk_data) -{ - void __iomem *np_base; - struct regmap *map; - u32 val; - - map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); - if (IS_ERR(map)) - return PTR_ERR(map); - - np_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); - - en7581_register_clocks(&pdev->dev, clk_data, map, np_base); - - val = readl(np_base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); - - return 0; -} - static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -670,23 +639,18 @@ static int en7523_reset_xlate(struct reset_controller_dev *rcdev, return rst_data->idx_map[reset_spec->args[0]]; } -static const struct reset_control_ops en7523_reset_ops = { +static const struct reset_control_ops en7581_reset_ops = { .assert = en7523_reset_assert, .deassert = en7523_reset_deassert, .status = en7523_reset_status, }; -static int en7523_reset_register(struct platform_device *pdev, - const struct en_clk_soc_data *soc_data) +static int en7581_reset_register(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct en_rst_data *rst_data; void __iomem *base; - /* no reset lines available */ - if (!soc_data->reset.idx_map_nr) - return 0; - base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) return PTR_ERR(base); @@ -695,13 +659,13 @@ static int en7523_reset_register(struct platform_device *pdev, if (!rst_data) return -ENOMEM; - rst_data->bank_ofs = soc_data->reset.bank_ofs; - rst_data->idx_map = soc_data->reset.idx_map; + rst_data->bank_ofs = en7581_rst_ofs; + rst_data->idx_map = en7581_rst_map; rst_data->base = base; - rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr; + rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate = en7523_reset_xlate; - rst_data->rcdev.ops = &en7523_reset_ops; + rst_data->rcdev.ops = &en7581_reset_ops; rst_data->rcdev.of_node = dev->of_node; rst_data->rcdev.of_reset_n_cells = 1; rst_data->rcdev.owner = THIS_MODULE; @@ -710,6 +674,32 @@ static int en7523_reset_register(struct platform_device *pdev, return devm_reset_controller_register(dev, &rst_data->rcdev); } +static int en7581_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *np_base; + struct regmap *map; + u32 val; + + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + np_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7581_register_clocks(&pdev->dev, clk_data, map, np_base); + + val = readl(np_base + REG_NP_SCU_SSTR); + val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + writel(val, np_base + REG_NP_SCU_SSTR); + val = readl(np_base + REG_NP_SCU_PCIC); + writel(val | 3, np_base + REG_NP_SCU_PCIC); + + return en7581_reset_register(pdev); +} + static int en7523_clk_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -728,19 +718,7 @@ static int en7523_clk_probe(struct platform_device *pdev) if (r) return r; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n", - pdev->name); - - r = en7523_reset_register(pdev, soc_data); - if (r) { - of_clk_del_provider(node); - return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n", - pdev->name); - } - - return 0; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } static const struct en_clk_soc_data en7523_data = { @@ -758,11 +736,6 @@ static const struct en_clk_soc_data en7581_data = { .enable = en7581_pci_enable, .disable = en7581_pci_disable, }, - .reset = { - .bank_ofs = en7581_rst_ofs, - .idx_map = en7581_rst_map, - .idx_map_nr = ARRAY_SIZE(en7581_rst_map), - }, .hw_init = en7581_clk_hw_init, }; From patchwork Tue Sep 3 21:39:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789339 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED95219CC2F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rkEN7c+Q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A49CC4CEC4; Tue, 3 Sep 2024 21:40:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399629; bh=AdkbPzAh+zDtLdmmxzCPVT53dh7L9hVnwre5LDtz2N0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rkEN7c+QLFi3PkKiTLLPiJSJI/+KkD3tRMmDSlF+iGIFbbliG0HzyShYCEdPFHmz0 eKnw9KanqOTKrtxu+LL8bEwRPwQFDdaqaTpbcLadTtnakLvhwYYY0PwhCZMNg2r0n6 qSIjVF06hWYuskyMD22r16eoHpgwOOjBRtBFVoOO7sI+AdT2C8C+KO0XmRzoWOy7nX mifRmc+d5ZwKOtuCUrIsYL/p3eWht66l2zvhJg6vnUVdNnyt8pOsDLgUVKVXaoRTmS jhXa96/a5YKKvhF7YIo71xJ9d5sAbWu2UkLBMaUArPmgW0hNC2cLd9kw6qQtn2oD01 BW2/f8YyEPlrQ== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:51 +0200 Subject: [PATCH v2 7/7] clk: en7523: map io region in a single block Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-7-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Map all clock-controller memory region in a single block. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 60dc938144d7..e52c5460e927 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -39,8 +39,8 @@ #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) #define REG_CRYPTO_CLKSRC2 0x20c -#define REG_RST_CTRL2 0x00 -#define REG_RST_CTRL1 0x04 +#define REG_RST_CTRL2 0x830 +#define REG_RST_CTRL1 0x834 struct en_clk_desc { int id; @@ -645,15 +645,9 @@ static const struct reset_control_ops en7581_reset_ops = { .status = en7523_reset_status, }; -static int en7581_reset_register(struct platform_device *pdev) +static int en7581_reset_register(struct device *dev, void __iomem *base) { - struct device *dev = &pdev->dev; struct en_rst_data *rst_data; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(base)) - return PTR_ERR(base); rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); if (!rst_data) @@ -677,27 +671,27 @@ static int en7581_reset_register(struct platform_device *pdev) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - void __iomem *np_base; struct regmap *map; + void __iomem *base; u32 val; map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) return PTR_ERR(map); - np_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); - en7581_register_clocks(&pdev->dev, clk_data, map, np_base); + en7581_register_clocks(&pdev->dev, clk_data, map, base); - val = readl(np_base + REG_NP_SCU_SSTR); + val = readl(base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); + writel(val, base + REG_NP_SCU_SSTR); + val = readl(base + REG_NP_SCU_PCIC); + writel(val | 3, base + REG_NP_SCU_PCIC); - return en7581_reset_register(pdev); + return en7581_reset_register(&pdev->dev, base); } static int en7523_clk_probe(struct platform_device *pdev)