From patchwork Thu Sep 5 11:55:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13792218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1257ACD5BB8 for ; Thu, 5 Sep 2024 11:53:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB4E310E870; Thu, 5 Sep 2024 11:53:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bOB2H1uS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id B0B4710E86D; Thu, 5 Sep 2024 11:53:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725537209; x=1757073209; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AgOW4veXAB76SiSiFGkCZJiW/UQ5sn7PmYs6LJYxWTw=; b=bOB2H1uSVkmE7osR0mJw4bpaB4HWx74Tc9vyFkgLXrp9KcyME/gipCjB O9u5Oj1H1jtccbAQaGTlShpy1oj8I9U24rLzn2ROaHNm3NpGUlDteR1tS ltbsxjPFfyufvfMqPgoVQFTtPebUVrZTy51vAhrO8LwPCbCtjr9/j2TkH OwZIL+fNLQDNEUMYb/ZB+anryO/b6MYca7GjbWwIbwl+xGpZzFRCH5hdH eY83/ir0Fj/zP7ettp0BSDSlzYtS23TAvVIsrR5jvuknoosrKyGtl99rM 2EVW5nR7ED8o4Sx7tGwBQvgHH7tddckQDN69IivQoDGsQz77ngTdoqp8Y A==; X-CSE-ConnectionGUID: hcKK2bM9R4Gf20/WcKh/JA== X-CSE-MsgGUID: m1Wyn/L0RRafJVhLuR5MMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11185"; a="24406108" X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="24406108" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:29 -0700 X-CSE-ConnectionGUID: M2orQk67SkehIFIg6QflkA== X-CSE-MsgGUID: 0XzCzIkATsmc6LlLnEIGMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="65918144" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:28 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 1/5] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14 Date: Thu, 5 Sep 2024 17:25:01 +0530 Message-ID: <20240905115505.3629087-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> References: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" LINK_N register has bits 31:24 for extended link N value used for HDMI2.1 and for an alternate mode of operation of DP TG DDA (Bspec:50488). Add support for these extra bits. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 31 +++++++++++++++---- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b4ef4d59da1a..60cdd7a37b03 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2595,6 +2595,8 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, compute_m_n(&m_n->link_m, &m_n->link_n, pixel_clock, link_symbol_clock, 0x80000); + + m_n->link_n_ext = 0; } void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) @@ -2632,6 +2634,7 @@ void intel_set_m_n(struct drm_i915_private *i915, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { + u8 link_n_ext = 0; intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(i915, data_n_reg, m_n->data_n); intel_de_write(i915, link_m_reg, m_n->link_m); @@ -2639,7 +2642,11 @@ void intel_set_m_n(struct drm_i915_private *i915, * On BDW+ writing LINK_N arms the double buffered update * of all the M/N registers, so it must be written last. */ - intel_de_write(i915, link_n_reg, m_n->link_n); + + if (DISPLAY_VER(i915) >= 14 && m_n->link_n_ext) + link_n_ext = PIPE_LINK_N1_EXTENDED(m_n->link_n_ext); + + intel_de_write(i915, link_n_reg, m_n->link_n | link_n_ext); } bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, @@ -3346,8 +3353,17 @@ void intel_get_m_n(struct drm_i915_private *i915, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { + u32 link_n; + m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; + + link_n = intel_de_read(i915, link_n_reg); + m_n->link_n = link_n & DATA_LINK_M_N_MASK; + if (DISPLAY_VER(i915) >= 14) + m_n->link_n_ext = REG_FIELD_GET(PIPE_LINK_N1_EXTENDED_MASK, link_n); + else + m_n->link_n_ext = 0; + m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; @@ -4843,7 +4859,8 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n, m_n->data_m == m2_n2->data_m && m_n->data_n == m2_n2->data_n && m_n->link_m == m2_n2->link_m && - m_n->link_n == m2_n2->link_n; + m_n->link_n == m2_n2->link_n && + m_n->link_n_ext == m2_n2->link_n_ext; } static bool @@ -5133,18 +5150,20 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (!intel_compare_link_m_n(¤t_config->name, \ &pipe_config->name)) { \ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ - "(expected tu %i data %i/%i link %i/%i, " \ - "found tu %i, data %i/%i link %i/%i)", \ + "(expected tu %i data %i/%i link %i/%i link_n_ext %i, " \ + "found tu %i, data %i/%i link %i/%i link_n_ext %i)", \ current_config->name.tu, \ current_config->name.data_m, \ current_config->name.data_n, \ current_config->name.link_m, \ current_config->name.link_n, \ + current_config->name.link_n_ext, \ pipe_config->name.tu, \ pipe_config->name.data_m, \ pipe_config->name.data_n, \ pipe_config->name.link_m, \ - pipe_config->name.link_n); \ + pipe_config->name.link_n, \ + pipe_config->name.link_n_ext); \ ret = false; \ } \ } while (0) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f29e5dc3db91..1328e2e89786 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1028,6 +1028,7 @@ struct intel_link_m_n { u32 data_n; u32 link_m; u32 link_n; + u8 link_n_ext; }; struct intel_csc_matrix { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 41f4350a7c6c..941d273dbf8c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2172,6 +2172,8 @@ #define _PIPEB_DATA_N2 0x6103c #define _PIPEB_LINK_M1 0x61040 #define _PIPEB_LINK_N1 0x61044 +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24) +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val)) #define _PIPEB_LINK_M2 0x61048 #define _PIPEB_LINK_N2 0x6104c From patchwork Thu Sep 5 11:55:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13792219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4334BCD5BAE for ; Thu, 5 Sep 2024 11:53:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B9CE810E873; Thu, 5 Sep 2024 11:53:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MB5CwTfq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8AFDD10E872; Thu, 5 Sep 2024 11:53:30 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="65918153" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:29 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 2/5] drm/i915/display: Limit m/n ratio to 10 for display > 12 Date: Thu, 5 Sep 2024 17:25:02 +0530 Message-ID: <20240905115505.3629087-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> References: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per Bspec:49266 for DISPLAY > 12 which support higher link rates have a limitation: If the CEILING( Link M / Link N ) ratio is greater than 10.0, then hardware cannot support the given resolution / refresh rate at the given configuration. Modify the helper to compute m_n, to check for the max link_m/n ratio for the given platforms, and return error code in case the resolution/refresh rate is not supported. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++++++- drivers/gpu/drm/i915/display/intel_display.h | 10 +++-- drivers/gpu/drm/i915/display/intel_dp.c | 39 +++++++++++++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 34 ++++++++++------- drivers/gpu/drm/i915/display/intel_fdi.c | 15 ++++---- 5 files changed, 87 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 60cdd7a37b03..a28500d5f969 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2569,8 +2569,15 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n, intel_reduce_m_n_ratio(ret_m, ret_n); } -void -intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, +static int +get_max_link_m_n_ratio(void) +{ + return 10; +} + +int +intel_link_compute_m_n(struct intel_display *display, + u16 bits_per_pixel_x16, int nlanes, int pixel_clock, int link_clock, int bw_overhead, struct intel_link_m_n *m_n) @@ -2579,6 +2586,7 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, bw_overhead); u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); + int link_m_n_ratio, max_link_m_n_ratio; /* * Windows/BIOS uses fixed M/N values always. Follow suit. @@ -2597,6 +2605,23 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 0x80000); m_n->link_n_ext = 0; + + if (DISPLAY_VER(display) < 12) + return 0; + + /* Check for Link M/N ratio for Display >= 12 */ + max_link_m_n_ratio = get_max_link_m_n_ratio(); + + link_m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_m); + + if (link_m_n_ratio > max_link_m_n_ratio) { + drm_dbg_kms(display->drm, + "Cannot support Link_m/Link_n ratio : %d > max_link_m_n_ratio\n", + link_m_n_ratio); + return -EINVAL; + } + + return 0; } void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b21d9578d5db..483a8f6cd69b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -51,6 +51,7 @@ struct i915_gtt_view; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_digital_port; struct intel_dp; struct intel_encoder; @@ -406,10 +407,11 @@ int intel_atomic_add_affected_planes(struct intel_atomic_state *state, struct intel_crtc *crtc); u8 intel_calc_active_pipes(struct intel_atomic_state *state, u8 active_pipes); -void intel_link_compute_m_n(u16 bpp, int nlanes, - int pixel_clock, int link_clock, - int bw_overhead, - struct intel_link_m_n *m_n); +int intel_link_compute_m_n(struct intel_display *display, + u16 bpp, int nlanes, + int pixel_clock, int link_clock, + int bw_overhead, + struct intel_link_m_n *m_n); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); enum drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a1fcedfd404b..d0c819807bfc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2847,15 +2847,17 @@ static bool can_enable_drrs(struct intel_connector *connector, intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; } -static void +static int intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, int link_bpp_x16) { struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); const struct drm_display_mode *downclock_mode = intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); int pixel_clock; + int ret; /* * FIXME all joined pipes share the same transcoder. @@ -2867,7 +2869,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) intel_zero_m_n(&pipe_config->dp_m2_n2); - return; + return 0; } if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) @@ -2879,14 +2881,18 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, if (pipe_config->splitter.enable) pixel_clock /= pipe_config->splitter.link_count; - intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, - pipe_config->port_clock, - intel_dp_bw_fec_overhead(pipe_config->fec_enable), - &pipe_config->dp_m2_n2); + ret = intel_link_compute_m_n(display, link_bpp_x16, pipe_config->lane_count, pixel_clock, + pipe_config->port_clock, + intel_dp_bw_fec_overhead(pipe_config->fec_enable), + &pipe_config->dp_m2_n2); + if (ret) + return ret; /* FIXME: abstract this better */ if (pipe_config->splitter.enable) pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; + + return 0; } static bool intel_dp_has_audio(struct intel_encoder *encoder, @@ -3009,6 +3015,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -3090,12 +3097,14 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_audio_compute_config(encoder, pipe_config, conn_state); - intel_link_compute_m_n(link_bpp_x16, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - pipe_config->port_clock, - intel_dp_bw_fec_overhead(pipe_config->fec_enable), - &pipe_config->dp_m_n); + ret = intel_link_compute_m_n(display, link_bpp_x16, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + pipe_config->port_clock, + intel_dp_bw_fec_overhead(pipe_config->fec_enable), + &pipe_config->dp_m_n); + if (ret) + return ret; /* FIXME: abstract this better */ if (pipe_config->splitter.enable) @@ -3108,7 +3117,11 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_compute_as_sdp(intel_dp, pipe_config); intel_psr_compute_config(intel_dp, pipe_config, conn_state); intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); - intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); + + ret = intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); + if (ret) + return ret; + intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 15541932b809..317eb04bd8c6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -122,23 +122,28 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable)); } -static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, - const struct intel_connector *connector, - int overhead, - int bpp_x16, - struct intel_link_m_n *m_n) +static int intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, + const struct intel_connector *connector, + int overhead, + int bpp_x16, + struct intel_link_m_n *m_n) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_display *display = to_intel_display(connector); + int ret; /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */ - intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, - adjusted_mode->crtc_clock, - crtc_state->port_clock, - overhead, - m_n); + ret = intel_link_compute_m_n(display, bpp_x16, crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + overhead, m_n); + if (ret) + return ret; m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); + + return ret; } static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead) @@ -220,10 +225,11 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, true, dsc, link_bpp_x16); - intel_dp_mst_compute_m_n(crtc_state, connector, - local_bw_overhead, - link_bpp_x16, - &crtc_state->dp_m_n); + if (!intel_dp_mst_compute_m_n(crtc_state, connector, + local_bw_overhead, + link_bpp_x16, + &crtc_state->dp_m_n)) + continue; /* * The TU size programmed to the HW determines which slots in diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 222cd0e1a2bc..d7f0a967c259 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -323,8 +323,9 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *i915 = to_i915(dev); + struct intel_display *display = to_intel_display(pipe_config); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int lane, link_bw, fdi_dotclock; + int lane, link_bw, fdi_dotclock, ret; /* FDI is a binary signal running at ~2.7GHz, encoding * each output octet as 10 bits. The actual frequency @@ -342,13 +343,13 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, pipe_config->fdi_lanes = lane; - intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), - lane, fdi_dotclock, - link_bw, - intel_dp_bw_fec_overhead(false), - &pipe_config->fdi_m_n); + ret = intel_link_compute_m_n(display, fxp_q4_from_int(pipe_config->pipe_bpp), + lane, fdi_dotclock, + link_bw, + intel_dp_bw_fec_overhead(false), + &pipe_config->fdi_m_n); - return 0; + return ret; } static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state, From patchwork Thu Sep 5 11:55:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13792220 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F09FCD5BB8 for ; Thu, 5 Sep 2024 11:53:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B341D10E878; Thu, 5 Sep 2024 11:53:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Mi+rZCyV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26F3410E876; Thu, 5 Sep 2024 11:53:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725537212; x=1757073212; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DjAzBucOGtdUGlG3WN2yWhPXGbS4T/K+A7wPpeewaO0=; b=Mi+rZCyVWNa6XIdMK/BzDCwSfRdI/2m9fRH2oTiDTjTLcraHXYqOUcnj zdcfse/emcgEK+IA7phRIV4wd5+DsJ+AFMJWCWZ91S0j0l+rPby4R78+B WgHgywjq7oqlDVUVrR85Ns1AZkqqPmh/H1iSBwsULw2BcKjB3s+kUs7e0 Wbw2Alfw51u/IE2nekQMfJ0xp+r49UKEpU7eGtgF53wt3BnZHCJDCciVI dkJf4fbbir3EGzRa+I6j1YOTYP0ar7uV2YbpjCC1PzNHijxdbNC5xmlgP 2RuxWFrO9Er11FC84DZmf20fG6W61U8wpFkjvbHqoaDlS7XLUzwJwGHqY Q==; X-CSE-ConnectionGUID: JmgoAQQ+R4y5+JwsHQP1rg== X-CSE-MsgGUID: 2+B9rT6IQamaJJXvMGxdOg== X-IronPort-AV: E=McAfee;i="6700,10204,11185"; a="24406113" X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="24406113" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:32 -0700 X-CSE-ConnectionGUID: 6eMfEI+oQNqnTenAy6clmQ== X-CSE-MsgGUID: E34MdBvLQcunpJWf23yCtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="65918167" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:31 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 3/5] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10 Date: Thu, 5 Sep 2024 17:25:03 +0530 Message-ID: <20240905115505.3629087-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> References: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To support Link M/N ratio between 10.0 and 15.0, for some BMG ultrajoiner cases we need Wa_14021768792. To bypass the hardware limitation within the Timing Generator DDA (TGDDA), we need to program the LINKM and LINKN registers as defined in the WA. Along with this we also need relvant bits in HDMI_EMP_DATA and CHICKEN_TRANS regs. Add the bits for the WA and a new member 'bmg_bypass_m_n_ratio_limit' to track if we need to bypass the Link M/N ratio limit in intel_link_m_n structure. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 79 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 5 ++ 3 files changed, 83 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a28500d5f969..d23f90096b0e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2683,6 +2683,19 @@ bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); } +static +void bmg_bypass_m_n_limit_write(struct intel_crtc *crtc, + enum transcoder transcoder, + const struct intel_link_m_n *m_n) +{ + struct intel_display *display = to_intel_display(crtc); + int m_n_frac = m_n->link_m % m_n->link_n; + enum pipe pipe = crtc->pipe; + + intel_de_rmw(display, MTL_CHICKEN_TRANS(transcoder), 0, BMG_DP_BYPASS_M_N_LIMIT); + intel_de_write(display, HDMI_EMP_DATA(pipe), m_n_frac); +} + void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, const struct intel_link_m_n *m_n) @@ -2700,6 +2713,9 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, intel_set_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); + + if (m_n->bypass_m_n_ratio_limit) + bmg_bypass_m_n_limit_write(crtc, transcoder, m_n); } void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, @@ -2716,6 +2732,9 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), PIPE_LINK_N2(dev_priv, transcoder)); + + if (m_n->bypass_m_n_ratio_limit) + bmg_bypass_m_n_limit_write(crtc, transcoder, m_n); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) @@ -3394,12 +3413,51 @@ void intel_get_m_n(struct drm_i915_private *i915, m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; } +static +void bmg_bypass_m_n_limit_read(struct intel_crtc *crtc, + enum transcoder transcoder, + struct intel_link_m_n *m_n) +{ + struct intel_display *display = to_intel_display(crtc); + enum pipe pipe = crtc->pipe; + u32 chicken_trans, m_n_frac; + + chicken_trans = intel_de_read(display, MTL_CHICKEN_TRANS(transcoder)); + m_n_frac = intel_de_read(display, HDMI_EMP_DATA(pipe)); + + if ((chicken_trans & BMG_DP_BYPASS_M_N_LIMIT) && + m_n_frac == (m_n->link_m % m_n->link_n)) + m_n->bypass_m_n_ratio_limit = true; +} + +static +int bmg_can_bypass_m_n_limit(struct intel_display *display, + int m_n_ratio, + enum pipe pipe) +{ + struct drm_i915_private *i915 = to_i915(display->drm); + + if (DISPLAY_VER(display) != 14 || !IS_DGFX(i915) || + !IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER)) + return false; + + if (pipe != PIPE_A) + return false; + + if (m_n_ratio > 15) + return false; + + return true; +} + void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; + int m_n_ratio; if (DISPLAY_VER(dev_priv) >= 5) intel_get_m_n(dev_priv, m_n, @@ -3411,6 +3469,11 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, intel_get_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); + + m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n); + + if (bmg_can_bypass_m_n_limit(display, m_n_ratio, pipe)) + bmg_bypass_m_n_limit_read(crtc, transcoder, m_n); } void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, @@ -3418,6 +3481,9 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); + enum pipe pipe = crtc->pipe; + int m_n_ratio; if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) return; @@ -3427,6 +3493,11 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), PIPE_LINK_N2(dev_priv, transcoder)); + + m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n); + + if (bmg_can_bypass_m_n_limit(display, m_n_ratio, pipe)) + bmg_bypass_m_n_limit_read(crtc, transcoder, m_n); } static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) @@ -5175,20 +5246,22 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (!intel_compare_link_m_n(¤t_config->name, \ &pipe_config->name)) { \ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ - "(expected tu %i data %i/%i link %i/%i link_n_ext %i, " \ - "found tu %i, data %i/%i link %i/%i link_n_ext %i)", \ + "(expected tu %i data %i/%i link %i/%i link_n_ext %i bypass_m_n_ratio_limit %s, " \ + "found tu %i, data %i/%i link %i/%i link_n_ext %i bypass_m_n_ratio_limit %s)", \ current_config->name.tu, \ current_config->name.data_m, \ current_config->name.data_n, \ current_config->name.link_m, \ current_config->name.link_n, \ current_config->name.link_n_ext, \ + str_yes_no(current_config->name.bypass_m_n_ratio_limit), \ pipe_config->name.tu, \ pipe_config->name.data_m, \ pipe_config->name.data_n, \ pipe_config->name.link_m, \ pipe_config->name.link_n, \ - pipe_config->name.link_n_ext); \ + pipe_config->name.link_n_ext, \ + str_yes_no(pipe_config->name.bypass_m_n_ratio_limit)); \ ret = false; \ } \ } while (0) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1328e2e89786..d7ea7d437a6d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1029,6 +1029,8 @@ struct intel_link_m_n { u32 link_m; u32 link_n; u8 link_n_ext; + /* Wa_14021768792 for linkm/n ratio > 10 */ + bool bypass_m_n_ratio_limit; }; struct intel_csc_matrix { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 941d273dbf8c..4e16a129d891 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1110,6 +1110,10 @@ #define _TRANS_VSYNCSHIFT_A 0x60028 #define _TRANS_MULT_A 0x6002c +#define _HDMI_EMP_DATA_A 0x600d8 +#define _HDMI_EMP_DATA_B 0x610d8 +#define HDMI_EMP_DATA(pipe) _MMIO_PIPE(pipe, _HDMI_EMP_DATA_A, _HDMI_EMP_DATA_B) + /* Pipe/transcoder B timing regs */ #define _TRANS_HTOTAL_B 0x61000 #define _TRANS_HBLANK_B 0x61004 @@ -2802,6 +2806,7 @@ #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) #define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) +#define BMG_DP_BYPASS_M_N_LIMIT REG_BIT(11) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) #define HDCP_LINE_REKEY_DISABLE REG_BIT(0) From patchwork Thu Sep 5 11:55:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13792221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69942CD5BBA for ; Thu, 5 Sep 2024 11:53:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0127610E879; Thu, 5 Sep 2024 11:53:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Unq/nAGL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id C876910E876; Thu, 5 Sep 2024 11:53:33 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="65918173" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:33 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 4/5] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10 Date: Thu, 5 Sep 2024 17:25:04 +0530 Message-ID: <20240905115505.3629087-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> References: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Handle the bypass logic for the M/N ratio limit for DP. Calculate the M/N ratio, check if it can bypass the limit, and set the appropriate flags for the workaround. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 1 - drivers/gpu/drm/i915/display/intel_display.h | 4 +++ drivers/gpu/drm/i915/display/intel_dp.c | 31 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 5 ++++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++- 5 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d23f90096b0e..f55a85f04ce5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3430,7 +3430,6 @@ void bmg_bypass_m_n_limit_read(struct intel_crtc *crtc, m_n->bypass_m_n_ratio_limit = true; } -static int bmg_can_bypass_m_n_limit(struct intel_display *display, int m_n_ratio, enum pipe pipe) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 483a8f6cd69b..caf7549a3352 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -589,4 +589,8 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); +int bmg_can_bypass_m_n_limit(struct intel_display *display, + int m_n_ratio, + enum pipe pipe); + #endif diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d0c819807bfc..c741b3409fa6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2847,6 +2847,27 @@ static bool can_enable_drrs(struct intel_connector *connector, intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; } +bool +intel_dp_bmg_bypass_m_n_limit(struct intel_display *display, + struct intel_link_m_n *m_n, + enum pipe pipe) +{ + int m_n_ratio, m_n_frac; + + m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n); + + if (!bmg_can_bypass_m_n_limit(display, m_n_ratio, pipe)) + return false; + + m_n_frac = m_n->link_m % m_n->link_n; + + m_n->link_n_ext = m_n_ratio | (m_n_ratio + (m_n_frac > 0 ? 1 : 0)) << 4; + + m_n->bypass_m_n_ratio_limit = true; + + return true; +} + static int intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, @@ -2856,6 +2877,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_display *display = to_intel_display(connector); const struct drm_display_mode *downclock_mode = intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + enum pipe pipe = crtc->pipe; int pixel_clock; int ret; @@ -2885,7 +2908,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, pipe_config->port_clock, intel_dp_bw_fec_overhead(pipe_config->fec_enable), &pipe_config->dp_m2_n2); - if (ret) + + if (ret && !intel_dp_bmg_bypass_m_n_limit(display, &pipe_config->dp_m2_n2, pipe)) return ret; /* FIXME: abstract this better */ @@ -3021,6 +3045,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); const struct drm_display_mode *fixed_mode; struct intel_connector *connector = intel_dp->attached_connector; + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + enum pipe pipe = crtc->pipe; int ret = 0, link_bpp_x16; if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) @@ -3103,7 +3129,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, pipe_config->port_clock, intel_dp_bw_fec_overhead(pipe_config->fec_enable), &pipe_config->dp_m_n); - if (ret) + + if (ret && !intel_dp_bmg_bypass_m_n_limit(display, &pipe_config->dp_m_n, pipe)) return ret; /* FIXME: abstract this better */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 1b9aaddd8c35..92acb6a9eb4b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -20,8 +20,10 @@ struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; +struct intel_display; struct intel_dp; struct intel_encoder; +struct intel_link_m_n; struct link_config_limits { int min_rate, max_rate; @@ -203,5 +205,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); +bool intel_dp_bmg_bypass_m_n_limit(struct intel_display *display, + struct intel_link_m_n *m_n, + enum pipe pipe); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 317eb04bd8c6..817895b427ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -131,6 +131,8 @@ static int intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; struct intel_display *display = to_intel_display(connector); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; int ret; /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */ @@ -138,7 +140,8 @@ static int intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, adjusted_mode->crtc_clock, crtc_state->port_clock, overhead, m_n); - if (ret) + + if (ret && !intel_dp_bmg_bypass_m_n_limit(display, m_n, pipe)) return ret; m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); From patchwork Thu Sep 5 11:55:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13792222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C841ACD5BB7 for ; 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X-CSE-ConnectionGUID: sJJX9EoyS46jMjkTOsDyfA== X-CSE-MsgGUID: qaz/aVIrS56cpiIRJvW58g== X-IronPort-AV: E=McAfee;i="6700,10204,11185"; a="24406126" X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="24406126" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:35 -0700 X-CSE-ConnectionGUID: azrI1p4sS+qd7vBixXRZrQ== X-CSE-MsgGUID: nfcGNFd/Rxi07a+XRoII6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="65918177" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 04:53:34 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@linux.intel.com Subject: [PATCH 5/5] drm/i915: Add Wa_14021768792 as per WA framework Date: Thu, 5 Sep 2024 17:25:05 +0530 Message-ID: <20240905115505.3629087-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> References: <20240905115505.3629087-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Modify the condition for WA as per Xe WA framework. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_wa.h | 2 ++ drivers/gpu/drm/xe/display/xe_display_wa.c | 5 +++++ drivers/gpu/drm/xe/xe_wa_oob.rules | 1 + 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f55a85f04ce5..4496ba30d64d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -75,6 +75,7 @@ #include "intel_display_driver.h" #include "intel_display_power.h" #include "intel_display_types.h" +#include "intel_display_wa.h" #include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_link_training.h" @@ -3436,8 +3437,7 @@ int bmg_can_bypass_m_n_limit(struct intel_display *display, { struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) != 14 || !IS_DGFX(i915) || - !IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER)) + if (!intel_display_needs_wa_14021768792(i915)) return false; if (pipe != PIPE_A) diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h index be644ab6ae00..10c1b5787d05 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.h +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h @@ -14,8 +14,10 @@ void intel_display_wa_apply(struct drm_i915_private *i915); #ifdef I915 static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; } +static inline bool intel_display_needs_wa_14021768792(struct drm_i915_private *i915) { return false; } #else bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915); +bool intel_display_needs_wa_14021768792(struct drm_i915_private *i915); #endif #endif diff --git a/drivers/gpu/drm/xe/display/xe_display_wa.c b/drivers/gpu/drm/xe/display/xe_display_wa.c index 68e3d1959ad6..c4728e61e190 100644 --- a/drivers/gpu/drm/xe/display/xe_display_wa.c +++ b/drivers/gpu/drm/xe/display/xe_display_wa.c @@ -14,3 +14,8 @@ bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return XE_WA(xe_root_mmio_gt(i915), 16023588340); } + +bool intel_display_needs_wa_14021768792(struct drm_i915_private *i915) +{ + return XE_WA(xe_root_mmio_gt(i915), 14021768792); +} diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules index 920ca5060146..a7cc2c2d98d0 100644 --- a/drivers/gpu/drm/xe/xe_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules @@ -37,3 +37,4 @@ 16023588340 GRAPHICS_VERSION(2001) 14019789679 GRAPHICS_VERSION(1255) GRAPHICS_VERSION_RANGE(1270, 2004) +14021768792 PLATFORM(BATTLEMAGE), GRAPHICS_STEP(C0, FOREVER)