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AJvYcCVcjkSruH7i9emaePmMOhpOf5en8Jc1bJJ2YSAzrkBl7teN569GojDaV2Osq2YzN8hvr0BYt9r/0DnUTuKhvvt8@lists.infradead.org X-Gm-Message-State: AOJu0YwyN5yrFA+V7zNyJIr2Eby7Kwzru1QEOZ0PJYNiU2aH4ZTZNrdw EDZCdctOHaco58bbLe8GMzW/Wv6E5JFLCAMxoXwkautfvewPjpor X-Google-Smtp-Source: AGHT+IFfjtobqQPMkb9OKLlg1I5PWajndb+eLtuLMdvhxBWmOQ4JJ0fKh+2FCmn3asUIzAuiLIKtnw== X-Received: by 2002:a05:6a00:2d05:b0:706:aa39:d5c1 with SMTP id d2e1a72fcca58-719263eab2cmr11149885b3a.8.1726256066430; Fri, 13 Sep 2024 12:34:26 -0700 (PDT) Received: from amenon-us-dl.hsd1.ca.comcast.net ([2601:646:a002:44b0:385b:1e44:bb9b:db08]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-719090d08a5sm6407832b3a.212.2024.09.13.12.34.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 12:34:25 -0700 (PDT) From: Aakash Menon X-Google-Original-From: Aakash Menon To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, aakash.menon@protempis.com, horms@kernel.org, horatiu.vultur@microchip.com Cc: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] net: sparx5: Fix invalid timestamps Date: Fri, 13 Sep 2024 12:33:57 -0700 Message-ID: <20240913193357.21899-1-aakash.menon@protempis.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240913_123428_726606_1E972BC6 X-CRM114-Status: GOOD ( 12.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Bit 270-271 are occasionally unexpectedly set by the hardware. This issue was observed with 10G SFPs causing huge time errors (> 30ms) in PTP. Only 30 bits are needed for the nanosecond part of the timestamp, clear 2 most significant bits before extracting timestamp from the internal frame header. Signed-off-by: Aakash Menon --- drivers/net/ethernet/microchip/sparx5/sparx5_packet.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c index f3f5fb420468..a05263488851 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c @@ -45,8 +45,12 @@ void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) fwd = (fwd >> 5); info->src_port = FIELD_GET(GENMASK(7, 1), fwd); + /* + * Bit 270-271 are occasionally unexpectedly set by the hardware, + * clear bits before extracting timestamp + */ info->timestamp = - ((u64)xtr_hdr[2] << 24) | + ((u64)(xtr_hdr[2] & 0x3F) << 24) | ((u64)xtr_hdr[3] << 16) | ((u64)xtr_hdr[4] << 8) | ((u64)xtr_hdr[5] << 0);